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spi: cadence-qspi: add logging for clk configuration changes

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Signed-off-by: Heinrich Toews <ht@twx-software.de>
This commit is contained in:
Heinrich Toews
2026-02-24 16:45:17 +01:00
parent f3d8580745
commit 4e58c348b2
1 changed files with 16 additions and 0 deletions
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drivers/spi/spi-cadence-quadspi.c
+16
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@@ -1195,6 +1195,7 @@ static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
void __iomem *reg_base = cqspi->iobase;
u32 reg, div;
u32 actual_clk;
/* Recalculate the baudrate divisor based on QSPI specification. */
div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
@@ -1207,10 +1208,25 @@ static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
cqspi->sclk, ref_clk_hz/((div+1)*2));
}
/* Calculate actual clock for logging purposes */
actual_clk = ref_clk_hz / (2 * (div + 1));
dev_info(&cqspi->pdev->dev,
"CQSPI Clock Config: Ref=%u Hz, Target=%u Hz, Divisor=%u, Result=%u Hz\n",
ref_clk_hz, cqspi->sclk, div, actual_clk);
reg = readl(reg_base + CQSPI_REG_CONFIG);
/* Log old register value for deep debugging */
dev_info(&cqspi->pdev->dev, "Old CONFIG_REG: 0x%08x\n", reg);
reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
writel(reg, reg_base + CQSPI_REG_CONFIG);
dev_info(&cqspi->pdev->dev, "New CONFIG_REG: 0x%08x (BaudDiv field updated)\n",
readl(reg_base + CQSPI_REG_CONFIG));
}
static void cqspi_readdata_capture(struct cqspi_st *cqspi,