mtd: spi-nor: everspin: implement 200MHz Octal-STR mode for EM008LX
This patch enables high-speed Octal-STR (8s-8s-8s) operation at 200MHz for the Everspin EM008LX MRAM series. To maintain reliable boot-up, the device is identified at a safe frequency. Upon successful JEDEC ID verification, the driver escalates the clock frequency to 200MHz and synchronizes the dummy cycles. Key Improvements: - Added frequency escalation in params->setup() hook to 200MHz. - Implemented Octal register access (0x85/0x81) for configuration. - Synchronized dummy cycles to 20, as required for 200MHz operation. - Validated with Cadence OSPI controller using a 400MHz reference clock and a read-capture delay of 3-5 cycles. The resulting configuration achieves the maximum specified throughput of the Everspin MRAM while maintaining data integrity. Signed-off-by: Heinrich Toews <ht@twx-software.de>
This commit is contained in:
Heinrich Toews
@@ -183,6 +183,9 @@
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pinctrl-0 = <&ospi0_pins_default>;
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status = "okay";
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/* Setup the clock for 200 MHz (400 MHz Ref / 2) */
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assigned-clock-rates = <400000000>;
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/* Everspin Tech. EM008LXO
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* Order-No EM008LXOAB320IS1R
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*/
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@@ -196,21 +199,24 @@
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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/* 80 MHz Target */
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spi-max-frequency = <80000000>;
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/* 50 MHz for Startup */
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spi-max-frequency = <50000000>;
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/* PHY mode is highly recommended for >50MHz on Cadence controllers */
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/* 200 MHz needs a very precise sampling point.
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* Start with 4 or 5 since 125MHz already needed 3.
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*/
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cdns,read-delay = <5>;
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/* Enable PHY mode to assist controller internal clocking at
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* high speeds
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*/
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cdns,phy-mode;
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/* Read delay: Start with 0.
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If you get bit errors, try cdns,read-delay = <1>; */
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cdns,read-delay = <0>;
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/* Tighten timings for 80MHz operation (T=12.5ns) */
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cdns,tshsl-ns = <25>; /* Chip Select high pulse width */
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cdns,tsd2d-ns = <25>; /* Delay between two back-to-back transfers */
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cdns,tchsh-ns = <6>; /* CS# hold time */
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cdns,tslch-ns = <6>; /* CS# setup time */
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/* Tighten timings for 200 MHz (T=5ns) */
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cdns,tshsl-ns = <200>; /* CS# high pulse width (increased for stability) */
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cdns,tsd2d-ns = <200>; /* Delay between back-to-back transfers */
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cdns,tchsh-ns = <3>; /* CS# hold time */
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cdns,tslch-ns = <3>; /* CS# setup time */
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spi-rx-bus-width = <8>;
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spi-tx-bus-width = <8>;
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+132
-26
@@ -9,10 +9,19 @@
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#include <linux/spi/spi-mem.h>
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#include "core.h"
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#define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile configuration register */
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#define SPINOR_REG_MT_CFR0V 0x00 /* Address for Mode Configuration */
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#define SPINOR_REG_MT_CFR1V 0x01 /* Address for Dummy Cycle Configuration */
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#define SPINOR_MT_OCT_STR 0xB7 /* Enable Octal STR mode with DS */
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/* Optimization for 200 MHz: 20 Dummy Cycles are typically required */
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#define EVERSPIN_MRAM_DUMMY_CYCLES 8
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#define EVERSPIN_MRAM_DUMMY_CYCLES_FAST 20
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#define EVERSPIN_MRAM_SPEED_MHZ 200000000
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#define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile configuration register */
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#define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile configuration register */
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#define SPINOR_REG_MT_CFR0V 0x00 /* Address for Mode Configuration */
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#define SPINOR_REG_MT_CFR1V 0x01 /* Address for Dummy Cycle Configuration */
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#define SPINOR_MT_OCT_STR 0xB7 /* Enable Octal STR mode with DS */
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#define SPINOR_OP_EV_OCTAL_FAST_READ 0xCB /* Everspin Octal Fast Read (8-8-8) */
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#define SPINOR_OP_EV_OCTAL_PAGE_PROG 0x82 /* Everspin Octal Page Program (8-8-8) */
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/**
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* everspin_mram_software_reset - Software Reset in Single-SPI mode
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@@ -22,8 +31,8 @@ static int everspin_mram_software_reset(struct spi_nor *nor)
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struct spi_mem_op op;
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int ret;
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/* Software Reset Enable (0x66) */
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op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(0x66, 1),
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/* Software Reset Enable (SPINOR_OP_SRSTEN: 0x66) */
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op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 1),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_NO_DATA);
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@@ -32,8 +41,8 @@ static int everspin_mram_software_reset(struct spi_nor *nor)
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if (ret)
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return ret;
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/* Software Reset (0x99) */
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op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(0x99, 1),
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/* Software Reset (SPINOR_OP_SRST: 0x99) */
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op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 1),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_NO_DATA);
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@@ -63,6 +72,47 @@ static int everspin_mram_write_reg(struct spi_nor *nor, u32 addr, u8 val)
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return spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_1_1_1);
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}
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/**
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* everspin_mram_read_reg_octal - Reads a register in 8s-8s-8s mode
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* Uses Opcode 0x85, 3-byte address, and 8 dummy cycles.
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*/
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static int everspin_mram_read_reg_octal(struct spi_nor *nor, u32 addr, u8 *val)
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{
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_RD_ANY_REG, 8),
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SPI_MEM_OP_ADDR(3, addr, 8),
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SPI_MEM_OP_DUMMY(8, 8), /* Fixed 8 dummies for reg read */
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SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 8));
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int ret;
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ret = spi_nor_read_any_reg(nor, &op, SNOR_PROTO_8_8_8);
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if (ret)
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return ret;
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*val = nor->bouncebuf[0];
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return 0;
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}
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/**
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* everspin_mram_write_reg_octal - Writes a register in 8s-8s-8s mode
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* Uses Opcode 0x81, 3-byte address, and 0 dummy cycles.
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*/
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static int everspin_mram_write_reg_octal(struct spi_nor *nor, u32 addr, u8 val)
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{
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 8),
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SPI_MEM_OP_ADDR(3, addr, 8),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 8));
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nor->bouncebuf[0] = val;
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/* WREN is required before writing to volatile registers */
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spi_nor_write_enable(nor);
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return spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8);
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}
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/**
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* everspin_mram_unlock - Clears Block Protection bits
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*/
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@@ -92,7 +142,8 @@ static void everspin_mram_default_init(struct spi_nor *nor)
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*/
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everspin_mram_software_reset(nor);
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dev_info(nor->dev, "Starting Everspin MRAM initialization ...\n");
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dev_info(nor->dev, "Starting Everspin MRAM initialization (Octal-STR, %d Dummies) ...\n",
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EVERSPIN_MRAM_DUMMY_CYCLES);
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/* Initial SR1 Check */
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op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1),
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@@ -108,8 +159,8 @@ static void everspin_mram_default_init(struct spi_nor *nor)
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everspin_mram_unlock(nor);
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}
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/* Configuration: 8 dummy bytes */
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everspin_mram_write_reg(nor, SPINOR_REG_MT_CFR1V, 8);
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/* Configuration: Set Dummy Cycles in CFR1V */
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everspin_mram_write_reg(nor, SPINOR_REG_MT_CFR1V, EVERSPIN_MRAM_DUMMY_CYCLES);
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/* Verify WEL */
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ret = spi_nor_read_any_reg(nor, &op, SNOR_PROTO_1_1_1);
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@@ -127,8 +178,8 @@ static void everspin_mram_default_init(struct spi_nor *nor)
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/* Address: None */
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SPI_MEM_OP_NO_ADDR,
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/* Dummy: 8 cycles, sent on 8 lanes (as per your table) */
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SPI_MEM_OP_DUMMY(8, 8),
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/* EVERSPIN_MRAM_DUMMY_CYCLES cycles, sent on 8 lanes */
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SPI_MEM_OP_DUMMY(EVERSPIN_MRAM_DUMMY_CYCLES, 8),
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/* Data: 1 byte (Status), received on 8 lanes */
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SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 8)
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@@ -152,8 +203,8 @@ static void everspin_mram_default_init(struct spi_nor *nor)
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/* No address phase */
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SPI_MEM_OP_NO_ADDR,
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/* 8 Dummy Cycles, sent on 8 lanes */
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SPI_MEM_OP_DUMMY(8, 8),
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/* EVERSPIN_MRAM_DUMMY_CYCLES Dummy Cycles, sent on 8 lanes */
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SPI_MEM_OP_DUMMY(EVERSPIN_MRAM_DUMMY_CYCLES, 8),
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/* Read 3 bytes of ID data, received on 8 lanes */
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SPI_MEM_OP_DATA_IN(3, nor->bouncebuf, 8)
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@@ -183,6 +234,55 @@ static int everspin_mram_ready_noop(struct spi_nor *nor)
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return 1;
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}
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/**
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* everspin_mram_setup - Finalizes the SPI setup and escalates frequency
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* @nor: pointer to 'struct spi_nor'
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* @hwcaps: pointer to 'struct spi_nor_hwcaps'
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*
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* This hook is called after default_init/late_init but before the first
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* data transfer. It is the ideal place to switch from safe scan frequency
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* to high-performance operational frequency.
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*/
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static int everspin_mram_setup(struct spi_nor *nor,
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const struct spi_nor_hwcaps *hwcaps)
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{
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struct spi_nor_flash_parameter *params = nor->params;
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struct spi_device *spi = nor->spimem->spi;
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int ret;
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u8 val = 0;
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/*
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* Request high speed frequency.
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*/
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spi->max_speed_hz = EVERSPIN_MRAM_SPEED_MHZ;
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dev_info(nor->dev, "Escalating speed to %u Hz in setup hook\n",
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spi->max_speed_hz);
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/* Update Dummy Bytes to serve the higher rate EVERSPIN_MRAM_SPEED_MHZ */
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nor->read_dummy = EVERSPIN_MRAM_DUMMY_CYCLES_FAST;
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spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 0,
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EVERSPIN_MRAM_DUMMY_CYCLES_FAST,
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SPINOR_OP_EV_OCTAL_FAST_READ, SNOR_PROTO_8_8_8);
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everspin_mram_write_reg_octal(nor, SPINOR_REG_MT_CFR1V,
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EVERSPIN_MRAM_DUMMY_CYCLES_FAST);
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everspin_mram_read_reg_octal(nor, SPINOR_REG_MT_CFR1V, &val);
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dev_info(nor->dev, "Updating Dummy Bytes to %d (read: %d)\n", nor->read_dummy, val);
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/*
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* Force the controller driver (cadence-qspi) to re-run
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* cqspi_config_baudrate_div() and update hardware registers.
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*/
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ret = spi_setup(spi);
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if (ret) {
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dev_err(nor->dev, "Failed to update SPI setup (%d)\n", ret);
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return ret;
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}
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return 0;
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}
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/**
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* everspin_mram_late_init - Final 8-8-8 STR configuration for EM008LXO
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*/
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@@ -192,33 +292,39 @@ static int everspin_mram_late_init(struct spi_nor *nor)
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dev_info(nor->dev, "Finalizing 8s-8s-8s STR: Write/Read fully functional.\n");
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/* 1. Bypass core hwcaps restrictions */
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/* Bypass core hwcaps restrictions.
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* We need this as a workaround.
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*/
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params->hwcaps.mask |= SNOR_HWCAPS_READ | SNOR_HWCAPS_PP;
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/* 2. Global Octal STR Protocol Settings */
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/* Global Octal STR Protocol Settings */
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nor->read_proto = SNOR_PROTO_8_8_8;
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nor->write_proto = SNOR_PROTO_8_8_8;
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nor->reg_proto = SNOR_PROTO_8_8_8;
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nor->read_opcode = 0xCB;
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nor->read_dummy = 8;
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nor->program_opcode = 0x82;
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nor->read_opcode = SPINOR_OP_EV_OCTAL_FAST_READ;
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/* Set global read dummy cycles */
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nor->read_dummy = EVERSPIN_MRAM_DUMMY_CYCLES;
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nor->program_opcode = SPINOR_OP_EV_OCTAL_PAGE_PROG;
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nor->addr_nbytes = 3;
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params->addr_nbytes = 3;
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/* 3. Disable WIP Polling (Fixes the 40s Timeout) */
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/* Disable WIP Polling (Fixes the 40s Timeout) */
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params->ready = everspin_mram_ready_noop;
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/* 4. Align Page Size for Controller Stability */
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/* Align Page Size for Controller Stability */
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/* Cadence OSPI handles 256-byte pages more reliably in Octal mode */
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params->page_size = 256;
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/* 5. Map Opcodes to standard slots for MTD core */
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spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
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0, 8, 0xCB, SNOR_PROTO_8_8_8);
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/* Map Opcodes to standard slots for MTD core */
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spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 0,
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EVERSPIN_MRAM_DUMMY_CYCLES,
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SPINOR_OP_EV_OCTAL_FAST_READ, SNOR_PROTO_8_8_8);
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spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
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0x82, SNOR_PROTO_8_8_8);
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SPINOR_OP_EV_OCTAL_PAGE_PROG, SNOR_PROTO_8_8_8);
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nor->params->setup = everspin_mram_setup;
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return 0;
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}
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