diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 3e0480aadf9d..541afcf32f9a 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1195,6 +1195,7 @@ static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 	const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 	void __iomem *reg_base = cqspi->iobase;
 	u32 reg, div;
+	u32 actual_clk;
 
 	/* Recalculate the baudrate divisor based on QSPI specification. */
 	div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
@@ -1207,10 +1208,25 @@ static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 			cqspi->sclk, ref_clk_hz/((div+1)*2));
 	}
 
+	/* Calculate actual clock for logging purposes */
+	actual_clk = ref_clk_hz / (2 * (div + 1));
+
+	dev_info(&cqspi->pdev->dev,
+	  "CQSPI Clock Config: Ref=%u Hz, Target=%u Hz, Divisor=%u, Result=%u Hz\n",
+	  ref_clk_hz, cqspi->sclk, div, actual_clk);
+
 	reg = readl(reg_base + CQSPI_REG_CONFIG);
+
+	/* Log old register value for deep debugging */
+	dev_info(&cqspi->pdev->dev, "Old CONFIG_REG: 0x%08x\n", reg);
+
 	reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 	reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
+
 	writel(reg, reg_base + CQSPI_REG_CONFIG);
+
+	dev_info(&cqspi->pdev->dev, "New CONFIG_REG: 0x%08x (BaudDiv field updated)\n",
+	  readl(reg_base + CQSPI_REG_CONFIG));
 }
 
 static void cqspi_readdata_capture(struct cqspi_st *cqspi,