arm64: dts: qcom: sm8650: add description of CCI controllers
Qualcomm SM8650 SoC has three CCI controllers with two I2C busses connected to each of them. The CCI controllers on SM8650 are compatible with the ones found on many other older generations of Qualcomm SoCs. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20240612215835.1149199-5-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Vladimir Zapolskiy
committed by
Bjorn Andersson
Bjorn Andersson
parent
4f33e6432f
commit
9e2ebc5817
@@ -3329,6 +3329,105 @@
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#power-domain-cells = <1>;
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};
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cci0: cci@ac15000 {
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compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
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reg = <0 0x0ac15000 0 0x1000>;
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interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
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power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
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clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_CCI_0_CLK>;
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clock-names = "camnoc_axi",
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"cpas_ahb",
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"cci";
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pinctrl-0 = <&cci0_0_default &cci0_1_default>;
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pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
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pinctrl-names = "default", "sleep";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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cci0_i2c0: i2c-bus@0 {
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reg = <0>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cci0_i2c1: i2c-bus@1 {
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reg = <1>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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cci1: cci@ac16000 {
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compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
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reg = <0 0x0ac16000 0 0x1000>;
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interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
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power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
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clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_CCI_1_CLK>;
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clock-names = "camnoc_axi",
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"cpas_ahb",
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"cci";
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pinctrl-0 = <&cci1_0_default &cci1_1_default>;
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pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
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pinctrl-names = "default", "sleep";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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cci1_i2c0: i2c-bus@0 {
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reg = <0>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cci1_i2c1: i2c-bus@1 {
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reg = <1>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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cci2: cci@ac17000 {
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compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
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reg = <0 0x0ac17000 0 0x1000>;
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interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
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power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
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clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_CCI_2_CLK>;
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clock-names = "camnoc_axi",
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"cpas_ahb",
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"cci";
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pinctrl-0 = <&cci2_0_default &cci2_1_default>;
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pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
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pinctrl-names = "default", "sleep";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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cci2_i2c0: i2c-bus@0 {
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reg = <0>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cci2_i2c1: i2c-bus@1 {
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reg = <1>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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camcc: clock-controller@ade0000 {
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compatible = "qcom,sm8650-camcc";
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reg = <0 0x0ade0000 0 0x20000>;
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@@ -4029,6 +4128,198 @@
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wakeup-parent = <&pdc>;
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cci0_0_default: cci0-0-default-state {
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sda-pins {
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pins = "gpio113";
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function = "cci_i2c_sda";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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scl-pins {
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pins = "gpio114";
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function = "cci_i2c_scl";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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};
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cci0_0_sleep: cci0-0-sleep-state {
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sda-pins {
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pins = "gpio113";
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function = "cci_i2c_sda";
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drive-strength = <2>;
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bias-pull-down;
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};
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scl-pins {
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pins = "gpio114";
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function = "cci_i2c_scl";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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cci0_1_default: cci0-1-default-state {
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sda-pins {
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pins = "gpio115";
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function = "cci_i2c_sda";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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scl-pins {
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pins = "gpio116";
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function = "cci_i2c_scl";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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};
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cci0_1_sleep: cci0-1-sleep-state {
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sda-pins {
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pins = "gpio115";
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function = "cci_i2c_sda";
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drive-strength = <2>;
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bias-pull-down;
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};
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scl-pins {
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pins = "gpio116";
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function = "cci_i2c_scl";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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cci1_0_default: cci1-0-default-state {
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sda-pins {
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pins = "gpio117";
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function = "cci_i2c_sda";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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scl-pins {
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pins = "gpio118";
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function = "cci_i2c_scl";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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};
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cci1_0_sleep: cci1-0-sleep-state {
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sda-pins {
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pins = "gpio117";
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function = "cci_i2c_sda";
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drive-strength = <2>;
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bias-pull-down;
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};
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scl-pins {
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pins = "gpio118";
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function = "cci_i2c_scl";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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cci1_1_default: cci1-1-default-state {
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sda-pins {
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pins = "gpio12";
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function = "cci_i2c_sda";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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scl-pins {
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pins = "gpio13";
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function = "cci_i2c_scl";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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};
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cci1_1_sleep: cci1-1-sleep-state {
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sda-pins {
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pins = "gpio12";
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function = "cci_i2c_sda";
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drive-strength = <2>;
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bias-pull-down;
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};
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scl-pins {
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pins = "gpio13";
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function = "cci_i2c_scl";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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cci2_0_default: cci2-0-default-state {
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sda-pins {
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pins = "gpio112";
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function = "cci_i2c_sda";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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scl-pins {
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pins = "gpio153";
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function = "cci_i2c_scl";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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};
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cci2_0_sleep: cci2-0-sleep-state {
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sda-pins {
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pins = "gpio112";
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function = "cci_i2c_sda";
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drive-strength = <2>;
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bias-pull-down;
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};
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scl-pins {
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pins = "gpio153";
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function = "cci_i2c_scl";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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cci2_1_default: cci2-1-default-state {
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sda-pins {
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pins = "gpio119";
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function = "cci_i2c_sda";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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scl-pins {
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pins = "gpio120";
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function = "cci_i2c_scl";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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};
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cci2_1_sleep: cci2-1-sleep-state {
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sda-pins {
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pins = "gpio119";
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function = "cci_i2c_sda";
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drive-strength = <2>;
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bias-pull-down;
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};
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scl-pins {
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pins = "gpio120";
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function = "cci_i2c_scl";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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hub_i2c0_data_clk: hub-i2c0-data-clk-state {
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/* SDA, SCL */
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pins = "gpio64", "gpio65";
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