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arm64: dts: qcom: sm8550: add description of CCI controllers

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Qualcomm SM8550 SoC contains 3 Camera Control Interface controllers
very similar to the ones found on other Qualcomm SoCs.

One noticeable difference is that cci@ac16000 controller provides only
one I2C bus and has an additional control over AON CCI pins gpio208
and gpio209, but this feature is not yet supported in the CCI driver.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240612215835.1149199-4-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Vladimir Zapolskiy
2024-06-13 00:58:34 +03:00
committed by Bjorn Andersson
parent b87b8df9c0
commit 4f33e6432f
1 changed files with 252 additions and 0 deletions
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arch/arm64/boot/dts/qcom/sm8550.dtsi
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@@ -2747,6 +2747,98 @@
#power-domain-cells = <1>;
};
cci0: cci@ac15000 {
compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
reg = <0 0x0ac15000 0 0x1000>;
interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CCI_0_CLK>;
clock-names = "camnoc_axi",
"cpas_ahb",
"cci";
pinctrl-0 = <&cci0_0_default &cci0_1_default>;
pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
pinctrl-names = "default", "sleep";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
cci0_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci0_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cci1: cci@ac16000 {
compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
reg = <0 0x0ac16000 0 0x1000>;
interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CCI_1_CLK>;
clock-names = "camnoc_axi",
"cpas_ahb",
"cci";
pinctrl-0 = <&cci1_0_default>;
pinctrl-1 = <&cci1_0_sleep>;
pinctrl-names = "default", "sleep";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
cci1_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cci2: cci@ac17000 {
compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
reg = <0 0x0ac17000 0 0x1000>;
interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CCI_2_CLK>;
clock-names = "camnoc_axi",
"cpas_ahb",
"cci";
pinctrl-0 = <&cci2_0_default &cci2_1_default>;
pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
pinctrl-names = "default", "sleep";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
cci2_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci2_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
camcc: clock-controller@ade0000 {
compatible = "qcom,sm8550-camcc";
reg = <0 0x0ade0000 0 0x20000>;
@@ -3393,6 +3485,166 @@
gpio-ranges = <&tlmm 0 0 211>;
wakeup-parent = <&pdc>;
cci0_0_default: cci0-0-default-state {
sda-pins {
pins = "gpio110";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio111";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci0_0_sleep: cci0-0-sleep-state {
sda-pins {
pins = "gpio110";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio111";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
cci0_1_default: cci0-1-default-state {
sda-pins {
pins = "gpio112";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio113";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci0_1_sleep: cci0-1-sleep-state {
sda-pins {
pins = "gpio112";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio113";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
cci1_0_default: cci1-0-default-state {
sda-pins {
pins = "gpio114";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio115";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci1_0_sleep: cci1-0-sleep-state {
sda-pins {
pins = "gpio114";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio115";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
cci2_0_default: cci2-0-default-state {
sda-pins {
pins = "gpio74";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio75";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci2_0_sleep: cci2-0-sleep-state {
sda-pins {
pins = "gpio74";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio75";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
cci2_1_default: cci2-1-default-state {
sda-pins {
pins = "gpio0";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio1";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci2_1_sleep: cci2-1-sleep-state {
sda-pins {
pins = "gpio0";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio1";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
hub_i2c0_data_clk: hub-i2c0-data-clk-state {
/* SDA, SCL */
pins = "gpio16", "gpio17";