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clk: rockchip: rv1106: adjust pvtpll length for cpu

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Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I26b02751a38dad4dc501cbbcd4497636dd6ac991
This commit is contained in:
Liang Chen
2023-05-30 17:09:55 +08:00
committed by Tao Huang
parent c91152fefd
commit 750f6e702f
1 changed files with 1 additions and 1 deletions
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drivers/clk/rockchip/clk-rv1106.c
+1 -1
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@@ -1118,7 +1118,7 @@ static void rockchip_rv1106_pvtpll_init(struct rockchip_clk_provider *ctx)
/* set pvtpll ref clk mux */
writel_relaxed(CPU_PVTPLL_PATH_CORE, ctx->reg_base + CPU_CLK_PATH_BASE);
regmap_write(ctx->grf, CPU_PVTPLL_CON0_H, HIWORD_UPDATE(0x6, PVTPLL_LENGTH_SEL_MASK,
regmap_write(ctx->grf, CPU_PVTPLL_CON0_H, HIWORD_UPDATE(0x7, PVTPLL_LENGTH_SEL_MASK,
PVTPLL_LENGTH_SEL_SHIFT));
regmap_write(ctx->grf, CPU_PVTPLL_CON0_L, HIWORD_UPDATE(0x1, PVTPLL_RING_SEL_MASK,
PVTPLL_RING_SEL_SHIFT));