From 750f6e702fa2df6ced70c0f5877e7a546f5807df Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Tue, 30 May 2023 17:09:55 +0800 Subject: [PATCH] clk: rockchip: rv1106: adjust pvtpll length for cpu Signed-off-by: Liang Chen Change-Id: I26b02751a38dad4dc501cbbcd4497636dd6ac991 --- drivers/clk/rockchip/clk-rv1106.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-rv1106.c index 551c3396bc84..0833bf2adb8b 100644 --- a/drivers/clk/rockchip/clk-rv1106.c +++ b/drivers/clk/rockchip/clk-rv1106.c @@ -1118,7 +1118,7 @@ static void rockchip_rv1106_pvtpll_init(struct rockchip_clk_provider *ctx) /* set pvtpll ref clk mux */ writel_relaxed(CPU_PVTPLL_PATH_CORE, ctx->reg_base + CPU_CLK_PATH_BASE); - regmap_write(ctx->grf, CPU_PVTPLL_CON0_H, HIWORD_UPDATE(0x6, PVTPLL_LENGTH_SEL_MASK, + regmap_write(ctx->grf, CPU_PVTPLL_CON0_H, HIWORD_UPDATE(0x7, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT)); regmap_write(ctx->grf, CPU_PVTPLL_CON0_L, HIWORD_UPDATE(0x1, PVTPLL_RING_SEL_MASK, PVTPLL_RING_SEL_SHIFT));