Merge branches 'clk-cleanup', 'clk-renesas', 'clk-mediatek', 'clk-samsung' and 'clk-socfpga' into clk-next
- Support for 5L35023 variant of Versa 3 clock generator
* clk-cleanup:
clk: analogbits: Fix incorrect calculation of vco rate delta
clk: Use str_enable_disable-like helpers
clk: clk-loongson2: Switch to use devm_clk_hw_register_fixed_rate_parent_data()
clk: starfive: Make _clk_get become a common helper function
clk: ep93xx: make const read-only arrays static
clk: lmk04832: make read-only const arrays static
clk: ti: use kcalloc() instead of kzalloc()
dt-bindings: clock: st,stm32mp1-rcc: complete the reference path
dt-bindings: clock: st,stm32mp1-rcc: fix reference paths
dt-bindings: clock: ti: Convert composite.txt to json-schema
dt-bindings: clock: ti: Convert gate.txt to json-schema
clk: Drop obsolete devm_clk_bulk_get_all_enable() helper
PCI: exynos: Switch to devm_clk_bulk_get_all_enabled()
soc: mediatek: pwrap: Switch to devm_clk_bulk_get_all_enabled()
clk: davinci: remove platform data struct
clk: fix an OF node reference leak in of_clk_get_parent_name()
clk: mmp: pxa1908-apbc: Fix NULL vs IS_ERR() check
clk: mmp: pxa1908-apbcp: Fix a NULL vs IS_ERR() check
clk: mmp: pxa1908-mpmu: Fix a NULL vs IS_ERR() check
* clk-renesas: (24 commits)
dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard
clk: renesas: r9a09g057: Add clock and reset entries for GIC
clk: renesas: r9a09g057: Add reset entry for SYS
clk: renesas: r8a779g0: Add VSPX clocks
clk: renesas: r8a779g0: Add FCPVX clocks
clk: renesas: r9a09g047: Add I2C clocks/resets
clk: renesas: r9a09g047: Add CA55 core clocks
clk: renesas: rzv2h: Add support for RZ/G3E SoC
clk: renesas: rzv2h: Add MSTOP support
dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
clk: versaclock3: Add support for the 5L35023 variant
dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator
clk: versaclock3: Prepare for the addition of 5L35023 device
clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP
clk: renesas: r8a779h0: Add display clocks
clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets
clk: renesas: rzv2h: Add selective Runtime PM support for clocks
clk: renesas: r9a06g032: Use BIT macro consistently
...
* clk-mediatek:
clk: ralink: mtmips: remove duplicated 'xtal' clock for Ralink SoC RT3883
clk: mediatek: mt2701-img: add missing dummy clk
clk: mediatek: mt2701-mm: add missing dummy clk
clk: mediatek: mt2701-bdp: add missing dummy clk
clk: mediatek: mt2701-aud: fix conversion to mtk_clk_simple_probe
clk: mediatek: mt2701-vdec: fix conversion to mtk_clk_simple_probe
* clk-samsung:
clk: samsung: Introduce Exynos990 clock controller driver
clk: samsung: clk-pll: Add support for pll_{0717x, 0718x, 0732x}
dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindings
* clk-socfpga:
clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
This commit is contained in:
Stephen Boyd
@@ -31,6 +31,7 @@ description: |
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properties:
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compatible:
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enum:
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- renesas,5l35023
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- renesas,5p35023
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reg:
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@@ -4,19 +4,22 @@
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$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
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title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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description:
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On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
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and control of clock signals for the IP modules, generation and control of resets,
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and control over booting, low power consumption and power supply domains.
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On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
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generation and control of clock signals for the IP modules, generation and
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control of resets, and control over booting, low power consumption and power
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supply domains.
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properties:
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compatible:
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const: renesas,r9a09g057-cpg
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enum:
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- renesas,r9a09g047-cpg # RZ/G3E
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- renesas,r9a09g057-cpg # RZ/V2H
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reg:
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maxItems: 1
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@@ -37,7 +40,7 @@ properties:
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description: |
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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and a core clock reference, as defined in
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<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
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<dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
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- For module clocks, the two clock specifier cells must be "CPG_MOD" and
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a module number. The module number is calculated as the CLKON register
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offset index multiplied by 16, plus the actual bit in the register
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@@ -0,0 +1,121 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,exynos990-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos990 SoC clock controller
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maintainers:
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- Igor Belwon <igor.belwon@mentallysanemainliners.org>
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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description: |
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Exynos990 clock controller is comprised of several CMU units, generating
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clocks for different domains. Those CMU units are modeled as separate device
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tree nodes, and might depend on each other. The root clock in that root tree
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is an external clock: OSCCLK (26 MHz). This external clock must be defined
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as a fixed-rate clock in dts.
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CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
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dividers; all other clocks of function blocks (other CMUs) are usually
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derived from CMU_TOP.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All clocks available for usage
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in clock consumer nodes are defined as preprocessor macros in
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'include/dt-bindings/clock/samsung,exynos990.h' header.
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properties:
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compatible:
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enum:
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- samsung,exynos990-cmu-hsi0
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- samsung,exynos990-cmu-top
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clocks:
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minItems: 1
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maxItems: 5
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clock-names:
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minItems: 1
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maxItems: 5
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"#clock-cells":
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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- clock-names
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- "#clock-cells"
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- reg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos990-cmu-hsi0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_HSI0 BUS clock (from CMU_TOP)
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- description: CMU_HSI0 USB31DRD clock (from CMU_TOP)
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- description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)
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- description: CMU_HSI0 DPGTC clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- const: usb31drd
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- const: usbdp_debug
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- const: dpgtc
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos990-cmu-top
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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clock-names:
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items:
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- const: oscclk
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/samsung,exynos990.h>
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cmu_hsi0: clock-controller@10a00000 {
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compatible = "samsung,exynos990-cmu-hsi0";
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reg = <0x10a00000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
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<&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
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<&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
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<&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
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clock-names = "oscclk",
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"bus",
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"usb31drd",
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"usbdp_debug",
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"dpgtc";
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};
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...
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@@ -525,6 +525,23 @@ properties:
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- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
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- const: renesas,r9a09g011
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- description: RZ/G3E (R9A09G047)
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items:
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- enum:
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- renesas,smarc2-evk # RZ SMARC Carrier-II EVK
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- enum:
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- renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
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- enum:
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- renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)
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- renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)
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- renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
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- renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
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- renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)
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- renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)
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- renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
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- renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
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- const: renesas,r9a09g047
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- description: RZ/V2H(P) (R9A09G057)
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items:
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- enum:
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@@ -78,9 +78,6 @@
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#define VC3_PLL1_VCO_MIN 300000000UL
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#define VC3_PLL1_VCO_MAX 600000000UL
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#define VC3_PLL2_VCO_MIN 400000000UL
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#define VC3_PLL2_VCO_MAX 1200000000UL
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#define VC3_PLL3_VCO_MIN 300000000UL
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#define VC3_PLL3_VCO_MAX 800000000UL
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@@ -147,9 +144,13 @@ struct vc3_pfd_data {
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u8 mdiv2_bitmsk;
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};
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struct vc3_vco {
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unsigned long min;
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unsigned long max;
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};
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struct vc3_pll_data {
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unsigned long vco_min;
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unsigned long vco_max;
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struct vc3_vco vco;
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u8 num;
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u8 int_div_msb_offs;
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u8 int_div_lsb_offs;
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@@ -166,12 +167,17 @@ struct vc3_div_data {
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struct vc3_hw_data {
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struct clk_hw hw;
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struct regmap *regmap;
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const void *data;
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void *data;
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u32 div_int;
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u32 div_frc;
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};
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struct vc3_hw_cfg {
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struct vc3_vco pll2_vco;
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u32 se2_clk_sel_msk;
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};
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static const struct clk_div_table div1_divs[] = {
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{ .val = 0, .div = 1, }, { .val = 1, .div = 4, },
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{ .val = 2, .div = 5, }, { .val = 3, .div = 6, },
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@@ -386,10 +392,10 @@ static long vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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const struct vc3_pll_data *pll = vc3->data;
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u64 div_frc;
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if (rate < pll->vco_min)
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rate = pll->vco_min;
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if (rate > pll->vco_max)
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rate = pll->vco_max;
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if (rate < pll->vco.min)
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rate = pll->vco.min;
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if (rate > pll->vco.max)
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rate = pll->vco.max;
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vc3->div_int = rate / *parent_rate;
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@@ -680,8 +686,10 @@ static struct vc3_hw_data clk_pll[] = {
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.num = VC3_PLL1,
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.int_div_msb_offs = VC3_PLL1_LOOP_FILTER_N_DIV_MSB,
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.int_div_lsb_offs = VC3_PLL1_VCO_N_DIVIDER,
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.vco_min = VC3_PLL1_VCO_MIN,
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.vco_max = VC3_PLL1_VCO_MAX
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.vco = {
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.min = VC3_PLL1_VCO_MIN,
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.max = VC3_PLL1_VCO_MAX
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}
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},
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.hw.init = &(struct clk_init_data) {
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.name = "pll1",
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@@ -698,8 +706,6 @@ static struct vc3_hw_data clk_pll[] = {
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.num = VC3_PLL2,
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.int_div_msb_offs = VC3_PLL2_FB_INT_DIV_MSB,
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.int_div_lsb_offs = VC3_PLL2_FB_INT_DIV_LSB,
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.vco_min = VC3_PLL2_VCO_MIN,
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.vco_max = VC3_PLL2_VCO_MAX
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},
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.hw.init = &(struct clk_init_data) {
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.name = "pll2",
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@@ -716,8 +722,10 @@ static struct vc3_hw_data clk_pll[] = {
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.num = VC3_PLL3,
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.int_div_msb_offs = VC3_PLL3_LOOP_FILTER_N_DIV_MSB,
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.int_div_lsb_offs = VC3_PLL3_N_DIVIDER,
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.vco_min = VC3_PLL3_VCO_MIN,
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.vco_max = VC3_PLL3_VCO_MAX
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.vco = {
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.min = VC3_PLL3_VCO_MIN,
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.max = VC3_PLL3_VCO_MAX
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}
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},
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||||
.hw.init = &(struct clk_init_data) {
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.name = "pll3",
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@@ -901,7 +909,6 @@ static struct vc3_hw_data clk_mux[] = {
|
||||
[VC3_SE2_MUX] = {
|
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.data = &(struct vc3_clk_data) {
|
||||
.offs = VC3_SE2_CTRL_REG0,
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||||
.bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "se2_mux",
|
||||
@@ -982,6 +989,7 @@ static int vc3_probe(struct i2c_client *client)
|
||||
{
|
||||
struct device *dev = &client->dev;
|
||||
u8 settings[NUM_CONFIG_REGISTERS];
|
||||
const struct vc3_hw_cfg *data;
|
||||
struct regmap *regmap;
|
||||
const char *name;
|
||||
int ret, i;
|
||||
@@ -1029,9 +1037,16 @@ static int vc3_probe(struct i2c_client *client)
|
||||
clk_pfd[i].hw.init->name);
|
||||
}
|
||||
|
||||
data = i2c_get_match_data(client);
|
||||
|
||||
/* Register pll's */
|
||||
for (i = 0; i < ARRAY_SIZE(clk_pll); i++) {
|
||||
clk_pll[i].regmap = regmap;
|
||||
if (i == VC3_PLL2) {
|
||||
struct vc3_pll_data *pll_data = clk_pll[i].data;
|
||||
|
||||
pll_data->vco = data->pll2_vco;
|
||||
}
|
||||
ret = devm_clk_hw_register(dev, &clk_pll[i].hw);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "%s failed\n",
|
||||
@@ -1059,6 +1074,11 @@ static int vc3_probe(struct i2c_client *client)
|
||||
/* Register clk muxes */
|
||||
for (i = 0; i < ARRAY_SIZE(clk_mux); i++) {
|
||||
clk_mux[i].regmap = regmap;
|
||||
if (i == VC3_SE2_MUX) {
|
||||
struct vc3_clk_data *clk_data = clk_mux[i].data;
|
||||
|
||||
clk_data->bitmsk = data->se2_clk_sel_msk;
|
||||
}
|
||||
ret = devm_clk_hw_register(dev, &clk_mux[i].hw);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "%s failed\n",
|
||||
@@ -1108,8 +1128,19 @@ static int vc3_probe(struct i2c_client *client)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct vc3_hw_cfg vc3_5p = {
|
||||
.pll2_vco = { .min = 400000000UL, .max = 1200000000UL },
|
||||
.se2_clk_sel_msk = BIT(6),
|
||||
};
|
||||
|
||||
static const struct vc3_hw_cfg vc3_5l = {
|
||||
.pll2_vco = { .min = 30000000UL, .max = 130000000UL },
|
||||
.se2_clk_sel_msk = BIT(0),
|
||||
};
|
||||
|
||||
static const struct of_device_id dev_ids[] = {
|
||||
{ .compatible = "renesas,5p35023" },
|
||||
{ .compatible = "renesas,5p35023", .data = &vc3_5p },
|
||||
{ .compatible = "renesas,5l35023", .data = &vc3_5l },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, dev_ids);
|
||||
|
||||
@@ -55,10 +55,16 @@ static const struct mtk_gate audio_clks[] = {
|
||||
GATE_DUMMY(CLK_DUMMY, "aud_dummy"),
|
||||
/* AUDIO0 */
|
||||
GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
|
||||
GATE_DUMMY(CLK_AUD_LRCK_DETECT, "audio_lrck_detect_dummy"),
|
||||
GATE_DUMMY(CLK_AUD_I2S, "audio_i2c_dummy"),
|
||||
GATE_DUMMY(CLK_AUD_APLL_TUNER, "audio_apll_tuner_dummy"),
|
||||
GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
|
||||
GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21),
|
||||
GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22),
|
||||
GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23),
|
||||
GATE_DUMMY(CLK_AUD_TML, "audio_tml_dummy"),
|
||||
GATE_DUMMY(CLK_AUD_AHB_IDLE_EXT, "audio_ahb_idle_ext_dummy"),
|
||||
GATE_DUMMY(CLK_AUD_AHB_IDLE_INT, "audio_ahb_idle_int_dummy"),
|
||||
/* AUDIO1 */
|
||||
GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0),
|
||||
GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1),
|
||||
@@ -76,10 +82,12 @@ static const struct mtk_gate audio_clks[] = {
|
||||
GATE_AUDIO1(CLK_AUD_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
|
||||
GATE_AUDIO1(CLK_AUD_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
|
||||
GATE_AUDIO1(CLK_AUD_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
|
||||
GATE_DUMMY(CLK_AUD_HDMIRX, "audio_hdmirx_dummy"),
|
||||
GATE_AUDIO1(CLK_AUD_INTDIR, "audio_intdir", "intdir_sel", 20),
|
||||
GATE_AUDIO1(CLK_AUD_A1SYS, "audio_a1sys", "aud_mux1_sel", 21),
|
||||
GATE_AUDIO1(CLK_AUD_A2SYS, "audio_a2sys", "aud_mux2_sel", 22),
|
||||
GATE_AUDIO1(CLK_AUD_AFE_CONN, "audio_afe_conn", "aud_mux1_sel", 23),
|
||||
GATE_DUMMY(CLK_AUD_AFE_PCMIF, "audio_afe_pcmif_dummy"),
|
||||
GATE_AUDIO1(CLK_AUD_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25),
|
||||
/* AUDIO2 */
|
||||
GATE_AUDIO2(CLK_AUD_MMIF_UL1, "audio_ul1", "aud_mux1_sel", 0),
|
||||
@@ -100,6 +108,8 @@ static const struct mtk_gate audio_clks[] = {
|
||||
GATE_AUDIO2(CLK_AUD_MMIF_AWB2, "audio_awb2", "aud_mux1_sel", 15),
|
||||
GATE_AUDIO2(CLK_AUD_MMIF_DAI, "audio_dai", "aud_mux1_sel", 16),
|
||||
/* AUDIO3 */
|
||||
GATE_DUMMY(CLK_AUD_DMIC1, "audio_dmic1_dummy"),
|
||||
GATE_DUMMY(CLK_AUD_DMIC2, "audio_dmic2_dummy"),
|
||||
GATE_AUDIO3(CLK_AUD_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
|
||||
GATE_AUDIO3(CLK_AUD_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
|
||||
GATE_AUDIO3(CLK_AUD_ASRCI5, "audio_asrci5", "asm_h_sel", 4),
|
||||
|
||||
@@ -31,6 +31,7 @@ static const struct mtk_gate_regs bdp1_cg_regs = {
|
||||
GATE_MTK(_id, _name, _parent, &bdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
|
||||
|
||||
static const struct mtk_gate bdp_clks[] = {
|
||||
GATE_DUMMY(CLK_DUMMY, "bdp_dummy"),
|
||||
GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),
|
||||
GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),
|
||||
GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),
|
||||
|
||||
@@ -22,6 +22,7 @@ static const struct mtk_gate_regs img_cg_regs = {
|
||||
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
static const struct mtk_gate img_clks[] = {
|
||||
GATE_DUMMY(CLK_DUMMY, "img_dummy"),
|
||||
GATE_IMG(CLK_IMG_SMI_COMM, "img_smi_comm", "mm_sel", 0),
|
||||
GATE_IMG(CLK_IMG_RESZ, "img_resz", "mm_sel", 1),
|
||||
GATE_IMG(CLK_IMG_JPGDEC_SMI, "img_jpgdec_smi", "mm_sel", 5),
|
||||
|
||||
@@ -31,6 +31,7 @@ static const struct mtk_gate_regs disp1_cg_regs = {
|
||||
GATE_MTK(_id, _name, _parent, &disp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
static const struct mtk_gate mm_clks[] = {
|
||||
GATE_DUMMY(CLK_DUMMY, "mm_dummy"),
|
||||
GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0),
|
||||
GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
|
||||
GATE_DISP0(CLK_MM_CMDQ, "mm_cmdq", "mm_sel", 2),
|
||||
|
||||
@@ -31,6 +31,7 @@ static const struct mtk_gate_regs vdec1_cg_regs = {
|
||||
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
|
||||
|
||||
static const struct mtk_gate vdec_clks[] = {
|
||||
GATE_DUMMY(CLK_DUMMY, "vdec_dummy"),
|
||||
GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0),
|
||||
GATE_VDEC1(CLK_VDEC_LARB, "vdec_larb_cken", "mm_sel", 0),
|
||||
};
|
||||
|
||||
@@ -266,7 +266,6 @@ err_clk_unreg:
|
||||
}
|
||||
|
||||
static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
|
||||
CLK_FIXED("xtal", NULL, 40000000),
|
||||
CLK_FIXED("periph", "xtal", 40000000)
|
||||
};
|
||||
|
||||
|
||||
@@ -40,6 +40,7 @@ config CLK_RENESAS
|
||||
select CLK_R9A07G054 if ARCH_R9A07G054
|
||||
select CLK_R9A08G045 if ARCH_R9A08G045
|
||||
select CLK_R9A09G011 if ARCH_R9A09G011
|
||||
select CLK_R9A09G047 if ARCH_R9A09G047
|
||||
select CLK_R9A09G057 if ARCH_R9A09G057
|
||||
select CLK_SH73A0 if ARCH_SH73A0
|
||||
|
||||
@@ -194,6 +195,10 @@ config CLK_R9A09G011
|
||||
bool "RZ/V2M clock support" if COMPILE_TEST
|
||||
select CLK_RZG2L
|
||||
|
||||
config CLK_R9A09G047
|
||||
bool "RZ/G3E clock support" if COMPILE_TEST
|
||||
select CLK_RZV2H
|
||||
|
||||
config CLK_R9A09G057
|
||||
bool "RZ/V2H(P) clock support" if COMPILE_TEST
|
||||
select CLK_RZV2H
|
||||
@@ -234,7 +239,7 @@ config CLK_RZG2L
|
||||
select RESET_CONTROLLER
|
||||
|
||||
config CLK_RZV2H
|
||||
bool "RZ/V2H(P) family clock support" if COMPILE_TEST
|
||||
bool "RZ/{G3E,V2H(P)} family clock support" if COMPILE_TEST
|
||||
select RESET_CONTROLLER
|
||||
|
||||
config CLK_RENESAS_VBATTB
|
||||
|
||||
@@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
|
||||
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
|
||||
|
||||
|
||||
@@ -238,6 +238,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
|
||||
DEF_MOD("pfc2", 917, R8A779G0_CLK_CP),
|
||||
DEF_MOD("pfc3", 918, R8A779G0_CLK_CP),
|
||||
DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
|
||||
DEF_MOD("vspx0", 1028, R8A779G0_CLK_S0D1_VIO),
|
||||
DEF_MOD("vspx1", 1029, R8A779G0_CLK_S0D1_VIO),
|
||||
DEF_MOD("fcpvx0", 1100, R8A779G0_CLK_S0D1_VIO),
|
||||
DEF_MOD("fcpvx1", 1101, R8A779G0_CLK_S0D1_VIO),
|
||||
DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC),
|
||||
DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
|
||||
DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
|
||||
|
||||
@@ -177,6 +177,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {
|
||||
DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2),
|
||||
DEF_MOD("csi40", 331, R8A779H0_CLK_CSI),
|
||||
DEF_MOD("csi41", 400, R8A779H0_CLK_CSI),
|
||||
DEF_MOD("dis0", 411, R8A779H0_CLK_VIOBUSD2),
|
||||
DEF_MOD("dsitxlink0", 415, R8A779H0_CLK_VIOBUSD2),
|
||||
DEF_MOD("fcpvd0", 508, R8A779H0_CLK_VIOBUSD2),
|
||||
DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1),
|
||||
DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
|
||||
DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
|
||||
@@ -225,6 +228,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {
|
||||
DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vspd0", 830, R8A779H0_CLK_VIOBUSD2),
|
||||
DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
|
||||
DEF_MOD("cmt0", 910, R8A779H0_CLK_R),
|
||||
DEF_MOD("cmt1", 911, R8A779H0_CLK_R),
|
||||
|
||||
@@ -20,15 +20,24 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/soc/renesas/r9a06g032-sysctrl.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
|
||||
|
||||
#define R9A06G032_SYSCTRL_USB 0x00
|
||||
#define R9A06G032_SYSCTRL_USB_H2MODE (1<<1)
|
||||
#define R9A06G032_SYSCTRL_USB_H2MODE BIT(1)
|
||||
#define R9A06G032_SYSCTRL_DMAMUX 0xA0
|
||||
|
||||
#define R9A06G032_SYSCTRL_RSTEN 0x120
|
||||
#define R9A06G032_SYSCTRL_RSTEN_MRESET_EN BIT(0)
|
||||
#define R9A06G032_SYSCTRL_RSTCTRL 0x198
|
||||
/* These work for both reset registers */
|
||||
#define R9A06G032_SYSCTRL_SWRST BIT(6)
|
||||
#define R9A06G032_SYSCTRL_WDA7RST_1 BIT(2)
|
||||
#define R9A06G032_SYSCTRL_WDA7RST_0 BIT(1)
|
||||
|
||||
/**
|
||||
* struct regbit - describe one bit in a register
|
||||
* @reg: offset of register relative to base address,
|
||||
@@ -1270,6 +1279,12 @@ static void r9a06g032_clocks_del_clk_provider(void *data)
|
||||
of_clk_del_provider(data);
|
||||
}
|
||||
|
||||
static int r9a06g032_restart_handler(struct sys_off_data *data)
|
||||
{
|
||||
writel(R9A06G032_SYSCTRL_SWRST, sysctrl_priv->reg + R9A06G032_SYSCTRL_RSTCTRL);
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static void __init r9a06g032_init_h2mode(struct r9a06g032_priv *clocks)
|
||||
{
|
||||
struct device_node *usbf_np;
|
||||
@@ -1324,6 +1339,18 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
|
||||
|
||||
r9a06g032_init_h2mode(clocks);
|
||||
|
||||
/* Clear potentially pending resets */
|
||||
writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1,
|
||||
clocks->reg + R9A06G032_SYSCTRL_RSTCTRL);
|
||||
/* Allow software reset */
|
||||
writel(R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
|
||||
clocks->reg + R9A06G032_SYSCTRL_RSTEN);
|
||||
|
||||
error = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
|
||||
r9a06g032_restart_handler, NULL);
|
||||
if (error)
|
||||
dev_warn(dev, "couldn't register restart handler (%d)\n", error);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) {
|
||||
const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i];
|
||||
const char *parent_name = d->source ?
|
||||
|
||||
@@ -187,6 +187,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
|
||||
DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1),
|
||||
DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3),
|
||||
DEF_FIXED("HP", R9A08G045_CLK_HP, CLK_PLL6, 1, 2),
|
||||
DEF_FIXED("TSU", R9A08G045_CLK_TSU, CLK_PLL2_DIV2, 1, 8),
|
||||
};
|
||||
|
||||
static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
|
||||
@@ -209,6 +210,14 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
|
||||
DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),
|
||||
DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),
|
||||
DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),
|
||||
DEF_MOD("ssi0_pclk2", R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0),
|
||||
DEF_MOD("ssi0_sfr", R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1),
|
||||
DEF_MOD("ssi1_pclk2", R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2),
|
||||
DEF_MOD("ssi1_sfr", R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3),
|
||||
DEF_MOD("ssi2_pclk2", R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4),
|
||||
DEF_MOD("ssi2_sfr", R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5),
|
||||
DEF_MOD("ssi3_pclk2", R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6),
|
||||
DEF_MOD("ssi3_sfr", R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7),
|
||||
DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0),
|
||||
DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1),
|
||||
DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2),
|
||||
@@ -224,7 +233,14 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
|
||||
DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2),
|
||||
DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3),
|
||||
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
|
||||
DEF_MOD("scif1_clk_pck", R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1),
|
||||
DEF_MOD("scif2_clk_pck", R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2),
|
||||
DEF_MOD("scif3_clk_pck", R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3),
|
||||
DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4),
|
||||
DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5),
|
||||
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
|
||||
DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0),
|
||||
DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1),
|
||||
DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
|
||||
};
|
||||
|
||||
@@ -238,6 +254,10 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
|
||||
DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
|
||||
DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
|
||||
DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
|
||||
DEF_RST(R9A08G045_SSI0_RST_M2_REG, 0x870, 0),
|
||||
DEF_RST(R9A08G045_SSI1_RST_M2_REG, 0x870, 1),
|
||||
DEF_RST(R9A08G045_SSI2_RST_M2_REG, 0x870, 2),
|
||||
DEF_RST(R9A08G045_SSI3_RST_M2_REG, 0x870, 3),
|
||||
DEF_RST(R9A08G045_USB_U2H0_HRESETN, 0x878, 0),
|
||||
DEF_RST(R9A08G045_USB_U2H1_HRESETN, 0x878, 1),
|
||||
DEF_RST(R9A08G045_USB_U2P_EXL_SYSRST, 0x878, 2),
|
||||
@@ -249,9 +269,16 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
|
||||
DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2),
|
||||
DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3),
|
||||
DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
|
||||
DEF_RST(R9A08G045_SCIF1_RST_SYSTEM_N, 0x884, 1),
|
||||
DEF_RST(R9A08G045_SCIF2_RST_SYSTEM_N, 0x884, 2),
|
||||
DEF_RST(R9A08G045_SCIF3_RST_SYSTEM_N, 0x884, 3),
|
||||
DEF_RST(R9A08G045_SCIF4_RST_SYSTEM_N, 0x884, 4),
|
||||
DEF_RST(R9A08G045_SCIF5_RST_SYSTEM_N, 0x884, 5),
|
||||
DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
|
||||
DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
|
||||
DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
|
||||
DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0),
|
||||
DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1),
|
||||
DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),
|
||||
};
|
||||
|
||||
@@ -286,6 +313,14 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
|
||||
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), 0),
|
||||
DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
|
||||
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), 0),
|
||||
DEF_PD("ssi0", R9A08G045_PD_SSI0,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(10)), 0),
|
||||
DEF_PD("ssi1", R9A08G045_PD_SSI1,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(11)), 0),
|
||||
DEF_PD("ssi2", R9A08G045_PD_SSI2,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(12)), 0),
|
||||
DEF_PD("ssi3", R9A08G045_PD_SSI3,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(13)), 0),
|
||||
DEF_PD("usb0", R9A08G045_PD_USB0,
|
||||
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), 0),
|
||||
DEF_PD("usb1", R9A08G045_PD_USB1,
|
||||
@@ -306,6 +341,18 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
|
||||
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), 0),
|
||||
DEF_PD("scif0", R9A08G045_PD_SCIF0,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), 0),
|
||||
DEF_PD("scif1", R9A08G045_PD_SCIF1,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(2)), 0),
|
||||
DEF_PD("scif2", R9A08G045_PD_SCIF2,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(3)), 0),
|
||||
DEF_PD("scif3", R9A08G045_PD_SCIF3,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(4)), 0),
|
||||
DEF_PD("scif4", R9A08G045_PD_SCIF4,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(5)), 0),
|
||||
DEF_PD("scif5", R9A08G045_PD_SCIF5,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0),
|
||||
DEF_PD("adc", R9A08G045_PD_ADC,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0),
|
||||
DEF_PD("vbat", R9A08G045_PD_VBAT,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),
|
||||
GENPD_FLAG_ALWAYS_ON),
|
||||
|
||||
@@ -0,0 +1,150 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas RZ/G3E CPG driver
|
||||
*
|
||||
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
|
||||
|
||||
#include "rzv2h-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_AUDIO_EXTAL,
|
||||
CLK_RTXIN,
|
||||
CLK_QEXTAL,
|
||||
|
||||
/* PLL Clocks */
|
||||
CLK_PLLCM33,
|
||||
CLK_PLLCLN,
|
||||
CLK_PLLDTY,
|
||||
CLK_PLLCA55,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_PLLCM33_DIV16,
|
||||
CLK_PLLCLN_DIV16,
|
||||
CLK_PLLDTY_ACPU,
|
||||
CLK_PLLDTY_ACPU_DIV4,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE,
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_1_8[] = {
|
||||
{0, 1},
|
||||
{1, 2},
|
||||
{2, 4},
|
||||
{3, 8},
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_2_64[] = {
|
||||
{0, 2},
|
||||
{1, 4},
|
||||
{2, 8},
|
||||
{3, 16},
|
||||
{4, 64},
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
|
||||
DEF_INPUT("rtxin", CLK_RTXIN),
|
||||
DEF_INPUT("qextal", CLK_QEXTAL),
|
||||
|
||||
/* PLL Clocks */
|
||||
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
|
||||
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
|
||||
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
|
||||
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
|
||||
|
||||
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
|
||||
|
||||
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
|
||||
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
|
||||
|
||||
/* Core Clocks */
|
||||
DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
|
||||
DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,
|
||||
CDDIV1_DIVCTL0, dtable_1_8),
|
||||
DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55,
|
||||
CDDIV1_DIVCTL1, dtable_1_8),
|
||||
DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55,
|
||||
CDDIV1_DIVCTL2, dtable_1_8),
|
||||
DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55,
|
||||
CDDIV1_DIVCTL3, dtable_1_8),
|
||||
DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
|
||||
};
|
||||
|
||||
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
|
||||
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
|
||||
BUS_MSTOP(3, BIT(5))),
|
||||
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
|
||||
BUS_MSTOP(3, BIT(14))),
|
||||
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
|
||||
BUS_MSTOP(3, BIT(13))),
|
||||
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
|
||||
BUS_MSTOP(1, BIT(1))),
|
||||
DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
|
||||
BUS_MSTOP(1, BIT(2))),
|
||||
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
|
||||
BUS_MSTOP(1, BIT(3))),
|
||||
DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
|
||||
BUS_MSTOP(1, BIT(4))),
|
||||
DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
|
||||
BUS_MSTOP(1, BIT(5))),
|
||||
DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
|
||||
BUS_MSTOP(1, BIT(6))),
|
||||
DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
|
||||
BUS_MSTOP(1, BIT(7))),
|
||||
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
|
||||
BUS_MSTOP(1, BIT(8))),
|
||||
};
|
||||
|
||||
static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
|
||||
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
|
||||
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
|
||||
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
|
||||
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
|
||||
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
|
||||
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
|
||||
DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
|
||||
DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
|
||||
DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
|
||||
DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
|
||||
DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
|
||||
DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
|
||||
DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
|
||||
};
|
||||
|
||||
const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r9a09g047_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r9a09g047_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r9a09g047_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks),
|
||||
.num_hw_mod_clks = 28 * 16,
|
||||
|
||||
/* Resets */
|
||||
.resets = r9a09g047_resets,
|
||||
.num_resets = ARRAY_SIZE(r9a09g047_resets),
|
||||
|
||||
.num_mstop_bits = 208,
|
||||
};
|
||||
@@ -28,6 +28,7 @@ enum clk_ids {
|
||||
CLK_PLLCLN,
|
||||
CLK_PLLDTY,
|
||||
CLK_PLLCA55,
|
||||
CLK_PLLVDO,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_PLLCM33_DIV16,
|
||||
@@ -35,7 +36,13 @@ enum clk_ids {
|
||||
CLK_PLLCLN_DIV8,
|
||||
CLK_PLLCLN_DIV16,
|
||||
CLK_PLLDTY_ACPU,
|
||||
CLK_PLLDTY_ACPU_DIV2,
|
||||
CLK_PLLDTY_ACPU_DIV4,
|
||||
CLK_PLLDTY_DIV16,
|
||||
CLK_PLLVDO_CRU0,
|
||||
CLK_PLLVDO_CRU1,
|
||||
CLK_PLLVDO_CRU2,
|
||||
CLK_PLLVDO_CRU3,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE,
|
||||
@@ -49,6 +56,12 @@ static const struct clk_div_table dtable_1_8[] = {
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_2_4[] = {
|
||||
{0, 2},
|
||||
{1, 4},
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_2_64[] = {
|
||||
{0, 2},
|
||||
{1, 4},
|
||||
@@ -69,6 +82,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
||||
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
|
||||
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
|
||||
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
|
||||
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
|
||||
@@ -78,7 +92,14 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
||||
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
|
||||
|
||||
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
|
||||
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
|
||||
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
|
||||
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
|
||||
|
||||
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
|
||||
DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
|
||||
DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
|
||||
DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
|
||||
|
||||
/* Core Clocks */
|
||||
DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
|
||||
@@ -94,49 +115,117 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
|
||||
DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5),
|
||||
DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3),
|
||||
DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4),
|
||||
DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5),
|
||||
DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6),
|
||||
DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7),
|
||||
DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8),
|
||||
DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9),
|
||||
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10),
|
||||
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11),
|
||||
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12),
|
||||
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13),
|
||||
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14),
|
||||
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15),
|
||||
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16),
|
||||
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17),
|
||||
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18),
|
||||
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15),
|
||||
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19),
|
||||
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20),
|
||||
DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21),
|
||||
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22),
|
||||
DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23),
|
||||
DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24),
|
||||
DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25),
|
||||
DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26),
|
||||
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27),
|
||||
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3),
|
||||
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4),
|
||||
DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5),
|
||||
DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6),
|
||||
DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7),
|
||||
DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8),
|
||||
DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9),
|
||||
DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10),
|
||||
DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11),
|
||||
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12),
|
||||
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13),
|
||||
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),
|
||||
DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
|
||||
BUS_MSTOP_NONE),
|
||||
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
|
||||
BUS_MSTOP(3, BIT(5))),
|
||||
DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
|
||||
BUS_MSTOP(5, BIT(10))),
|
||||
DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
|
||||
BUS_MSTOP(5, BIT(11))),
|
||||
DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
|
||||
BUS_MSTOP(2, BIT(13))),
|
||||
DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
|
||||
BUS_MSTOP(2, BIT(14))),
|
||||
DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
|
||||
BUS_MSTOP(11, BIT(13))),
|
||||
DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
|
||||
BUS_MSTOP(11, BIT(14))),
|
||||
DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
|
||||
BUS_MSTOP(11, BIT(15))),
|
||||
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
|
||||
BUS_MSTOP(12, BIT(0))),
|
||||
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
|
||||
BUS_MSTOP(3, BIT(10))),
|
||||
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
|
||||
BUS_MSTOP(3, BIT(10))),
|
||||
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
|
||||
BUS_MSTOP(1, BIT(0))),
|
||||
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
|
||||
BUS_MSTOP(1, BIT(0))),
|
||||
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
|
||||
BUS_MSTOP(5, BIT(12))),
|
||||
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
|
||||
BUS_MSTOP(5, BIT(12))),
|
||||
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
|
||||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
|
||||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
|
||||
BUS_MSTOP(3, BIT(14))),
|
||||
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
|
||||
BUS_MSTOP(3, BIT(13))),
|
||||
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
|
||||
BUS_MSTOP(1, BIT(1))),
|
||||
DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
|
||||
BUS_MSTOP(1, BIT(2))),
|
||||
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
|
||||
BUS_MSTOP(1, BIT(3))),
|
||||
DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
|
||||
BUS_MSTOP(1, BIT(4))),
|
||||
DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
|
||||
BUS_MSTOP(1, BIT(5))),
|
||||
DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
|
||||
BUS_MSTOP(1, BIT(6))),
|
||||
DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
|
||||
BUS_MSTOP(1, BIT(7))),
|
||||
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
|
||||
BUS_MSTOP(1, BIT(8))),
|
||||
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
|
||||
BUS_MSTOP(8, BIT(2))),
|
||||
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
|
||||
BUS_MSTOP(8, BIT(2))),
|
||||
DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
|
||||
BUS_MSTOP(8, BIT(2))),
|
||||
DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
|
||||
BUS_MSTOP(8, BIT(2))),
|
||||
DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
|
||||
BUS_MSTOP(8, BIT(3))),
|
||||
DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
|
||||
BUS_MSTOP(8, BIT(3))),
|
||||
DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
|
||||
BUS_MSTOP(8, BIT(3))),
|
||||
DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
|
||||
BUS_MSTOP(8, BIT(3))),
|
||||
DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
|
||||
BUS_MSTOP(9, BIT(5))),
|
||||
DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
|
||||
BUS_MSTOP(9, BIT(5))),
|
||||
DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
|
||||
BUS_MSTOP(9, BIT(5))),
|
||||
DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
|
||||
BUS_MSTOP(9, BIT(6))),
|
||||
DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
|
||||
BUS_MSTOP(9, BIT(6))),
|
||||
DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
|
||||
BUS_MSTOP(9, BIT(6))),
|
||||
DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
|
||||
BUS_MSTOP(9, BIT(7))),
|
||||
DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28,
|
||||
BUS_MSTOP(9, BIT(7))),
|
||||
DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
|
||||
BUS_MSTOP(9, BIT(7))),
|
||||
};
|
||||
|
||||
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
|
||||
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
|
||||
DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
|
||||
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
|
||||
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
|
||||
DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
|
||||
DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
|
||||
DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
|
||||
@@ -162,6 +251,18 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
|
||||
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
|
||||
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
|
||||
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
|
||||
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
|
||||
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
|
||||
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
|
||||
DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
|
||||
DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
|
||||
DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
|
||||
DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */
|
||||
DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */
|
||||
DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */
|
||||
DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */
|
||||
DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */
|
||||
DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */
|
||||
};
|
||||
|
||||
const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
|
||||
@@ -179,4 +280,6 @@ const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
|
||||
/* Resets */
|
||||
.resets = r9a09g057_resets,
|
||||
.num_resets = ARRAY_SIZE(r9a09g057_resets),
|
||||
|
||||
.num_mstop_bits = 192,
|
||||
};
|
||||
|
||||
@@ -979,7 +979,7 @@ static void __init cpg_mssr_reserved_exit(struct cpg_mssr_priv *priv)
|
||||
static int __init cpg_mssr_reserved_init(struct cpg_mssr_priv *priv,
|
||||
const struct cpg_mssr_info *info)
|
||||
{
|
||||
struct device_node *soc = of_find_node_by_path("/soc");
|
||||
struct device_node *soc __free(device_node) = of_find_node_by_path("/soc");
|
||||
struct device_node *node;
|
||||
uint32_t args[MAX_PHANDLE_ARGS];
|
||||
unsigned int *ids = NULL;
|
||||
|
||||
+172
-26
@@ -23,6 +23,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/refcount.h>
|
||||
#include <linux/reset-controller.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
@@ -40,6 +41,9 @@
|
||||
#define GET_RST_OFFSET(x) (0x900 + ((x) * 4))
|
||||
#define GET_RST_MON_OFFSET(x) (0xA00 + ((x) * 4))
|
||||
|
||||
#define CPG_BUS_1_MSTOP (0xd00)
|
||||
#define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4)
|
||||
|
||||
#define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), (val)))
|
||||
#define MDIV(val) FIELD_GET(GENMASK(15, 6), (val))
|
||||
#define PDIV(val) FIELD_GET(GENMASK(5, 0), (val))
|
||||
@@ -64,6 +68,7 @@
|
||||
* @resets: Array of resets
|
||||
* @num_resets: Number of Module Resets in info->resets[]
|
||||
* @last_dt_core_clk: ID of the last Core Clock exported to DT
|
||||
* @mstop_count: Array of mstop values
|
||||
* @rcdev: Reset controller entity
|
||||
*/
|
||||
struct rzv2h_cpg_priv {
|
||||
@@ -78,6 +83,8 @@ struct rzv2h_cpg_priv {
|
||||
unsigned int num_resets;
|
||||
unsigned int last_dt_core_clk;
|
||||
|
||||
atomic_t *mstop_count;
|
||||
|
||||
struct reset_controller_dev rcdev;
|
||||
};
|
||||
|
||||
@@ -97,7 +104,9 @@ struct pll_clk {
|
||||
* struct mod_clock - Module clock
|
||||
*
|
||||
* @priv: CPG private data
|
||||
* @mstop_data: mstop data relating to module clock
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @no_pm: flag to indicate PM is not supported
|
||||
* @on_index: register offset
|
||||
* @on_bit: ON/MON bit
|
||||
* @mon_index: monitor register offset
|
||||
@@ -105,7 +114,9 @@ struct pll_clk {
|
||||
*/
|
||||
struct mod_clock {
|
||||
struct rzv2h_cpg_priv *priv;
|
||||
unsigned int mstop_data;
|
||||
struct clk_hw hw;
|
||||
bool no_pm;
|
||||
u8 on_index;
|
||||
u8 on_bit;
|
||||
s8 mon_index;
|
||||
@@ -431,8 +442,71 @@ fail:
|
||||
core->name, PTR_ERR(clk));
|
||||
}
|
||||
|
||||
static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv,
|
||||
u32 mstop_data)
|
||||
{
|
||||
unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);
|
||||
u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);
|
||||
unsigned int index = (mstop_index - 1) * 16;
|
||||
atomic_t *mstop = &priv->mstop_count[index];
|
||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
u32 val = 0;
|
||||
|
||||
spin_lock_irqsave(&priv->rmw_lock, flags);
|
||||
for_each_set_bit(i, &mstop_mask, 16) {
|
||||
if (!atomic_read(&mstop[i]))
|
||||
val |= BIT(i) << 16;
|
||||
atomic_inc(&mstop[i]);
|
||||
}
|
||||
if (val)
|
||||
writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
|
||||
spin_unlock_irqrestore(&priv->rmw_lock, flags);
|
||||
}
|
||||
|
||||
static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
|
||||
u32 mstop_data)
|
||||
{
|
||||
unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);
|
||||
u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);
|
||||
unsigned int index = (mstop_index - 1) * 16;
|
||||
atomic_t *mstop = &priv->mstop_count[index];
|
||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
u32 val = 0;
|
||||
|
||||
spin_lock_irqsave(&priv->rmw_lock, flags);
|
||||
for_each_set_bit(i, &mstop_mask, 16) {
|
||||
if (!atomic_read(&mstop[i]) ||
|
||||
atomic_dec_and_test(&mstop[i]))
|
||||
val |= BIT(i) << 16 | BIT(i);
|
||||
}
|
||||
if (val)
|
||||
writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
|
||||
spin_unlock_irqrestore(&priv->rmw_lock, flags);
|
||||
}
|
||||
|
||||
static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct mod_clock *clock = to_mod_clock(hw);
|
||||
struct rzv2h_cpg_priv *priv = clock->priv;
|
||||
u32 bitmask;
|
||||
u32 offset;
|
||||
|
||||
if (clock->mon_index >= 0) {
|
||||
offset = GET_CLK_MON_OFFSET(clock->mon_index);
|
||||
bitmask = BIT(clock->mon_bit);
|
||||
} else {
|
||||
offset = GET_CLK_ON_OFFSET(clock->on_index);
|
||||
bitmask = BIT(clock->on_bit);
|
||||
}
|
||||
|
||||
return readl(priv->base + offset) & bitmask;
|
||||
}
|
||||
|
||||
static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
|
||||
{
|
||||
bool enabled = rzv2h_mod_clock_is_enabled(hw);
|
||||
struct mod_clock *clock = to_mod_clock(hw);
|
||||
unsigned int reg = GET_CLK_ON_OFFSET(clock->on_index);
|
||||
struct rzv2h_cpg_priv *priv = clock->priv;
|
||||
@@ -444,11 +518,20 @@ static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
|
||||
dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,
|
||||
enable ? "ON" : "OFF");
|
||||
|
||||
value = bitmask << 16;
|
||||
if (enable)
|
||||
value |= bitmask;
|
||||
if (enabled == enable)
|
||||
return 0;
|
||||
|
||||
writel(value, priv->base + reg);
|
||||
value = bitmask << 16;
|
||||
if (enable) {
|
||||
value |= bitmask;
|
||||
writel(value, priv->base + reg);
|
||||
if (clock->mstop_data != BUS_MSTOP_NONE)
|
||||
rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);
|
||||
} else {
|
||||
if (clock->mstop_data != BUS_MSTOP_NONE)
|
||||
rzv2h_mod_clock_mstop_disable(priv, clock->mstop_data);
|
||||
writel(value, priv->base + reg);
|
||||
}
|
||||
|
||||
if (!enable || clock->mon_index < 0)
|
||||
return 0;
|
||||
@@ -474,24 +557,6 @@ static void rzv2h_mod_clock_disable(struct clk_hw *hw)
|
||||
rzv2h_mod_clock_endisable(hw, false);
|
||||
}
|
||||
|
||||
static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct mod_clock *clock = to_mod_clock(hw);
|
||||
struct rzv2h_cpg_priv *priv = clock->priv;
|
||||
u32 bitmask;
|
||||
u32 offset;
|
||||
|
||||
if (clock->mon_index >= 0) {
|
||||
offset = GET_CLK_MON_OFFSET(clock->mon_index);
|
||||
bitmask = BIT(clock->mon_bit);
|
||||
} else {
|
||||
offset = GET_CLK_ON_OFFSET(clock->on_index);
|
||||
bitmask = BIT(clock->on_bit);
|
||||
}
|
||||
|
||||
return readl(priv->base + offset) & bitmask;
|
||||
}
|
||||
|
||||
static const struct clk_ops rzv2h_mod_clock_ops = {
|
||||
.enable = rzv2h_mod_clock_enable,
|
||||
.disable = rzv2h_mod_clock_disable,
|
||||
@@ -541,8 +606,10 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
|
||||
clock->on_bit = mod->on_bit;
|
||||
clock->mon_index = mod->mon_index;
|
||||
clock->mon_bit = mod->mon_bit;
|
||||
clock->no_pm = mod->no_pm;
|
||||
clock->priv = priv;
|
||||
clock->hw.init = &init;
|
||||
clock->mstop_data = mod->mstop_data;
|
||||
|
||||
ret = devm_clk_hw_register(dev, &clock->hw);
|
||||
if (ret) {
|
||||
@@ -552,6 +619,41 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
|
||||
|
||||
priv->clks[id] = clock->hw.clk;
|
||||
|
||||
/*
|
||||
* Ensure the module clocks and MSTOP bits are synchronized when they are
|
||||
* turned ON by the bootloader. Enable MSTOP bits for module clocks that were
|
||||
* turned ON in an earlier boot stage.
|
||||
*/
|
||||
if (clock->mstop_data != BUS_MSTOP_NONE &&
|
||||
!mod->critical && rzv2h_mod_clock_is_enabled(&clock->hw)) {
|
||||
rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);
|
||||
} else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) {
|
||||
unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data);
|
||||
u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data);
|
||||
unsigned int index = (mstop_index - 1) * 16;
|
||||
atomic_t *mstop = &priv->mstop_count[index];
|
||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
u32 val = 0;
|
||||
|
||||
/*
|
||||
* Critical clocks are turned ON immediately upon registration, and the
|
||||
* MSTOP counter is updated through the rzv2h_mod_clock_enable() path.
|
||||
* However, if the critical clocks were already turned ON by the initial
|
||||
* bootloader, synchronize the atomic counter here and clear the MSTOP bit.
|
||||
*/
|
||||
spin_lock_irqsave(&priv->rmw_lock, flags);
|
||||
for_each_set_bit(i, &mstop_mask, 16) {
|
||||
if (atomic_read(&mstop[i]))
|
||||
continue;
|
||||
val |= BIT(i) << 16;
|
||||
atomic_inc(&mstop[i]);
|
||||
}
|
||||
if (val)
|
||||
writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
|
||||
spin_unlock_irqrestore(&priv->rmw_lock, flags);
|
||||
}
|
||||
|
||||
return;
|
||||
|
||||
fail:
|
||||
@@ -668,17 +770,51 @@ struct rzv2h_cpg_pd {
|
||||
struct generic_pm_domain genpd;
|
||||
};
|
||||
|
||||
static bool rzv2h_cpg_is_pm_clk(struct rzv2h_cpg_pd *pd,
|
||||
const struct of_phandle_args *clkspec)
|
||||
{
|
||||
if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
|
||||
return false;
|
||||
|
||||
switch (clkspec->args[0]) {
|
||||
case CPG_MOD: {
|
||||
struct rzv2h_cpg_priv *priv = pd->priv;
|
||||
unsigned int id = clkspec->args[1];
|
||||
struct mod_clock *clock;
|
||||
|
||||
if (id >= priv->num_mod_clks)
|
||||
return false;
|
||||
|
||||
if (priv->clks[priv->num_core_clks + id] == ERR_PTR(-ENOENT))
|
||||
return false;
|
||||
|
||||
clock = to_mod_clock(__clk_get_hw(priv->clks[priv->num_core_clks + id]));
|
||||
|
||||
return !clock->no_pm;
|
||||
}
|
||||
|
||||
case CPG_CORE:
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
|
||||
{
|
||||
struct rzv2h_cpg_pd *pd = container_of(domain, struct rzv2h_cpg_pd, genpd);
|
||||
struct device_node *np = dev->of_node;
|
||||
struct of_phandle_args clkspec;
|
||||
bool once = true;
|
||||
struct clk *clk;
|
||||
unsigned int i;
|
||||
int error;
|
||||
int i = 0;
|
||||
|
||||
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
|
||||
&clkspec)) {
|
||||
for (i = 0; !of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec); i++) {
|
||||
if (!rzv2h_cpg_is_pm_clk(pd, &clkspec)) {
|
||||
of_node_put(clkspec.np);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (once) {
|
||||
once = false;
|
||||
error = pm_clk_create(dev);
|
||||
@@ -700,7 +836,6 @@ static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct device
|
||||
error);
|
||||
goto fail_put;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
@@ -786,6 +921,11 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev)
|
||||
if (!clks)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->mstop_count = devm_kcalloc(dev, info->num_mstop_bits,
|
||||
sizeof(*priv->mstop_count), GFP_KERNEL);
|
||||
if (!priv->mstop_count)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) *
|
||||
info->num_resets, GFP_KERNEL);
|
||||
if (!priv->resets)
|
||||
@@ -832,6 +972,12 @@ static const struct of_device_id rzv2h_cpg_match[] = {
|
||||
.compatible = "renesas,r9a09g057-cpg",
|
||||
.data = &r9a09g057_cpg_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R9A09G047
|
||||
{
|
||||
.compatible = "renesas,r9a09g047-cpg",
|
||||
.data = &r9a09g047_cpg_info,
|
||||
},
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
@@ -8,6 +8,8 @@
|
||||
#ifndef __RENESAS_RZV2H_CPG_H__
|
||||
#define __RENESAS_RZV2H_CPG_H__
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
/**
|
||||
* struct ddiv - Structure for dynamic switching divider
|
||||
*
|
||||
@@ -33,12 +35,24 @@ struct ddiv {
|
||||
|
||||
#define CPG_CDDIV0 (0x400)
|
||||
#define CPG_CDDIV1 (0x404)
|
||||
#define CPG_CDDIV3 (0x40C)
|
||||
#define CPG_CDDIV4 (0x410)
|
||||
|
||||
#define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
|
||||
#define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4)
|
||||
#define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
|
||||
#define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
|
||||
#define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
|
||||
#define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15)
|
||||
#define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16)
|
||||
#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
|
||||
#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
|
||||
|
||||
#define BUS_MSTOP_IDX_MASK GENMASK(31, 16)
|
||||
#define BUS_MSTOP_BITS_MASK GENMASK(15, 0)
|
||||
#define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \
|
||||
FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask)))
|
||||
#define BUS_MSTOP_NONE GENMASK(31, 0)
|
||||
|
||||
/**
|
||||
* Definitions of CPG Core Clocks
|
||||
@@ -98,8 +112,10 @@ enum clk_types {
|
||||
* struct rzv2h_mod_clk - Module Clocks definitions
|
||||
*
|
||||
* @name: handle between common and hardware-specific interfaces
|
||||
* @mstop_data: packed data mstop register offset and mask
|
||||
* @parent: id of parent clock
|
||||
* @critical: flag to indicate the clock is critical
|
||||
* @no_pm: flag to indicate PM is not supported
|
||||
* @on_index: control register index
|
||||
* @on_bit: ON bit
|
||||
* @mon_index: monitor register index
|
||||
@@ -107,30 +123,37 @@ enum clk_types {
|
||||
*/
|
||||
struct rzv2h_mod_clk {
|
||||
const char *name;
|
||||
u32 mstop_data;
|
||||
u16 parent;
|
||||
bool critical;
|
||||
bool no_pm;
|
||||
u8 on_index;
|
||||
u8 on_bit;
|
||||
s8 mon_index;
|
||||
u8 mon_bit;
|
||||
};
|
||||
|
||||
#define DEF_MOD_BASE(_name, _parent, _critical, _onindex, _onbit, _monindex, _monbit) \
|
||||
#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
|
||||
{ \
|
||||
.name = (_name), \
|
||||
.mstop_data = (_mstop), \
|
||||
.parent = (_parent), \
|
||||
.critical = (_critical), \
|
||||
.no_pm = (_no_pm), \
|
||||
.on_index = (_onindex), \
|
||||
.on_bit = (_onbit), \
|
||||
.mon_index = (_monindex), \
|
||||
.mon_bit = (_monbit), \
|
||||
}
|
||||
|
||||
#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
|
||||
DEF_MOD_BASE(_name, _parent, false, _onindex, _onbit, _monindex, _monbit)
|
||||
#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
|
||||
DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
|
||||
|
||||
#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
|
||||
DEF_MOD_BASE(_name, _parent, true, _onindex, _onbit, _monindex, _monbit)
|
||||
#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
|
||||
DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit)
|
||||
|
||||
#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
|
||||
DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit)
|
||||
|
||||
/**
|
||||
* struct rzv2h_reset - Reset definitions
|
||||
@@ -172,6 +195,9 @@ struct rzv2h_reset {
|
||||
*
|
||||
* @resets: Array of Module Reset definitions
|
||||
* @num_resets: Number of entries in resets[]
|
||||
*
|
||||
* @num_mstop_bits: Maximum number of MSTOP bits supported, equivalent to the
|
||||
* number of CPG_BUS_m_MSTOP registers multiplied by 16.
|
||||
*/
|
||||
struct rzv2h_cpg_info {
|
||||
/* Core Clocks */
|
||||
@@ -188,8 +214,11 @@ struct rzv2h_cpg_info {
|
||||
/* Resets */
|
||||
const struct rzv2h_reset *resets;
|
||||
unsigned int num_resets;
|
||||
|
||||
unsigned int num_mstop_bits;
|
||||
};
|
||||
|
||||
extern const struct rzv2h_cpg_info r9a09g047_cpg_info;
|
||||
extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
|
||||
|
||||
#endif /* __RENESAS_RZV2H_CPG_H__ */
|
||||
|
||||
@@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8895.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos990.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -430,7 +430,10 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = {
|
||||
#define PLL0822X_LOCK_STAT_SHIFT (29)
|
||||
#define PLL0822X_ENABLE_SHIFT (31)
|
||||
|
||||
/* PLL1418x is similar to PLL0822x, except that MDIV is one bit smaller */
|
||||
/*
|
||||
* PLL1418x, PLL0717x and PLL0718x are similar
|
||||
* to PLL0822x, except that MDIV is one bit smaller
|
||||
*/
|
||||
#define PLL1418X_MDIV_MASK (0x1FF)
|
||||
|
||||
static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
|
||||
@@ -441,10 +444,14 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
|
||||
u64 fvco = parent_rate;
|
||||
|
||||
pll_con3 = readl_relaxed(pll->con_reg);
|
||||
if (pll->type != pll_1418x)
|
||||
|
||||
if (pll->type != pll_1418x &&
|
||||
pll->type != pll_0717x &&
|
||||
pll->type != pll_0718x)
|
||||
mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
|
||||
else
|
||||
mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL1418X_MDIV_MASK;
|
||||
|
||||
pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
|
||||
sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
|
||||
|
||||
@@ -1377,6 +1384,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
case pll_0516x:
|
||||
case pll_0517x:
|
||||
case pll_0518x:
|
||||
case pll_0717x:
|
||||
case pll_0718x:
|
||||
case pll_0732x:
|
||||
pll->enable_offs = PLL0822X_ENABLE_SHIFT;
|
||||
pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
|
||||
if (!pll->rate_table)
|
||||
|
||||
@@ -45,6 +45,9 @@ enum samsung_pll_type {
|
||||
pll_531x,
|
||||
pll_1051x,
|
||||
pll_1052x,
|
||||
pll_0717x,
|
||||
pll_0718x,
|
||||
pll_0732x,
|
||||
};
|
||||
|
||||
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
|
||||
|
||||
@@ -35,7 +35,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
|
||||
unsigned long divf, divq, reg;
|
||||
u32 divf, divq, reg;
|
||||
unsigned long long vco_freq;
|
||||
|
||||
/* read VCO1 reg for numerator and denominator */
|
||||
|
||||
@@ -2,12 +2,12 @@
|
||||
*
|
||||
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
|
||||
#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
|
||||
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__
|
||||
#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__
|
||||
|
||||
#define VBATTB_XC 0
|
||||
#define VBATTB_XBYP 1
|
||||
#define VBATTB_MUX 2
|
||||
#define VBATTB_VBATTCLK 3
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__ */
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
*
|
||||
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
|
||||
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* Core Clock list */
|
||||
#define R9A09G047_SYS_0_PCLK 0
|
||||
#define R9A09G047_CA55_0_CORECLK0 1
|
||||
#define R9A09G047_CA55_0_CORECLK1 2
|
||||
#define R9A09G047_CA55_0_CORECLK2 3
|
||||
#define R9A09G047_CA55_0_CORECLK3 4
|
||||
#define R9A09G047_CA55_0_PERIPHCLK 5
|
||||
#define R9A09G047_CM33_CLK0 6
|
||||
#define R9A09G047_CST_0_SWCLKTCK 7
|
||||
#define R9A09G047_IOTOP_0_SHCLK 8
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
|
||||
@@ -0,0 +1,236 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2024 Igor Belwon <igor.belwon@mentallysanemainliners.org>
|
||||
*
|
||||
* Device Tree binding constants for Exynos990 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_990_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS_990_H
|
||||
|
||||
/* CMU_TOP */
|
||||
#define CLK_FOUT_SHARED0_PLL 1
|
||||
#define CLK_FOUT_SHARED1_PLL 2
|
||||
#define CLK_FOUT_SHARED2_PLL 3
|
||||
#define CLK_FOUT_SHARED3_PLL 4
|
||||
#define CLK_FOUT_SHARED4_PLL 5
|
||||
#define CLK_FOUT_G3D_PLL 6
|
||||
#define CLK_FOUT_MMC_PLL 7
|
||||
#define CLK_MOUT_PLL_SHARED0 8
|
||||
#define CLK_MOUT_PLL_SHARED1 9
|
||||
#define CLK_MOUT_PLL_SHARED2 10
|
||||
#define CLK_MOUT_PLL_SHARED3 11
|
||||
#define CLK_MOUT_PLL_SHARED4 12
|
||||
#define CLK_MOUT_PLL_MMC 13
|
||||
#define CLK_MOUT_PLL_G3D 14
|
||||
#define CLK_MOUT_CMU_APM_BUS 15
|
||||
#define CLK_MOUT_CMU_AUD_CPU 16
|
||||
#define CLK_MOUT_CMU_BUS0_BUS 17
|
||||
#define CLK_MOUT_CMU_BUS1_BUS 18
|
||||
#define CLK_MOUT_CMU_BUS1_SSS 19
|
||||
#define CLK_MOUT_CMU_CIS_CLK0 20
|
||||
#define CLK_MOUT_CMU_CIS_CLK1 21
|
||||
#define CLK_MOUT_CMU_CIS_CLK2 22
|
||||
#define CLK_MOUT_CMU_CIS_CLK3 23
|
||||
#define CLK_MOUT_CMU_CIS_CLK4 24
|
||||
#define CLK_MOUT_CMU_CIS_CLK5 25
|
||||
#define CLK_MOUT_CMU_CMU_BOOST 26
|
||||
#define CLK_MOUT_CMU_CORE_BUS 27
|
||||
#define CLK_MOUT_CMU_CPUCL0_DBG_BUS 28
|
||||
#define CLK_MOUT_CMU_CPUCL0_SWITCH 29
|
||||
#define CLK_MOUT_CMU_CPUCL1_SWITCH 30
|
||||
#define CLK_MOUT_CMU_CPUCL2_BUSP 31
|
||||
#define CLK_MOUT_CMU_CPUCL2_SWITCH 32
|
||||
#define CLK_MOUT_CMU_CSIS_BUS 33
|
||||
#define CLK_MOUT_CMU_CSIS_OIS_MCU 34
|
||||
#define CLK_MOUT_CMU_DNC_BUS 35
|
||||
#define CLK_MOUT_CMU_DNC_BUSM 36
|
||||
#define CLK_MOUT_CMU_DNS_BUS 37
|
||||
#define CLK_MOUT_CMU_DPU 38
|
||||
#define CLK_MOUT_CMU_DPU_ALT 39
|
||||
#define CLK_MOUT_CMU_DSP_BUS 40
|
||||
#define CLK_MOUT_CMU_G2D_G2D 41
|
||||
#define CLK_MOUT_CMU_G2D_MSCL 42
|
||||
#define CLK_MOUT_CMU_HPM 43
|
||||
#define CLK_MOUT_CMU_HSI0_BUS 44
|
||||
#define CLK_MOUT_CMU_HSI0_DPGTC 45
|
||||
#define CLK_MOUT_CMU_HSI0_USB31DRD 46
|
||||
#define CLK_MOUT_CMU_HSI0_USBDP_DEBUG 47
|
||||
#define CLK_MOUT_CMU_HSI1_BUS 48
|
||||
#define CLK_MOUT_CMU_HSI1_MMC_CARD 49
|
||||
#define CLK_MOUT_CMU_HSI1_PCIE 50
|
||||
#define CLK_MOUT_CMU_HSI1_UFS_CARD 51
|
||||
#define CLK_MOUT_CMU_HSI1_UFS_EMBD 52
|
||||
#define CLK_MOUT_CMU_HSI2_BUS 53
|
||||
#define CLK_MOUT_CMU_HSI2_PCIE 54
|
||||
#define CLK_MOUT_CMU_IPP_BUS 55
|
||||
#define CLK_MOUT_CMU_ITP_BUS 56
|
||||
#define CLK_MOUT_CMU_MCSC_BUS 57
|
||||
#define CLK_MOUT_CMU_MCSC_GDC 58
|
||||
#define CLK_MOUT_CMU_CMU_BOOST_CPU 59
|
||||
#define CLK_MOUT_CMU_MFC0_MFC0 60
|
||||
#define CLK_MOUT_CMU_MFC0_WFD 61
|
||||
#define CLK_MOUT_CMU_MIF_BUSP 62
|
||||
#define CLK_MOUT_CMU_MIF_SWITCH 63
|
||||
#define CLK_MOUT_CMU_NPU_BUS 64
|
||||
#define CLK_MOUT_CMU_PERIC0_BUS 65
|
||||
#define CLK_MOUT_CMU_PERIC0_IP 66
|
||||
#define CLK_MOUT_CMU_PERIC1_BUS 67
|
||||
#define CLK_MOUT_CMU_PERIC1_IP 68
|
||||
#define CLK_MOUT_CMU_PERIS_BUS 69
|
||||
#define CLK_MOUT_CMU_SSP_BUS 70
|
||||
#define CLK_MOUT_CMU_TNR_BUS 71
|
||||
#define CLK_MOUT_CMU_VRA_BUS 72
|
||||
#define CLK_DOUT_CMU_APM_BUS 73
|
||||
#define CLK_DOUT_CMU_AUD_CPU 74
|
||||
#define CLK_DOUT_CMU_BUS0_BUS 75
|
||||
#define CLK_DOUT_CMU_BUS1_BUS 76
|
||||
#define CLK_DOUT_CMU_BUS1_SSS 77
|
||||
#define CLK_DOUT_CMU_CIS_CLK0 78
|
||||
#define CLK_DOUT_CMU_CIS_CLK1 79
|
||||
#define CLK_DOUT_CMU_CIS_CLK2 80
|
||||
#define CLK_DOUT_CMU_CIS_CLK3 81
|
||||
#define CLK_DOUT_CMU_CIS_CLK4 82
|
||||
#define CLK_DOUT_CMU_CIS_CLK5 83
|
||||
#define CLK_DOUT_CMU_CMU_BOOST 84
|
||||
#define CLK_DOUT_CMU_CORE_BUS 85
|
||||
#define CLK_DOUT_CMU_CPUCL0_DBG_BUS 86
|
||||
#define CLK_DOUT_CMU_CPUCL0_SWITCH 87
|
||||
#define CLK_DOUT_CMU_CPUCL1_SWITCH 88
|
||||
#define CLK_DOUT_CMU_CPUCL2_BUSP 89
|
||||
#define CLK_DOUT_CMU_CPUCL2_SWITCH 90
|
||||
#define CLK_DOUT_CMU_CSIS_BUS 91
|
||||
#define CLK_DOUT_CMU_CSIS_OIS_MCU 92
|
||||
#define CLK_DOUT_CMU_DNC_BUS 93
|
||||
#define CLK_DOUT_CMU_DNC_BUSM 94
|
||||
#define CLK_DOUT_CMU_DNS_BUS 95
|
||||
#define CLK_DOUT_CMU_DSP_BUS 96
|
||||
#define CLK_DOUT_CMU_G2D_G2D 97
|
||||
#define CLK_DOUT_CMU_G2D_MSCL 98
|
||||
#define CLK_DOUT_CMU_G3D_SWITCH 99
|
||||
#define CLK_DOUT_CMU_HPM 100
|
||||
#define CLK_DOUT_CMU_HSI0_BUS 101
|
||||
#define CLK_DOUT_CMU_HSI0_DPGTC 102
|
||||
#define CLK_DOUT_CMU_HSI0_USB31DRD 103
|
||||
#define CLK_DOUT_CMU_HSI0_USBDP_DEBUG 104
|
||||
#define CLK_DOUT_CMU_HSI1_BUS 105
|
||||
#define CLK_DOUT_CMU_HSI1_MMC_CARD 106
|
||||
#define CLK_DOUT_CMU_HSI1_PCIE 107
|
||||
#define CLK_DOUT_CMU_HSI1_UFS_CARD 108
|
||||
#define CLK_DOUT_CMU_HSI1_UFS_EMBD 109
|
||||
#define CLK_DOUT_CMU_HSI2_BUS 110
|
||||
#define CLK_DOUT_CMU_HSI2_PCIE 111
|
||||
#define CLK_DOUT_CMU_IPP_BUS 112
|
||||
#define CLK_DOUT_CMU_ITP_BUS 113
|
||||
#define CLK_DOUT_CMU_MCSC_BUS 114
|
||||
#define CLK_DOUT_CMU_MCSC_GDC 115
|
||||
#define CLK_DOUT_CMU_CMU_BOOST_CPU 116
|
||||
#define CLK_DOUT_CMU_MFC0_MFC0 117
|
||||
#define CLK_DOUT_CMU_MFC0_WFD 118
|
||||
#define CLK_DOUT_CMU_MIF_BUSP 119
|
||||
#define CLK_DOUT_CMU_NPU_BUS 120
|
||||
#define CLK_DOUT_CMU_OTP 121
|
||||
#define CLK_DOUT_CMU_PERIC0_BUS 122
|
||||
#define CLK_DOUT_CMU_PERIC0_IP 123
|
||||
#define CLK_DOUT_CMU_PERIC1_BUS 124
|
||||
#define CLK_DOUT_CMU_PERIC1_IP 125
|
||||
#define CLK_DOUT_CMU_PERIS_BUS 126
|
||||
#define CLK_DOUT_CMU_SSP_BUS 127
|
||||
#define CLK_DOUT_CMU_TNR_BUS 128
|
||||
#define CLK_DOUT_CMU_VRA_BUS 129
|
||||
#define CLK_DOUT_CMU_DPU 130
|
||||
#define CLK_DOUT_CMU_DPU_ALT 131
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV2 132
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV3 133
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV4 134
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV2 135
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV3 136
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV4 137
|
||||
#define CLK_DOUT_CMU_SHARED2_DIV2 138
|
||||
#define CLK_DOUT_CMU_SHARED4_DIV2 139
|
||||
#define CLK_DOUT_CMU_SHARED4_DIV3 140
|
||||
#define CLK_DOUT_CMU_SHARED4_DIV4 141
|
||||
#define CLK_GOUT_CMU_G3D_BUS 142
|
||||
#define CLK_GOUT_CMU_MIF_SWITCH 143
|
||||
#define CLK_GOUT_CMU_APM_BUS 144
|
||||
#define CLK_GOUT_CMU_AUD_CPU 145
|
||||
#define CLK_GOUT_CMU_BUS0_BUS 146
|
||||
#define CLK_GOUT_CMU_BUS1_BUS 147
|
||||
#define CLK_GOUT_CMU_BUS1_SSS 148
|
||||
#define CLK_GOUT_CMU_CIS_CLK0 149
|
||||
#define CLK_GOUT_CMU_CIS_CLK1 150
|
||||
#define CLK_GOUT_CMU_CIS_CLK2 151
|
||||
#define CLK_GOUT_CMU_CIS_CLK3 152
|
||||
#define CLK_GOUT_CMU_CIS_CLK4 153
|
||||
#define CLK_GOUT_CMU_CIS_CLK5 154
|
||||
#define CLK_GOUT_CMU_CORE_BUS 155
|
||||
#define CLK_GOUT_CMU_CPUCL0_DBG_BUS 156
|
||||
#define CLK_GOUT_CMU_CPUCL0_SWITCH 157
|
||||
#define CLK_GOUT_CMU_CPUCL1_SWITCH 158
|
||||
#define CLK_GOUT_CMU_CPUCL2_BUSP 159
|
||||
#define CLK_GOUT_CMU_CPUCL2_SWITCH 160
|
||||
#define CLK_GOUT_CMU_CSIS_BUS 161
|
||||
#define CLK_GOUT_CMU_CSIS_OIS_MCU 162
|
||||
#define CLK_GOUT_CMU_DNC_BUS 163
|
||||
#define CLK_GOUT_CMU_DNC_BUSM 164
|
||||
#define CLK_GOUT_CMU_DNS_BUS 165
|
||||
#define CLK_GOUT_CMU_DPU 166
|
||||
#define CLK_GOUT_CMU_DPU_BUS 167
|
||||
#define CLK_GOUT_CMU_DSP_BUS 168
|
||||
#define CLK_GOUT_CMU_G2D_G2D 169
|
||||
#define CLK_GOUT_CMU_G2D_MSCL 170
|
||||
#define CLK_GOUT_CMU_G3D_SWITCH 171
|
||||
#define CLK_GOUT_CMU_HPM 172
|
||||
#define CLK_GOUT_CMU_HSI0_BUS 173
|
||||
#define CLK_GOUT_CMU_HSI0_DPGTC 174
|
||||
#define CLK_GOUT_CMU_HSI0_USB31DRD 175
|
||||
#define CLK_GOUT_CMU_HSI0_USBDP_DEBUG 176
|
||||
#define CLK_GOUT_CMU_HSI1_BUS 177
|
||||
#define CLK_GOUT_CMU_HSI1_MMC_CARD 178
|
||||
#define CLK_GOUT_CMU_HSI1_PCIE 179
|
||||
#define CLK_GOUT_CMU_HSI1_UFS_CARD 180
|
||||
#define CLK_GOUT_CMU_HSI1_UFS_EMBD 181
|
||||
#define CLK_GOUT_CMU_HSI2_BUS 182
|
||||
#define CLK_GOUT_CMU_HSI2_PCIE 183
|
||||
#define CLK_GOUT_CMU_IPP_BUS 184
|
||||
#define CLK_GOUT_CMU_ITP_BUS 185
|
||||
#define CLK_GOUT_CMU_MCSC_BUS 186
|
||||
#define CLK_GOUT_CMU_MCSC_GDC 187
|
||||
#define CLK_GOUT_CMU_MFC0_MFC0 188
|
||||
#define CLK_GOUT_CMU_MFC0_WFD 189
|
||||
#define CLK_GOUT_CMU_MIF_BUSP 190
|
||||
#define CLK_GOUT_CMU_NPU_BUS 191
|
||||
#define CLK_GOUT_CMU_PERIC0_BUS 192
|
||||
#define CLK_GOUT_CMU_PERIC0_IP 193
|
||||
#define CLK_GOUT_CMU_PERIC1_BUS 194
|
||||
#define CLK_GOUT_CMU_PERIC1_IP 195
|
||||
#define CLK_GOUT_CMU_PERIS_BUS 196
|
||||
#define CLK_GOUT_CMU_SSP_BUS 197
|
||||
#define CLK_GOUT_CMU_TNR_BUS 198
|
||||
#define CLK_GOUT_CMU_VRA_BUS 199
|
||||
|
||||
/* CMU_HSI0 */
|
||||
#define CLK_MOUT_HSI0_BUS_USER 1
|
||||
#define CLK_MOUT_HSI0_USB31DRD_USER 2
|
||||
#define CLK_MOUT_HSI0_USBDP_DEBUG_USER 3
|
||||
#define CLK_MOUT_HSI0_DPGTC_USER 4
|
||||
#define CLK_GOUT_HSI0_DP_LINK_DP_GTC_CLK 5
|
||||
#define CLK_GOUT_HSI0_DP_LINK_PCLK 6
|
||||
#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK 7
|
||||
#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_CLK 8
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_ACLK 9
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_PCLK 10
|
||||
#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK 11
|
||||
#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2 12
|
||||
#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK 13
|
||||
#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL 14
|
||||
#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY 15
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40 16
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_REF_SOC_PLL 17
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_SCL_APB 18
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USBPCS_APB_CLK 19
|
||||
#define CLK_GOUT_HSI0_VGEN_LITE_HSI0_CLK 20
|
||||
#define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21
|
||||
#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user