Merge tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the RZ/G3E (R9A09G047) SoC
- Add Module Stop (MSTOP) support on RZ/V2H
- Add Image Signal Processor helper block (FCPVX and VSPX) clocks on
R-Car V4H SoC
- Add System Controller (SYS) reset and Generic Interrupt Controller
(GIC) clock and reset entries on RZ/V2H
* tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard
clk: renesas: r9a09g057: Add clock and reset entries for GIC
clk: renesas: r9a09g057: Add reset entry for SYS
clk: renesas: r8a779g0: Add VSPX clocks
clk: renesas: r8a779g0: Add FCPVX clocks
clk: renesas: r9a09g047: Add I2C clocks/resets
clk: renesas: r9a09g047: Add CA55 core clocks
clk: renesas: rzv2h: Add support for RZ/G3E SoC
clk: renesas: rzv2h: Add MSTOP support
dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
This commit is contained in:
Stephen Boyd
@@ -4,19 +4,22 @@
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$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
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title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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description:
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On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
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and control of clock signals for the IP modules, generation and control of resets,
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and control over booting, low power consumption and power supply domains.
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On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
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generation and control of clock signals for the IP modules, generation and
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control of resets, and control over booting, low power consumption and power
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supply domains.
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properties:
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compatible:
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const: renesas,r9a09g057-cpg
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enum:
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- renesas,r9a09g047-cpg # RZ/G3E
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- renesas,r9a09g057-cpg # RZ/V2H
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reg:
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maxItems: 1
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@@ -37,7 +40,7 @@ properties:
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description: |
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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and a core clock reference, as defined in
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<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
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<dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
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- For module clocks, the two clock specifier cells must be "CPG_MOD" and
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a module number. The module number is calculated as the CLKON register
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offset index multiplied by 16, plus the actual bit in the register
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@@ -525,6 +525,23 @@ properties:
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- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
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- const: renesas,r9a09g011
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- description: RZ/G3E (R9A09G047)
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items:
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- enum:
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- renesas,smarc2-evk # RZ SMARC Carrier-II EVK
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- enum:
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- renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
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- enum:
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- renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)
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- renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)
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- renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
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- renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
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- renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)
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- renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)
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- renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
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- renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
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- const: renesas,r9a09g047
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- description: RZ/V2H(P) (R9A09G057)
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items:
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- enum:
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@@ -40,6 +40,7 @@ config CLK_RENESAS
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select CLK_R9A07G054 if ARCH_R9A07G054
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select CLK_R9A08G045 if ARCH_R9A08G045
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select CLK_R9A09G011 if ARCH_R9A09G011
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select CLK_R9A09G047 if ARCH_R9A09G047
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select CLK_R9A09G057 if ARCH_R9A09G057
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select CLK_SH73A0 if ARCH_SH73A0
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@@ -194,6 +195,10 @@ config CLK_R9A09G011
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bool "RZ/V2M clock support" if COMPILE_TEST
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select CLK_RZG2L
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config CLK_R9A09G047
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bool "RZ/G3E clock support" if COMPILE_TEST
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select CLK_RZV2H
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config CLK_R9A09G057
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bool "RZ/V2H(P) clock support" if COMPILE_TEST
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select CLK_RZV2H
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@@ -234,7 +239,7 @@ config CLK_RZG2L
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select RESET_CONTROLLER
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config CLK_RZV2H
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bool "RZ/V2H(P) family clock support" if COMPILE_TEST
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bool "RZ/{G3E,V2H(P)} family clock support" if COMPILE_TEST
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select RESET_CONTROLLER
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config CLK_RENESAS_VBATTB
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@@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
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obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
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obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
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obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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@@ -238,6 +238,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
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DEF_MOD("pfc2", 917, R8A779G0_CLK_CP),
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DEF_MOD("pfc3", 918, R8A779G0_CLK_CP),
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DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
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DEF_MOD("vspx0", 1028, R8A779G0_CLK_S0D1_VIO),
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DEF_MOD("vspx1", 1029, R8A779G0_CLK_S0D1_VIO),
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DEF_MOD("fcpvx0", 1100, R8A779G0_CLK_S0D1_VIO),
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DEF_MOD("fcpvx1", 1101, R8A779G0_CLK_S0D1_VIO),
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DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC),
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DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
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DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
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@@ -0,0 +1,150 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G3E CPG driver
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
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#include "rzv2h-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK,
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/* External Input Clocks */
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CLK_AUDIO_EXTAL,
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CLK_RTXIN,
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CLK_QEXTAL,
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/* PLL Clocks */
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CLK_PLLCM33,
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CLK_PLLCLN,
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CLK_PLLDTY,
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CLK_PLLCA55,
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/* Internal Core Clocks */
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CLK_PLLCM33_DIV16,
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CLK_PLLCLN_DIV16,
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CLK_PLLDTY_ACPU,
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CLK_PLLDTY_ACPU_DIV4,
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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static const struct clk_div_table dtable_1_8[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{3, 8},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_64[] = {
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{0, 2},
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{1, 4},
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{2, 8},
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{3, 16},
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{4, 64},
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{0, 0},
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};
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static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
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DEF_INPUT("rtxin", CLK_RTXIN),
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DEF_INPUT("qextal", CLK_QEXTAL),
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/* PLL Clocks */
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DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
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/* Internal Core Clocks */
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DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
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DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
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DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
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DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
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/* Core Clocks */
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DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
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DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,
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CDDIV1_DIVCTL0, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55,
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CDDIV1_DIVCTL1, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55,
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CDDIV1_DIVCTL2, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55,
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CDDIV1_DIVCTL3, dtable_1_8),
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DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
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};
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static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
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DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
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BUS_MSTOP(3, BIT(5))),
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DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
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BUS_MSTOP(3, BIT(14))),
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DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
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BUS_MSTOP(3, BIT(13))),
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DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
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BUS_MSTOP(1, BIT(1))),
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DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
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BUS_MSTOP(1, BIT(2))),
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DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
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BUS_MSTOP(1, BIT(3))),
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DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
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BUS_MSTOP(1, BIT(4))),
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DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
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BUS_MSTOP(1, BIT(5))),
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DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
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BUS_MSTOP(1, BIT(6))),
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DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
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BUS_MSTOP(1, BIT(7))),
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DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
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BUS_MSTOP(1, BIT(8))),
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};
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static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
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DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
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DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
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DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
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DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
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DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
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DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
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DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
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DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
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DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
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DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
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DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
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DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
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DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
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};
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const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
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/* Core Clocks */
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.core_clks = r9a09g047_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a09g047_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Module Clocks */
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.mod_clks = r9a09g047_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks),
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.num_hw_mod_clks = 28 * 16,
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/* Resets */
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.resets = r9a09g047_resets,
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.num_resets = ARRAY_SIZE(r9a09g047_resets),
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.num_mstop_bits = 208,
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};
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@@ -115,61 +115,117 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
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};
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static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
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DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5),
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DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3),
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DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4),
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DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5),
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DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6),
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DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7),
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DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8),
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DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9),
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DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10),
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DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11),
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DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12),
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DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13),
|
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DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14),
|
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DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15),
|
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DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16),
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DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17),
|
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DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18),
|
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DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15),
|
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DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19),
|
||||
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20),
|
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DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21),
|
||||
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22),
|
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DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23),
|
||||
DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24),
|
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DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25),
|
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DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26),
|
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DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27),
|
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DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3),
|
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DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4),
|
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DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5),
|
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DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6),
|
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DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7),
|
||||
DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8),
|
||||
DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9),
|
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DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10),
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DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11),
|
||||
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12),
|
||||
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13),
|
||||
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),
|
||||
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18),
|
||||
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19),
|
||||
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20),
|
||||
DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21),
|
||||
DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22),
|
||||
DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23),
|
||||
DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24),
|
||||
DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25),
|
||||
DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26),
|
||||
DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27),
|
||||
DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28),
|
||||
DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29),
|
||||
DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
|
||||
BUS_MSTOP_NONE),
|
||||
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
|
||||
BUS_MSTOP(3, BIT(5))),
|
||||
DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
|
||||
BUS_MSTOP(5, BIT(10))),
|
||||
DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
|
||||
BUS_MSTOP(5, BIT(11))),
|
||||
DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
|
||||
BUS_MSTOP(2, BIT(13))),
|
||||
DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
|
||||
BUS_MSTOP(2, BIT(14))),
|
||||
DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
|
||||
BUS_MSTOP(11, BIT(13))),
|
||||
DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
|
||||
BUS_MSTOP(11, BIT(14))),
|
||||
DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
|
||||
BUS_MSTOP(11, BIT(15))),
|
||||
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
|
||||
BUS_MSTOP(12, BIT(0))),
|
||||
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
|
||||
BUS_MSTOP(3, BIT(10))),
|
||||
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
|
||||
BUS_MSTOP(3, BIT(10))),
|
||||
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
|
||||
BUS_MSTOP(1, BIT(0))),
|
||||
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
|
||||
BUS_MSTOP(1, BIT(0))),
|
||||
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
|
||||
BUS_MSTOP(5, BIT(12))),
|
||||
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
|
||||
BUS_MSTOP(5, BIT(12))),
|
||||
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
|
||||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
|
||||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
|
||||
BUS_MSTOP(3, BIT(14))),
|
||||
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
|
||||
BUS_MSTOP(3, BIT(13))),
|
||||
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
|
||||
BUS_MSTOP(1, BIT(1))),
|
||||
DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
|
||||
BUS_MSTOP(1, BIT(2))),
|
||||
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
|
||||
BUS_MSTOP(1, BIT(3))),
|
||||
DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
|
||||
BUS_MSTOP(1, BIT(4))),
|
||||
DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
|
||||
BUS_MSTOP(1, BIT(5))),
|
||||
DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
|
||||
BUS_MSTOP(1, BIT(6))),
|
||||
DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
|
||||
BUS_MSTOP(1, BIT(7))),
|
||||
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
|
||||
BUS_MSTOP(1, BIT(8))),
|
||||
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
|
||||
BUS_MSTOP(8, BIT(2))),
|
||||
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
|
||||
BUS_MSTOP(8, BIT(2))),
|
||||
DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
|
||||
BUS_MSTOP(8, BIT(2))),
|
||||
DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
|
||||
BUS_MSTOP(8, BIT(2))),
|
||||
DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
|
||||
BUS_MSTOP(8, BIT(3))),
|
||||
DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
|
||||
BUS_MSTOP(8, BIT(3))),
|
||||
DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
|
||||
BUS_MSTOP(8, BIT(3))),
|
||||
DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
|
||||
BUS_MSTOP(8, BIT(3))),
|
||||
DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
|
||||
BUS_MSTOP(9, BIT(5))),
|
||||
DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
|
||||
BUS_MSTOP(9, BIT(5))),
|
||||
DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
|
||||
BUS_MSTOP(9, BIT(5))),
|
||||
DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
|
||||
BUS_MSTOP(9, BIT(6))),
|
||||
DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
|
||||
BUS_MSTOP(9, BIT(6))),
|
||||
DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
|
||||
BUS_MSTOP(9, BIT(6))),
|
||||
DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
|
||||
BUS_MSTOP(9, BIT(7))),
|
||||
DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28,
|
||||
BUS_MSTOP(9, BIT(7))),
|
||||
DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
|
||||
BUS_MSTOP(9, BIT(7))),
|
||||
};
|
||||
|
||||
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
|
||||
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
|
||||
DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
|
||||
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
|
||||
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
|
||||
DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
|
||||
DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
|
||||
DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
|
||||
@@ -224,4 +280,6 @@ const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
|
||||
/* Resets */
|
||||
.resets = r9a09g057_resets,
|
||||
.num_resets = ARRAY_SIZE(r9a09g057_resets),
|
||||
|
||||
.num_mstop_bits = 192,
|
||||
};
|
||||
|
||||
+132
-22
@@ -23,6 +23,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/refcount.h>
|
||||
#include <linux/reset-controller.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
@@ -40,6 +41,9 @@
|
||||
#define GET_RST_OFFSET(x) (0x900 + ((x) * 4))
|
||||
#define GET_RST_MON_OFFSET(x) (0xA00 + ((x) * 4))
|
||||
|
||||
#define CPG_BUS_1_MSTOP (0xd00)
|
||||
#define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4)
|
||||
|
||||
#define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), (val)))
|
||||
#define MDIV(val) FIELD_GET(GENMASK(15, 6), (val))
|
||||
#define PDIV(val) FIELD_GET(GENMASK(5, 0), (val))
|
||||
@@ -64,6 +68,7 @@
|
||||
* @resets: Array of resets
|
||||
* @num_resets: Number of Module Resets in info->resets[]
|
||||
* @last_dt_core_clk: ID of the last Core Clock exported to DT
|
||||
* @mstop_count: Array of mstop values
|
||||
* @rcdev: Reset controller entity
|
||||
*/
|
||||
struct rzv2h_cpg_priv {
|
||||
@@ -78,6 +83,8 @@ struct rzv2h_cpg_priv {
|
||||
unsigned int num_resets;
|
||||
unsigned int last_dt_core_clk;
|
||||
|
||||
atomic_t *mstop_count;
|
||||
|
||||
struct reset_controller_dev rcdev;
|
||||
};
|
||||
|
||||
@@ -97,6 +104,7 @@ struct pll_clk {
|
||||
* struct mod_clock - Module clock
|
||||
*
|
||||
* @priv: CPG private data
|
||||
* @mstop_data: mstop data relating to module clock
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @no_pm: flag to indicate PM is not supported
|
||||
* @on_index: register offset
|
||||
@@ -106,6 +114,7 @@ struct pll_clk {
|
||||
*/
|
||||
struct mod_clock {
|
||||
struct rzv2h_cpg_priv *priv;
|
||||
unsigned int mstop_data;
|
||||
struct clk_hw hw;
|
||||
bool no_pm;
|
||||
u8 on_index;
|
||||
@@ -433,8 +442,71 @@ fail:
|
||||
core->name, PTR_ERR(clk));
|
||||
}
|
||||
|
||||
static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv,
|
||||
u32 mstop_data)
|
||||
{
|
||||
unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);
|
||||
u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);
|
||||
unsigned int index = (mstop_index - 1) * 16;
|
||||
atomic_t *mstop = &priv->mstop_count[index];
|
||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
u32 val = 0;
|
||||
|
||||
spin_lock_irqsave(&priv->rmw_lock, flags);
|
||||
for_each_set_bit(i, &mstop_mask, 16) {
|
||||
if (!atomic_read(&mstop[i]))
|
||||
val |= BIT(i) << 16;
|
||||
atomic_inc(&mstop[i]);
|
||||
}
|
||||
if (val)
|
||||
writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
|
||||
spin_unlock_irqrestore(&priv->rmw_lock, flags);
|
||||
}
|
||||
|
||||
static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
|
||||
u32 mstop_data)
|
||||
{
|
||||
unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);
|
||||
u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);
|
||||
unsigned int index = (mstop_index - 1) * 16;
|
||||
atomic_t *mstop = &priv->mstop_count[index];
|
||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
u32 val = 0;
|
||||
|
||||
spin_lock_irqsave(&priv->rmw_lock, flags);
|
||||
for_each_set_bit(i, &mstop_mask, 16) {
|
||||
if (!atomic_read(&mstop[i]) ||
|
||||
atomic_dec_and_test(&mstop[i]))
|
||||
val |= BIT(i) << 16 | BIT(i);
|
||||
}
|
||||
if (val)
|
||||
writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
|
||||
spin_unlock_irqrestore(&priv->rmw_lock, flags);
|
||||
}
|
||||
|
||||
static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct mod_clock *clock = to_mod_clock(hw);
|
||||
struct rzv2h_cpg_priv *priv = clock->priv;
|
||||
u32 bitmask;
|
||||
u32 offset;
|
||||
|
||||
if (clock->mon_index >= 0) {
|
||||
offset = GET_CLK_MON_OFFSET(clock->mon_index);
|
||||
bitmask = BIT(clock->mon_bit);
|
||||
} else {
|
||||
offset = GET_CLK_ON_OFFSET(clock->on_index);
|
||||
bitmask = BIT(clock->on_bit);
|
||||
}
|
||||
|
||||
return readl(priv->base + offset) & bitmask;
|
||||
}
|
||||
|
||||
static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
|
||||
{
|
||||
bool enabled = rzv2h_mod_clock_is_enabled(hw);
|
||||
struct mod_clock *clock = to_mod_clock(hw);
|
||||
unsigned int reg = GET_CLK_ON_OFFSET(clock->on_index);
|
||||
struct rzv2h_cpg_priv *priv = clock->priv;
|
||||
@@ -446,11 +518,20 @@ static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
|
||||
dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,
|
||||
enable ? "ON" : "OFF");
|
||||
|
||||
value = bitmask << 16;
|
||||
if (enable)
|
||||
value |= bitmask;
|
||||
if (enabled == enable)
|
||||
return 0;
|
||||
|
||||
writel(value, priv->base + reg);
|
||||
value = bitmask << 16;
|
||||
if (enable) {
|
||||
value |= bitmask;
|
||||
writel(value, priv->base + reg);
|
||||
if (clock->mstop_data != BUS_MSTOP_NONE)
|
||||
rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);
|
||||
} else {
|
||||
if (clock->mstop_data != BUS_MSTOP_NONE)
|
||||
rzv2h_mod_clock_mstop_disable(priv, clock->mstop_data);
|
||||
writel(value, priv->base + reg);
|
||||
}
|
||||
|
||||
if (!enable || clock->mon_index < 0)
|
||||
return 0;
|
||||
@@ -476,24 +557,6 @@ static void rzv2h_mod_clock_disable(struct clk_hw *hw)
|
||||
rzv2h_mod_clock_endisable(hw, false);
|
||||
}
|
||||
|
||||
static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct mod_clock *clock = to_mod_clock(hw);
|
||||
struct rzv2h_cpg_priv *priv = clock->priv;
|
||||
u32 bitmask;
|
||||
u32 offset;
|
||||
|
||||
if (clock->mon_index >= 0) {
|
||||
offset = GET_CLK_MON_OFFSET(clock->mon_index);
|
||||
bitmask = BIT(clock->mon_bit);
|
||||
} else {
|
||||
offset = GET_CLK_ON_OFFSET(clock->on_index);
|
||||
bitmask = BIT(clock->on_bit);
|
||||
}
|
||||
|
||||
return readl(priv->base + offset) & bitmask;
|
||||
}
|
||||
|
||||
static const struct clk_ops rzv2h_mod_clock_ops = {
|
||||
.enable = rzv2h_mod_clock_enable,
|
||||
.disable = rzv2h_mod_clock_disable,
|
||||
@@ -546,6 +609,7 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
|
||||
clock->no_pm = mod->no_pm;
|
||||
clock->priv = priv;
|
||||
clock->hw.init = &init;
|
||||
clock->mstop_data = mod->mstop_data;
|
||||
|
||||
ret = devm_clk_hw_register(dev, &clock->hw);
|
||||
if (ret) {
|
||||
@@ -555,6 +619,41 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
|
||||
|
||||
priv->clks[id] = clock->hw.clk;
|
||||
|
||||
/*
|
||||
* Ensure the module clocks and MSTOP bits are synchronized when they are
|
||||
* turned ON by the bootloader. Enable MSTOP bits for module clocks that were
|
||||
* turned ON in an earlier boot stage.
|
||||
*/
|
||||
if (clock->mstop_data != BUS_MSTOP_NONE &&
|
||||
!mod->critical && rzv2h_mod_clock_is_enabled(&clock->hw)) {
|
||||
rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);
|
||||
} else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) {
|
||||
unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data);
|
||||
u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data);
|
||||
unsigned int index = (mstop_index - 1) * 16;
|
||||
atomic_t *mstop = &priv->mstop_count[index];
|
||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
u32 val = 0;
|
||||
|
||||
/*
|
||||
* Critical clocks are turned ON immediately upon registration, and the
|
||||
* MSTOP counter is updated through the rzv2h_mod_clock_enable() path.
|
||||
* However, if the critical clocks were already turned ON by the initial
|
||||
* bootloader, synchronize the atomic counter here and clear the MSTOP bit.
|
||||
*/
|
||||
spin_lock_irqsave(&priv->rmw_lock, flags);
|
||||
for_each_set_bit(i, &mstop_mask, 16) {
|
||||
if (atomic_read(&mstop[i]))
|
||||
continue;
|
||||
val |= BIT(i) << 16;
|
||||
atomic_inc(&mstop[i]);
|
||||
}
|
||||
if (val)
|
||||
writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
|
||||
spin_unlock_irqrestore(&priv->rmw_lock, flags);
|
||||
}
|
||||
|
||||
return;
|
||||
|
||||
fail:
|
||||
@@ -822,6 +921,11 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev)
|
||||
if (!clks)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->mstop_count = devm_kcalloc(dev, info->num_mstop_bits,
|
||||
sizeof(*priv->mstop_count), GFP_KERNEL);
|
||||
if (!priv->mstop_count)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) *
|
||||
info->num_resets, GFP_KERNEL);
|
||||
if (!priv->resets)
|
||||
@@ -868,6 +972,12 @@ static const struct of_device_id rzv2h_cpg_match[] = {
|
||||
.compatible = "renesas,r9a09g057-cpg",
|
||||
.data = &r9a09g057_cpg_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R9A09G047
|
||||
{
|
||||
.compatible = "renesas,r9a09g047-cpg",
|
||||
.data = &r9a09g047_cpg_info,
|
||||
},
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
@@ -8,6 +8,8 @@
|
||||
#ifndef __RENESAS_RZV2H_CPG_H__
|
||||
#define __RENESAS_RZV2H_CPG_H__
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
/**
|
||||
* struct ddiv - Structure for dynamic switching divider
|
||||
*
|
||||
@@ -46,6 +48,12 @@ struct ddiv {
|
||||
#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
|
||||
#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
|
||||
|
||||
#define BUS_MSTOP_IDX_MASK GENMASK(31, 16)
|
||||
#define BUS_MSTOP_BITS_MASK GENMASK(15, 0)
|
||||
#define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \
|
||||
FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask)))
|
||||
#define BUS_MSTOP_NONE GENMASK(31, 0)
|
||||
|
||||
/**
|
||||
* Definitions of CPG Core Clocks
|
||||
*
|
||||
@@ -104,6 +112,7 @@ enum clk_types {
|
||||
* struct rzv2h_mod_clk - Module Clocks definitions
|
||||
*
|
||||
* @name: handle between common and hardware-specific interfaces
|
||||
* @mstop_data: packed data mstop register offset and mask
|
||||
* @parent: id of parent clock
|
||||
* @critical: flag to indicate the clock is critical
|
||||
* @no_pm: flag to indicate PM is not supported
|
||||
@@ -114,6 +123,7 @@ enum clk_types {
|
||||
*/
|
||||
struct rzv2h_mod_clk {
|
||||
const char *name;
|
||||
u32 mstop_data;
|
||||
u16 parent;
|
||||
bool critical;
|
||||
bool no_pm;
|
||||
@@ -123,9 +133,10 @@ struct rzv2h_mod_clk {
|
||||
u8 mon_bit;
|
||||
};
|
||||
|
||||
#define DEF_MOD_BASE(_name, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
|
||||
#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
|
||||
{ \
|
||||
.name = (_name), \
|
||||
.mstop_data = (_mstop), \
|
||||
.parent = (_parent), \
|
||||
.critical = (_critical), \
|
||||
.no_pm = (_no_pm), \
|
||||
@@ -135,14 +146,14 @@ struct rzv2h_mod_clk {
|
||||
.mon_bit = (_monbit), \
|
||||
}
|
||||
|
||||
#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
|
||||
DEF_MOD_BASE(_name, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
|
||||
#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
|
||||
DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
|
||||
|
||||
#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
|
||||
DEF_MOD_BASE(_name, _parent, true, false, _onindex, _onbit, _monindex, _monbit)
|
||||
#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
|
||||
DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit)
|
||||
|
||||
#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
|
||||
DEF_MOD_BASE(_name, _parent, false, true, _onindex, _onbit, _monindex, _monbit)
|
||||
#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
|
||||
DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit)
|
||||
|
||||
/**
|
||||
* struct rzv2h_reset - Reset definitions
|
||||
@@ -184,6 +195,9 @@ struct rzv2h_reset {
|
||||
*
|
||||
* @resets: Array of Module Reset definitions
|
||||
* @num_resets: Number of entries in resets[]
|
||||
*
|
||||
* @num_mstop_bits: Maximum number of MSTOP bits supported, equivalent to the
|
||||
* number of CPG_BUS_m_MSTOP registers multiplied by 16.
|
||||
*/
|
||||
struct rzv2h_cpg_info {
|
||||
/* Core Clocks */
|
||||
@@ -200,8 +214,11 @@ struct rzv2h_cpg_info {
|
||||
/* Resets */
|
||||
const struct rzv2h_reset *resets;
|
||||
unsigned int num_resets;
|
||||
|
||||
unsigned int num_mstop_bits;
|
||||
};
|
||||
|
||||
extern const struct rzv2h_cpg_info r9a09g047_cpg_info;
|
||||
extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
|
||||
|
||||
#endif /* __RENESAS_RZV2H_CPG_H__ */
|
||||
|
||||
@@ -2,12 +2,12 @@
|
||||
*
|
||||
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
|
||||
#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
|
||||
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__
|
||||
#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__
|
||||
|
||||
#define VBATTB_XC 0
|
||||
#define VBATTB_XBYP 1
|
||||
#define VBATTB_MUX 2
|
||||
#define VBATTB_VBATTCLK 3
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__ */
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
*
|
||||
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
|
||||
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* Core Clock list */
|
||||
#define R9A09G047_SYS_0_PCLK 0
|
||||
#define R9A09G047_CA55_0_CORECLK0 1
|
||||
#define R9A09G047_CA55_0_CORECLK1 2
|
||||
#define R9A09G047_CA55_0_CORECLK2 3
|
||||
#define R9A09G047_CA55_0_CORECLK3 4
|
||||
#define R9A09G047_CA55_0_PERIPHCLK 5
|
||||
#define R9A09G047_CM33_CLK0 6
|
||||
#define R9A09G047_CST_0_SWCLKTCK 7
|
||||
#define R9A09G047_IOTOP_0_SHCLK 8
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
|
||||
Reference in New Issue
Block a user