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PENDING: arm64: dts: ti: k3-j784s4-main: Add DDR nodes for J784S4

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Add DT nodes for the 4 DDR controllers on the J784S4 device. These define
the memory controller with its register regions, interrupts, power
domains, and clock requirements.

This allows for DDR controller temperature monitoring.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
This commit is contained in:
Neha Malcom Francis
2026-01-22 16:55:01 +05:30
committed by Udit Kumar
parent be5943a0d8
commit 57b7ba68ef
1 changed files with 84 additions and 0 deletions
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arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+84
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@@ -149,6 +149,90 @@
assigned-clocks = <&k3_clks 355 0>;
assigned-clock-parents = <&k3_clks 355 4>;
};
memorycontroller0: memory-controller@2980000 {
compatible = "ti,j7-ddrss";
reg = <0x0 0x02980000 0x0 0x200>;
reg-names = "ss_cfg";
ranges = <0x00 0x00 0x00 0x02990000 0x00 0x00004000>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
<&k3_pds 46 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 191 1>;
#address-cells = <2>;
#size-cells = <2>;
ddr0: ddr@0 {
compatible = "cdns,j7-ddr";
reg = <0x00 0x0000 0x00 0x72c>,
<0x00 0x2000 0x00 0x4b0>,
<0x00 0x4000 0x00 0x163c>;
reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
};
};
memorycontroller1: memory-controller@29a0000 {
compatible = "ti,j7-ddrss";
reg = <0x0 0x029a0000 0x0 0x200>;
reg-names = "ss_cfg";
ranges = <0x00 0x00 0x00 0x029b0000 0x00 0x00004000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
<&k3_pds 47 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 192 1>;
#address-cells = <2>;
#size-cells = <2>;
ddr1: ddr@0 {
compatible = "cdns,j7-ddr";
reg = <0x00 0x0000 0x00 0x72c>,
<0x00 0x2000 0x00 0x4b0>,
<0x00 0x4000 0x00 0x163c>;
reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
};
};
memorycontroller2: memory-controller@29c0000 {
compatible = "ti,j7-ddrss";
reg = <0x0 0x029c0000 0x0 0x200>;
reg-names = "ss_cfg";
ranges = <0x00 0x00 0x00 0x029d0000 0x00 0x00004000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
<&k3_pds 48 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 193 1>;
#address-cells = <2>;
#size-cells = <2>;
ddr2: ddr@0 {
compatible = "cdns,j7-ddr";
reg = <0x00 0x0000 0x00 0x72c>,
<0x00 0x2000 0x00 0x4b0>,
<0x00 0x4000 0x00 0x163c>;
reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
};
};
memorycontroller3: memory-controller@29e0000 {
compatible = "ti,j7-ddrss";
reg = <0x0 0x029e0000 0x0 0x200>;
reg-names = "ss_cfg";
ranges = <0x00 0x00 0x00 0x029f0000 0x00 0x00004000>;
interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
<&k3_pds 49 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 194 1>;
#address-cells = <2>;
#size-cells = <2>;
ddr3: ddr@0 {
compatible = "cdns,j7-ddr";
reg = <0x00 0x0000 0x00 0x72c>,
<0x00 0x2000 0x00 0x4b0>,
<0x00 0x4000 0x00 0x163c>;
reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
};
};
};
&scm_conf {