From 57b7ba68ef579f09c402b01471a750f9e16633b7 Mon Sep 17 00:00:00 2001
From: Neha Malcom Francis <n-francis@ti.com>
Date: Thu, 22 Jan 2026 16:55:01 +0530
Subject: [PATCH] PENDING: arm64: dts: ti: k3-j784s4-main: Add DDR nodes for
 J784S4

Add DT nodes for the 4 DDR controllers on the J784S4 device. These define
the memory controller with its register regions, interrupts, power
domains, and clock requirements.

This allows for DDR controller temperature monitoring.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 84 ++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index ffc61ec77635..303e27f9e867 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -149,6 +149,90 @@
 		assigned-clocks = <&k3_clks 355 0>;
 		assigned-clock-parents = <&k3_clks 355 4>;
 	};
+
+	memorycontroller0: memory-controller@2980000 {
+		compatible = "ti,j7-ddrss";
+		reg = <0x0 0x02980000 0x0 0x200>;
+		reg-names = "ss_cfg";
+		ranges = <0x00 0x00 0x00 0x02990000 0x00 0x00004000>;
+		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
+				<&k3_pds 46 TI_SCI_PD_SHARED>;
+		clocks = <&k3_clks 191 1>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ddr0: ddr@0 {
+			compatible = "cdns,j7-ddr";
+			reg = <0x00 0x0000 0x00 0x72c>,
+				  <0x00 0x2000 0x00 0x4b0>,
+				  <0x00 0x4000 0x00 0x163c>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+		};
+	};
+
+	memorycontroller1: memory-controller@29a0000 {
+		compatible = "ti,j7-ddrss";
+		reg = <0x0 0x029a0000 0x0 0x200>;
+		reg-names = "ss_cfg";
+		ranges = <0x00 0x00 0x00 0x029b0000 0x00 0x00004000>;
+		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
+				<&k3_pds 47 TI_SCI_PD_SHARED>;
+		clocks = <&k3_clks 192 1>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ddr1: ddr@0 {
+			compatible = "cdns,j7-ddr";
+			reg = <0x00 0x0000 0x00 0x72c>,
+				  <0x00 0x2000 0x00 0x4b0>,
+				  <0x00 0x4000 0x00 0x163c>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+		};
+	};
+
+	memorycontroller2: memory-controller@29c0000 {
+		compatible = "ti,j7-ddrss";
+		reg = <0x0 0x029c0000 0x0 0x200>;
+		reg-names = "ss_cfg";
+		ranges = <0x00 0x00 0x00 0x029d0000 0x00 0x00004000>;
+		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
+				<&k3_pds 48 TI_SCI_PD_SHARED>;
+		clocks = <&k3_clks 193 1>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ddr2: ddr@0 {
+			compatible = "cdns,j7-ddr";
+			reg = <0x00 0x0000 0x00 0x72c>,
+				  <0x00 0x2000 0x00 0x4b0>,
+				  <0x00 0x4000 0x00 0x163c>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+		};
+	};
+
+	memorycontroller3: memory-controller@29e0000 {
+		compatible = "ti,j7-ddrss";
+		reg = <0x0 0x029e0000 0x0 0x200>;
+		reg-names = "ss_cfg";
+		ranges = <0x00 0x00 0x00 0x029f0000 0x00 0x00004000>;
+		interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
+				<&k3_pds 49 TI_SCI_PD_SHARED>;
+		clocks = <&k3_clks 194 1>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ddr3: ddr@0 {
+			compatible = "cdns,j7-ddr";
+			reg = <0x00 0x0000 0x00 0x72c>,
+				  <0x00 0x2000 0x00 0x4b0>,
+				  <0x00 0x4000 0x00 0x163c>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+		};
+	};
 };
 
 &scm_conf {