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mtd: spi-nor: log MTD_RAM type and physical address at probe time

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The late_init fixup in everspin.c sets mtd->priv to a map_info with
the AHB window's physical base address, but mtd->type/flags were
previously assigned redundantly in the fixup and then overwritten by
spi_nor_set_mtd_info() which always hardcodes MTD_NORFLASH.

Fix the ordering properly:

- spi_nor_set_mtd_info() in core.c now checks mtd->priv before
  assigning type/flags. If a fixup hook has already placed a
  struct map_info there, it uses MTD_RAM / MTD_CAP_RAM and emits
  a dev_info() with the physical base address:

    spi-nor: MTD type set to MTD_RAM (mmap enabled), phys base: 0x60000000

  This makes it easy to verify in the kernel log that the device
  came up correctly and which physical address to use for mmap().

- The now-redundant mtd->type / mtd->flags assignments are removed
  from everspin_mram_late_init().

- core.c gains #include <linux/mtd/map.h> for the struct map_info cast.

Signed-off-by: Heinrich Toews <ht@twx-software.de>
This commit is contained in:
Heinrich Toews
2026-04-07 16:41:11 +02:00
parent 98b840c366
commit 26cea97562
2 changed files with 24 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/mtd/spi-nor/core.c
+19 -2
View File
@@ -14,6 +14,7 @@
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/spi-nor.h>
#include <linux/mutex.h>
#include <linux/of_platform.h>
@@ -3420,8 +3421,24 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor)
mtd->dev.parent = dev;
if (!mtd->name)
mtd->name = dev_name(dev);
mtd->type = MTD_NORFLASH;
mtd->flags = MTD_CAP_NORFLASH;
/*
* If a fixup hook has already populated mtd->priv with a struct
* map_info (e.g. Everspin MRAM on Cadence OSPI DAC window), honour
* that and advertise the device as byte-addressable RAM so that
* mtdchar_mmap() can call vm_iomap_memory() for zero-copy access.
* Otherwise fall back to the standard NOR-flash type.
*/
if (mtd->priv) {
mtd->type = MTD_RAM;
mtd->flags = MTD_CAP_RAM;
dev_info(dev,
"MTD type set to MTD_RAM (mmap enabled), "
"phys base: %pa\n",
&((struct map_info *)mtd->priv)->phys);
} else {
mtd->type = MTD_NORFLASH;
mtd->flags = MTD_CAP_NORFLASH;
}
/* Unset BIT_WRITEABLE to enable JFFS2 write buffer for ECC'd NOR */
if (nor->flags & SNOR_F_ECC)
mtd->flags &= ~MTD_BIT_WRITEABLE;
drivers/mtd/spi-nor/everspin.c
+5 -10
View File
@@ -162,6 +162,7 @@ static void everspin_mram_default_init(struct spi_nor *nor)
ret = spi_nor_read_any_reg(nor, &op, SNOR_PROTO_1_1_1);
if (!ret) {
u8 sr1 = nor->bouncebuf[0];
dev_info(nor->dev, "Initial SR1: 0x%02x (BP-Bits: 0x%x)\n", sr1, (sr1 & 0x3c) >> 2);
if (sr1 & GENMASK(5, 2))
everspin_mram_unlock(nor);
@@ -198,6 +199,7 @@ static void everspin_mram_default_init(struct spi_nor *nor)
if (!ret) {
/* Access the result from the DMA-safe bounce buffer */
u8 status = nor->bouncebuf[0];
dev_info(nor->dev, "MRAM Status Register (8s-0-8s): 0x%02x\n", status);
}
@@ -373,16 +375,9 @@ static int everspin_mram_late_init(struct spi_nor *nor)
nor->priv = priv;
/*
* Advertise this device as byte-addressable RAM so that
* mtdchar_mmap() takes the vm_iomap_memory() path.
* MTD_CAP_RAM = MTD_WRITEABLE | MTD_BIT_WRITEABLE | MTD_NO_ERASE
*/
nor->mtd.type = MTD_RAM;
nor->mtd.flags = MTD_CAP_RAM;
/*
* mtdchar_mmap() casts mtd->priv to struct map_info * when
* mtd->type == MTD_RAM. Point it at our embedded map_info.
* mtd->type and mtd->flags will be set to MTD_RAM / MTD_CAP_RAM
* by spi_nor_set_mtd_info() in core.c once it sees mtd->priv != NULL.
* mtdchar_mmap() will then call vm_iomap_memory() via map->phys.
*/
nor->mtd.priv = &priv->map;