diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 58a54e1075c9..682f167eb31c 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -14,6 +14,7 @@
 #include <linux/math64.h>
 #include <linux/module.h>
 #include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
 #include <linux/mtd/spi-nor.h>
 #include <linux/mutex.h>
 #include <linux/of_platform.h>
@@ -3420,8 +3421,24 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor)
 	mtd->dev.parent = dev;
 	if (!mtd->name)
 		mtd->name = dev_name(dev);
-	mtd->type = MTD_NORFLASH;
-	mtd->flags = MTD_CAP_NORFLASH;
+	/*
+	 * If a fixup hook has already populated mtd->priv with a struct
+	 * map_info (e.g. Everspin MRAM on Cadence OSPI DAC window), honour
+	 * that and advertise the device as byte-addressable RAM so that
+	 * mtdchar_mmap() can call vm_iomap_memory() for zero-copy access.
+	 * Otherwise fall back to the standard NOR-flash type.
+	 */
+	if (mtd->priv) {
+		mtd->type  = MTD_RAM;
+		mtd->flags = MTD_CAP_RAM;
+		dev_info(dev,
+			 "MTD type set to MTD_RAM (mmap enabled), "
+			 "phys base: %pa\n",
+			 &((struct map_info *)mtd->priv)->phys);
+	} else {
+		mtd->type = MTD_NORFLASH;
+		mtd->flags = MTD_CAP_NORFLASH;
+	}
 	/* Unset BIT_WRITEABLE to enable JFFS2 write buffer for ECC'd NOR */
 	if (nor->flags & SNOR_F_ECC)
 		mtd->flags &= ~MTD_BIT_WRITEABLE;
diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c
index 7de8f6c2ba53..3edb18904945 100644
--- a/drivers/mtd/spi-nor/everspin.c
+++ b/drivers/mtd/spi-nor/everspin.c
@@ -162,6 +162,7 @@ static void everspin_mram_default_init(struct spi_nor *nor)
 	ret = spi_nor_read_any_reg(nor, &op, SNOR_PROTO_1_1_1);
 	if (!ret) {
 		u8 sr1 = nor->bouncebuf[0];
+
 		dev_info(nor->dev, "Initial SR1: 0x%02x (BP-Bits: 0x%x)\n", sr1, (sr1 & 0x3c) >> 2);
 		if (sr1 & GENMASK(5, 2))
 			everspin_mram_unlock(nor);
@@ -198,6 +199,7 @@ static void everspin_mram_default_init(struct spi_nor *nor)
 	if (!ret) {
 		/* Access the result from the DMA-safe bounce buffer */
 		u8 status = nor->bouncebuf[0];
+
 		dev_info(nor->dev, "MRAM Status Register (8s-0-8s): 0x%02x\n", status);
 	}
 
@@ -373,16 +375,9 @@ static int everspin_mram_late_init(struct spi_nor *nor)
 	nor->priv	= priv;
 
 	/*
-	 * Advertise this device as byte-addressable RAM so that
-	 * mtdchar_mmap() takes the vm_iomap_memory() path.
-	 * MTD_CAP_RAM = MTD_WRITEABLE | MTD_BIT_WRITEABLE | MTD_NO_ERASE
-	 */
-	nor->mtd.type	= MTD_RAM;
-	nor->mtd.flags	= MTD_CAP_RAM;
-
-	/*
-	 * mtdchar_mmap() casts mtd->priv to struct map_info * when
-	 * mtd->type == MTD_RAM.  Point it at our embedded map_info.
+	 * mtd->type and mtd->flags will be set to MTD_RAM / MTD_CAP_RAM
+	 * by spi_nor_set_mtd_info() in core.c once it sees mtd->priv != NULL.
+	 * mtdchar_mmap() will then call vm_iomap_memory() via map->phys.
 	 */
 	nor->mtd.priv	= &priv->map;