This patch enables high-speed Octal-STR (8s-8s-8s) operation at 200MHz
for the Everspin EM008LX MRAM series.
To maintain reliable boot-up, the device is identified at a safe
frequency. Upon successful JEDEC ID verification, the driver escalates
the clock frequency to 200MHz and synchronizes the dummy cycles.
Key Improvements:
- Added frequency escalation in params->setup() hook to 200MHz.
- Implemented Octal register access (0x85/0x81) for configuration.
- Synchronized dummy cycles to 20, as required for 200MHz operation.
- Validated with Cadence OSPI controller using a 400MHz reference clock
and a read-capture delay of 3-5 cycles.
The resulting configuration achieves the maximum specified throughput
of the Everspin MRAM while maintaining data integrity.
Signed-off-by: Heinrich Toews <ht@twx-software.de>
Heinrich Toews
f3d8580745