dirty

Signed-off-by: Heinrich Toews <ht@twx-software.de>

Documentation/devicetree/bindings/leds/worldsemi,ws2812b.yaml

@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/worldsemi,ws2812b.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: WS2812B LEDs driven using SPI
+
+maintainers:
+  - Chuanhong Guo <gch981213@gmail.com>
+
+description: |
+  WorldSemi WS2812B is a individually addressable LED chip that can be chained
+  together and controlled individually using a single wire.
+  This binding describes a chain of WS2812B LEDs connected to the SPI MOSI pin.
+  Typical setups includes connecting the data pin of the LED chain to MOSI as
+  the only device or using CS and MOSI with a tri-state voltage-level shifter
+  for the data pin.
+  The SPI frequency needs to be 2.105MHz~2.85MHz for the timing to be correct
+  and the controller needs to send all the bytes continuously.
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+  compatible:
+    const: worldsemi,ws2812b
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency:
+    minimum: 2105000
+    maximum: 2850000
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "^multi-led@[0-9a-f]+$":
+    type: object
+    $ref: leds-class-multicolor.yaml#
+    unevaluatedProperties: false
+
+    properties:
+      color-index:
+        description: |
+          A 3-item array specifying color of each components in this LED. It
+          should be one of the LED_COLOR_ID_* prefixed definitions from the
+          header include/dt-bindings/leds/common.h. Defaults to
+          <LED_COLOR_ID_GREEN LED_COLOR_ID_RED LED_COLOR_ID_BLUE>
+          if unspecified.
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        maxItems: 3
+
+      reg:
+        description: |
+          Which LED this node represents. The reg of the first LED on the chain
+          is 0.
+        maxItems: 1
+
+    required:
+      - reg
+      - color
+      - function
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/leds/common.h>
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        led-controller@0 {
+            compatible = "worldsemi,ws2812b";
+            reg = <0>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            spi-max-frequency = <2850000>;
+            multi-led@0 {
+                reg = <0>;
+                color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
+                color = <LED_COLOR_ID_RGB>;
+                function = LED_FUNCTION_STATUS;
+                function-enumerator = <0>;
+            };
+            multi-led@1 {
+                reg = <1>;
+                color = <LED_COLOR_ID_RGB>;
+                function = LED_FUNCTION_STATUS;
+                function-enumerator = <1>;
+            };
+            multi-led@2 {
+                reg = <2>;
+                color = <LED_COLOR_ID_RGB>;
+                function = LED_FUNCTION_STATUS;
+                function-enumerator = <2>;
+            };
+            multi-led@3 {
+                reg = <3>;
+                color = <LED_COLOR_ID_RGB>;
+                function = LED_FUNCTION_STATUS;
+                function-enumerator = <3>;
+            };
+        };
+    };
+
+...

Documentation/devicetree/bindings/remoteproc/ti,k3-m4f-rproc.yaml

@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/ti,k3-m4f-rproc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI K3 M4F processor subsystems
+
+maintainers:
+  - Hari Nagalla <hnagalla@ti.com>
+  - Mathieu Poirier <mathieu.poirier@linaro.org>
+
+description: |
+  Some K3 family SoCs have Arm Cortex M4F cores. AM64x is a SoC in K3
+  family with a M4F core. Typically safety oriented applications may use
+  the M4F core in isolation without an IPC. Where as some industrial and
+  home automation applications, may use the M4F core as a remote processor
+  with IPC communications.
+
+$ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
+
+properties:
+  compatible:
+    enum:
+      - ti,am64-m4fss
+
+  power-domains:
+    maxItems: 1
+
+  "#address-cells":
+    const: 2
+
+  "#size-cells":
+    const: 2
+
+  reg:
+    items:
+      - description: IRAM internal memory region
+      - description: DRAM internal memory region
+
+  reg-names:
+    items:
+      - const: iram
+      - const: dram
+
+  resets:
+    maxItems: 1
+
+  firmware-name:
+    maxItems: 1
+    description: Name of firmware to load for the M4F core
+
+  mboxes:
+    description:
+      OMAP Mailbox specifier denoting the sub-mailbox, to be used for
+      communication with the remote processor. This property should match
+      with the sub-mailbox node used in the firmware image.
+    maxItems: 1
+
+  memory-region:
+    description:
+      phandle to the reserved memory nodes to be associated with the
+      remoteproc device. Optional memory regions available for firmware
+      specific purposes.
+      (see reserved-memory/reserved-memory.yaml in dtschema project)
+    maxItems: 8
+    items:
+      - description: regions used for DMA allocations like vrings, vring buffers
+                     and memory dedicated to firmware's specific purposes.
+    additionalItems: true
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - ti,sci
+  - ti,sci-dev-id
+  - ti,sci-proc-ids
+  - resets
+  - firmware-name
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    reserved-memory {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 {
+            compatible = "shared-dma-pool";
+            reg = <0x00 0x9cb00000 0x00 0x100000>;
+            no-map;
+        };
+
+        mcu_m4fss_memory_region: m4f-memory@9cc00000 {
+            compatible = "shared-dma-pool";
+            reg = <0x00 0x9cc00000 0x00 0xe00000>;
+            no-map;
+        };
+    };
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        mailbox0_cluster0: mailbox-0 {
+            #mbox-cells = <1>;
+        };
+
+        remoteproc@5000000 {
+            compatible = "ti,am64-m4fss";
+            reg = <0x00 0x5000000 0x00 0x30000>,
+                  <0x00 0x5040000 0x00 0x10000>;
+            reg-names = "iram", "dram";
+            resets = <&k3_reset 9 1>;
+            firmware-name = "am62-mcu-m4f0_0-fw";
+            mboxes = <&mailbox0_cluster0>, <&mbox_m4_0>;
+            memory-region = <&mcu_m4fss_dma_memory_region>,
+                            <&mcu_m4fss_memory_region>;
+            ti,sci = <&dmsc>;
+            ti,sci-dev-id = <9>;
+            ti,sci-proc-ids = <0x18 0xff>;
+         };
+    };

Documentation/devicetree/bindings/vendor-prefixes.yaml

@@ -1538,6 +1538,8 @@ patternProperties:
     description: Wondermedia Technologies, Inc.
   "^wobo,.*":
     description: Wobo
+  "^worldsemi,.*":
+    description: WorldSemi Co., Limited
   "^x-powers,.*":
     description: X-Powers
   "^xen,.*":

arch/arm64/boot/dts/ti/Makefile

@@ -24,7 +24,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-hdmi-audio.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-hdmi-audio.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am623-pfc-750-8302.dtb
-dtb-$(CONFIG_ARCH_K3) += k3-am623-pfc-ems.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am623-pfc-750-830x-ems.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am623-pfc-750-8400.dtb
 
 # Boards with AM62Ax SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb

arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi

@@ -171,4 +171,17 @@
 		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 		status = "disabled";
 	};
+
+	mcu_m4fss: m4fss@5000000 {
+		compatible = "ti,am64-m4fss";
+		reg = <0x00 0x5000000 0x00 0x30000>,
+		      <0x00 0x5040000 0x00 0x10000>;
+		reg-names = "iram", "dram";
+		resets = <&k3_reset 9 1>;
+		firmware-name = "am62-mcu-m4f0_0-fw";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <9>;
+		ti,sci-proc-ids = <0x18 0xff>;
+		status = "disabled";
+	};
 };

arch/arm64/boot/dts/ti/k3-am623-pfc-750-8302.dts

@@ -6,12 +6,22 @@
  * Copyright (C) 2024 WAGO GmbH & Co. KG - https://www.wago.com/
  */
 
-#include "k3-am62x-pfc.dtsi"
+#include "k3-am623-pfc-750-8xxx-common.dtsi"
+#include "k3-am623-pfc-750-830x-common.dtsi"
+#include "k3-am623-pfc-kbus.dtsi"
+#include "k3-am623-pfc-rs485.dtsi"
+#include "k3-am623-pfc-tpm.dtsi"
+#include "k3-am623-pfc-rtc.dtsi"
 
 / {
 	model = "WAGO PFC300 750-8302";
 	compatible = "ti,am623-pfc", "ti,am625";
 
+	aliases {
+		ethernet0 = &cpsw_port1;
+		ethernet1 = &cpsw_port2;
+	};
+
         cpus {
                 cpu-map {
                         cluster0 {
@@ -31,10 +41,197 @@
                 /delete-node/ cpu@2;
                 /delete-node/ cpu@3;
         };
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 2G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+	};
+
+	/* this name of the gpio-keys device is a
+	 * historical heritage from 3.6.11 kernel.
+	 * the device-name is checked in omsd. So we
+	 * need to adapt this configuration
+	 */
+	oms: PAC-Operating-Mode-Switch {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&oms_pins_default>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		oms_run: run {
+			label = "RUN";
+			gpios = <&main_gpio0 65 GPIO_ACTIVE_LOW>;
+			linux,code = <1>;
+			linux,input-type = <5>;
+			debounce-interval = <1>;
+		};
+
+		oms_stop: stop {
+			label = "STOP";
+			gpios = <&main_gpio1 10 GPIO_ACTIVE_LOW>;
+			linux,code = <2>;
+			linux,input-type = <5>;
+			debounce-interval = <1>;
+		};
+
+		oms_reset: reset {
+			label = "RESET";
+			gpios = <&main_gpio1 12 GPIO_ACTIVE_LOW>;
+			linux,code = <3>;
+			linux,input-type = <1>;
+			debounce-interval = <1>;
+		};
+
+		oms_reset_all: reset_all {
+			label = "RESET_ALL";
+			gpios = <&main_gpio1 11 GPIO_ACTIVE_HIGH>;
+			linux,code = <4>;
+			linux,input-type = <1>;
+			debounce-interval = <1>;
+		};
+	};
+
+	uio_nvram: nvram@51000000 {
+		compatible = "uio_pdrv_genirq";
+		linux,uio-name = "UIO_NVRAM";
+		reg = <0 0x51000000 0 0x00020000>; /* 128k 16bit NVRAM */
+	};
+
+	vdd_mmc1: regulator-3 {
+		compatible = "regulator-fixed";
+	 	pinctrl-names = "default";
+	 	pinctrl-0 = <&vdd_sd_dv_pins_default>;
+		regulator-name = "vdd_mmc1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		vin-supply = <&vcc_3v3_sys>;
+		gpio = <&main_gpio0 31 GPIO_ACTIVE_LOW>;
+		enable-active-high;
+		startup-delay-us = <5000>;
+	};
+};
+
+&mcu_pmx0 {
+	gpmc_data_pins_default: gpmc-data-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x00bc, PIN_OUTPUT, 1) /* (V24) VOUT0_DATA1.GPMC0_A1    */
+			AM62X_IOPAD(0x00c0, PIN_OUTPUT, 1) /* (W25) VOUT0_DATA2.GPMC0_A2    */
+			AM62X_IOPAD(0x00c4, PIN_OUTPUT, 1) /* (W24) VOUT0_DATA3.GPMC0_A3    */
+			AM62X_IOPAD(0x00c8, PIN_OUTPUT, 1) /* (Y25) VOUT0_DATA4.GPMC0_A4    */
+			AM62X_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (Y24) VOUT0_DATA5.GPMC0_A5    */
+			AM62X_IOPAD(0x00d0, PIN_OUTPUT, 1) /* (Y23) VOUT0_DATA6.GPMC0_A6    */
+			AM62X_IOPAD(0x00d4, PIN_OUTPUT, 1) /* (AA25) VOUT0_DATA7.GPMC0_A7   */
+			AM62X_IOPAD(0x00d8, PIN_OUTPUT, 1) /* (V21) VOUT0_DATA8.GPMC0_A8    */
+			AM62X_IOPAD(0x00dc, PIN_OUTPUT, 1) /* (W21) VOUT0_DATA9.GPMC0_A9    */
+			AM62X_IOPAD(0x00e0, PIN_OUTPUT, 1) /* (V20) VOUT0_DATA10.GPMC0_A10  */
+			AM62X_IOPAD(0x00e4, PIN_OUTPUT, 1) /* (AA23) VOUT0_DATA11.GPMC0_A11 */
+			AM62X_IOPAD(0x00e8, PIN_OUTPUT, 1) /* (AB25) VOUT0_DATA12.GPMC0_A12 */
+			AM62X_IOPAD(0x00ec, PIN_OUTPUT, 1) /* (AA24) VOUT0_DATA13.GPMC0_A13 */
+			AM62X_IOPAD(0x00f0, PIN_OUTPUT, 1) /* (Y22) VOUT0_DATA14.GPMC0_A14  */
+			AM62X_IOPAD(0x00f4, PIN_OUTPUT, 1) /* (AA21) VOUT0_DATA15.GPMC0_A15 */
+			AM62X_IOPAD(0x00f8, PIN_OUTPUT, 1) /* (AB24) VOUT0_HSYNC.GPMC0_A16  */
+		>;
+	};
+
+	gpmc_addr_pins_default: gpmc-addr-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (M25) GPMC0_AD0  */
+			AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (N23) GPMC0_AD1  */
+			AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (N24) GPMC0_AD2  */
+			AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (N25) GPMC0_AD3  */
+			AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (P24) GPMC0_AD4  */
+			AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (P22) GPMC0_AD5  */
+			AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (P21) GPMC0_AD6  */
+			AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (R23) GPMC0_AD7  */
+			AM62X_IOPAD(0x005c, PIN_INPUT, 0) /* (R24) GPMC0_AD8  */
+			AM62X_IOPAD(0x0060, PIN_INPUT, 0) /* (R25) GPMC0_AD9  */
+			AM62X_IOPAD(0x0064, PIN_INPUT, 0) /* (T25) GPMC0_AD10 */
+			AM62X_IOPAD(0x0068, PIN_INPUT, 0) /* (R21) GPMC0_AD11 */
+			AM62X_IOPAD(0x006c, PIN_INPUT, 0) /* (T22) GPMC0_AD12 */
+			AM62X_IOPAD(0x0070, PIN_INPUT, 0) /* (T24) GPMC0_AD13 */
+			AM62X_IOPAD(0x0074, PIN_INPUT, 0) /* (U25) GPMC0_AD14 */
+			AM62X_IOPAD(0x0078, PIN_INPUT, 0) /* (U24) GPMC0_AD15 */
+		>;
+	};
+
+	gpmc_ctrl_pins_default: gpmc-ctrl-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0094, PIN_OUTPUT, 0) /* (N20) GPMC0_BE1n     */
+			AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (M21) GPMC0_CSn0     */
+			AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (L24) GPMC0_OEn_REn  */
+			AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L25) GPMC0_WEn      */
+			AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (M24) GPMC0_BE0n_CLE */
+		>;
+	};
+
+	main_mdio1_pins_default: main-mdio1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x160,  PIN_OUTPUT,       0) /* (AD24) MDIO0_MDC */
+			AM62X_IOPAD(0x15c,  PIN_INPUT_PULLUP, 0) /* (AB22) MDIO0_MDIO */
+			AM62X_IOPAD(0x019c, PIN_OUTPUT,       7) /* (B18) MCASP0_AXR1.GPIO1_9 */
+		>;
+	};
+
+	main_rgmii1_pins_default: main-rgmii1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x14c, PIN_INPUT,  0) /* (AB17) RGMII1_RD0 */
+			AM62X_IOPAD(0x150, PIN_INPUT,  0) /* (AC17) RGMII1_RD1 */
+			AM62X_IOPAD(0x154, PIN_INPUT,  0) /* (AB16) RGMII1_RD2 */
+			AM62X_IOPAD(0x158, PIN_INPUT,  0) /* (AA15) RGMII1_RD3 */
+			AM62X_IOPAD(0x148, PIN_INPUT,  0) /* (AD17) RGMII1_RXC */
+			AM62X_IOPAD(0x144, PIN_INPUT,  0) /* (AE17) RGMII1_RX_CTL */
+			AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
+			AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
+			AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
+			AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
+			AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
+			AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
+			AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 nINT-RGMII1 */
+		>;
+	};
+
+	main_rgmii2_pins_default: main-rgmii2-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x184, PIN_INPUT,  0) /* (AE23) RGMII2_RD0 */
+			AM62X_IOPAD(0x188, PIN_INPUT,  0) /* (AB20) RGMII2_RD1 */
+			AM62X_IOPAD(0x18c, PIN_INPUT,  0) /* (AC21) RGMII2_RD2 */
+			AM62X_IOPAD(0x190, PIN_INPUT,  0) /* (AE22) RGMII2_RD3 */
+			AM62X_IOPAD(0x180, PIN_INPUT,  0) /* (AD23) RGMII2_RXC */
+			AM62X_IOPAD(0x17c, PIN_INPUT,  0) /* (AD22) RGMII2_RX_CTL */
+			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
+			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
+			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
+			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
+			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
+			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
+			AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */
+		>;
+	};
+
+	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
+		>;
+	};
+
+	oms_pins_default: oms-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0108, PIN_INPUT, 7) /* (D24) MMC2_DAT3.GPIO0_65 */
+			AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
+			AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */
+			AM62X_IOPAD(0x01a4, PIN_INPUT, 7) /* (B20) MCASP0_ACLKX.GPIO1_11 */
+		>;
+	};
 };
 
 &wsysinit {
 	status = "okay";
+        board,variant = "pfc300";
 };
 
 &oms {
@@ -51,6 +248,42 @@
 
 &gpmc0 {
 	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpmc_data_pins_default>, <&gpmc_addr_pins_default>, <&gpmc_ctrl_pins_default>;
+
+	num-cs = <4>;
+	num-waitpins = <4>;
+	ranges = <
+		0 0 0x00 0x51000000 0x01000000	/* CS0: NVRAM, 16M */
+	>;
+
+	nvram: nor@0,0 { /* NVRAM Device 128k */
+		reg = <0 0 0x01000000>;
+		bank-width = <2>; /* 1: 8bit, 2: 16bit */
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <50>;
+		gpmc,cs-wr-off-ns = <30>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <0>;
+		gpmc,adv-wr-off-ns = <0>;
+		gpmc,oe-on-ns = <0>;
+		gpmc,oe-off-ns = <50>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <30>;
+		gpmc,rd-cycle-ns = <50>;
+		gpmc,wr-cycle-ns = <30>;
+		gpmc,access-ns = <40>;
+		gpmc,wr-access-ns = <10>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <10>;
+		gpmc,cycle2cycle-samecsen;
+		gpmc,cycle2cycle-diffcsen;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
 };
 
 &main_uart0 {
@@ -87,22 +320,56 @@
 
 &sdhci1 { /* SD */
 	status = "okay";
+
+	vmmc-supply = <&vdd_mmc1>;
+
+	cap-sd-highspeed;
+	no-1-8-v;
 };
 
 &cpsw3g {
 	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mdio1_pins_default
+		     &main_rgmii1_pins_default
+		     &main_rgmii2_pins_default>;
 };
 
 &cpsw_port1 {
 	status = "okay";
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&cpsw3g_phy0>;
 };
 
 &cpsw_port2 {
 	status = "okay";
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&cpsw3g_phy1>;
 };
 
 &cpsw3g_mdio {
 	status = "okay";
+
+        reset-gpios = <&main_gpio1 9 GPIO_ACTIVE_LOW>;
+        reset-delay-us = <10>;
+        reset-post-delay-us = <10000>;
+
+	cpsw3g_phy0: ethernet-phy@0 {
+		// ADIN1300
+		compatible = "ethernet-phy-id0283.bc30";
+
+		reg = <0>;
+		adi,rx-internal-delay-ps = <2000>;
+	};
+
+	cpsw3g_phy1: ethernet-phy@1 {
+		// ADIN1300
+		compatible = "ethernet-phy-id0283.bc30";
+
+		reg = <1>;
+		adi,rx-internal-delay-ps = <2000>;
+	};
 };
 
 &usbss0 {

arch/arm64/boot/dts/ti/k3-am623-pfc-750-830x-common.dtsi

@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+
+&main_i2c0 {
+
+        #include "k3-am623-pfc-750-830x-leds.dtsi"
+
+	tps65219_30: pmic@30 {
+		compatible = "ti,tps65219";
+		reg = <0x30>;
+		system-power-controller;
+
+		buck1-supply = <&vcc_5v0>;
+		buck2-supply = <&vcc_5v0>;
+		buck3-supply = <&vcc_5v0>;
+		ldo1-supply = <&vcc_3v3_sys>;
+		ldo2-supply = <&vcc_3v3_sys>;
+		ldo3-supply = <&vcc_5v0>;
+		ldo4-supply = <&vcc_5v0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_irq_pins_default>;
+
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <68 IRQ_TYPE_EDGE_FALLING>;
+
+		regulators {
+			buck1_30_reg: buck1 {
+				regulator-name = "VDD_CORE";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck2_30_reg: buck2 {
+				regulator-name = "VCC1V8_SYS";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck3_30_reg: buck3 {
+				regulator-name = "VCC3V3_SYS";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_30_reg: ldo1 {
+				regulator-name = "VCC3V3_SDC";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo2_30_reg: ldo2 {
+				regulator-name = "VDDA_1V8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+

arch/arm64/boot/dts/ti/k3-am623-pfc-750-830x-ems.dts

@@ -6,7 +6,8 @@
  * Copyright (C) 2024 WAGO GmbH & Co. KG - https://www.wago.com/
  */
 
-#include "k3-am62x-pfc.dtsi"
+#include "k3-am623-pfc-750-8xxx-common.dtsi"
+#include "k3-am623-pfc-750-830x-common.dtsi"
 
 / {
 	model = "WAGO AM623 PFC EMS";
@@ -460,14 +461,6 @@
 	status = "okay";
 };
 
-&oms {
-	status = "disabled";
-};
-
-&nvram {
-	status = "okay";
-};
-
 &watchdog_ext {
 	status = "okay";
 };
@@ -509,9 +502,6 @@
 	status = "disabled";
 };
 
-/delete-node/ &vdd_mmc1;
-/delete-node/ &vdd_sd_dv_pins_default;
-
 &cpsw3g {
 	status = "disabled";
 };

arch/arm64/boot/dts/ti/k3-am623-pfc-750-830x-leds.dtsi

@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+
+led_bar60: pca9552@60 {
+        compatible = "nxp,pca9552";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        reg = <0x60>;
+
+        lb60_0: sys-red@0 {
+                label = "sys-red";
+                reg = <0>;
+                linux,default-trigger = "timer";
+        };
+
+        lb60_1: sys-green@1 {
+                label = "sys-green";
+                reg = <1>;
+                linux,default-trigger = "timer";
+        };
+
+        lb60_2: run-red@2 {
+                label = "run-red";
+                reg = <2>;
+        };
+
+        lb60_3: run-green@3 {
+                label = "run-green";
+                reg = <3>;
+        };
+
+        lb60_4: io-red@4 {
+                label = "io-red";
+                reg = <4>;
+        };
+
+        lb60_5: io-green@5 {
+                label = "io-green";
+                reg = <5>;
+        };
+
+        lb60_6: ms-red@6 {
+                label = "ms-red";
+                reg = <6>;
+        };
+
+        lb60_7: ms-green@7 {
+                label = "ms-green";
+                reg = <7>;
+        };
+
+        lb60_8: ns-red@8 {
+                label = "ns-red";
+                reg = <8>;
+        };
+
+        lb60_9: ns-green@9 {
+                label = "ns-green";
+                reg = <9>;
+        };
+
+        lb60_10: usr_r@10 {
+                label = "trm-red";
+                reg = <10>;
+        };
+
+        lb60_11: usr_g@11 {
+                label = "trm-green";
+                reg = <11>;
+        };
+
+        lb60_15: sys-over-red@15 {
+                label = "sys-over-red";
+                reg = <15>;
+                linux,default-trigger = "default-on";
+        };
+};
+
+led_bar61: pca9552@61 {
+        compatible = "nxp,pca9552";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        reg = <0x61>;
+
+        lb61_0: u6-red@0 {
+                label = "u6-red";
+                reg = <0>;
+        };
+
+        lb61_1: u6-green@1 {
+                label = "u6-green";
+                reg = <1>;
+        };
+
+        lb61_2: u5-red@2 {
+                label = "u5-red";
+                reg = <2>;
+        };
+
+        lb61_3: u5-green@3 {
+                label = "u5-green";
+                reg = <3>;
+        };
+
+        lb61_4: u4-red@4 {
+                label = "u4-red";
+                reg = <4>;
+        };
+
+        lb61_5: u4-green@5 {
+                label = "u4-green";
+                reg = <5>;
+        };
+
+        lb61_6: u3-red@6 {
+                label = "u3-red";
+                reg = <6>;
+        };
+
+        lb61_7: u3-green@7 {
+                label = "u3-green";
+                reg = <7>;
+        };
+
+        lb61_8: u2-red@8 {
+                label = "u2-red";
+                reg = <8>;
+        };
+
+        lb61_9: u2-green@9 {
+                label = "u2-green";
+                reg = <9>;
+        };
+
+        lb61_10: u1-red@10 {
+                label = "u1-red";
+                reg = <10>;
+        };
+
+        lb61_11: u1-green@11 {
+                label = "u1-green";
+                reg = <11>;
+        };
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-750-8400.dts

@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PFC400 - AM62x based WAGO device
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+#include "k3-am623-pfc-750-84xx-wosm.dtsi"
+#include "k3-am623-pfc-750-84xx-baseboard.dtsi"
+#include "k3-am623-pfc-750-84xx-kbus.dtsi"
+#include "k3-am623-pfc-750-84xx-interaction.dtsi"
+
+&wsysinit {
+	status = "okay";
+        board,variant = "pfc400";
+};
+
+&mcu_pmx0 {
+	mcu_gpio0_pins: mcu-gpio-test-pin {
+		pinctrl-single,pins = <
+			AM64X_MCU_IOPAD(0x001C, PIN_OUTPUT, 7)   /* (A6) nRST-EM3 -> nRST-EM2 0x0408401C MCU_UART0_CTSn.MCU_GPIO0_7  (PIN twisted) */
+			AM64X_MCU_IOPAD(0x0020, PIN_OUTPUT, 7)   /* (B6) nRST-EM2 -> nRST-EM3 0x04084020 MCU_UART0_RTSn.MCU_GPIO0_8  (PIN twisted) */
+			AM64X_MCU_IOPAD(0x003C, PIN_OUTPUT, 7)   /* (E5) nRST-EM1             0x0408403C   MCU_MCAN1_TX.MCU_GPIO0_15 */
+		>;
+	};
+};
+
+&mcu_gpio0 {
+	pinctrl-0 = <&mcu_gpio0_pins>;
+	pinctrl-names = "default";
+	status = "reserved";
+	/* status = "okay"; */
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-baseboard.dtsi

@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+* PFC400 baseboard dtsi for AM62x based WAGO devices
+*
+* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+* Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+*/
+
+&leds_gpio {
+	led-1 {
+		label = "pfc400:nrst-em2";
+		gpios = <&mcu_gpio0 7 GPIO_ACTIVE_HIGH>;
+		default-state = "on";
+	};
+
+	led-2 {
+		label = "pfc400:nrst-em3";
+		gpios = <&mcu_gpio0 8 GPIO_ACTIVE_HIGH>;
+		default-state = "on";
+	};
+
+	led-3 {
+		label = "pfc400:nrst-em1";
+		gpios = <&mcu_gpio0 15 GPIO_ACTIVE_HIGH>;
+		linux,default-trigger = "heartbeat";
+		function = LED_FUNCTION_HEARTBEAT;
+		default-state = "on";
+	};
+};
+
+&main_pmx0 {
+        main_ksz9477_pins: main-ksz9477-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01a0, PIN_OUTPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10  nRST-RGMII2 / nRST-ETHSW (BB) */
+			AM62X_IOPAD(0x0034, PIN_INPUT, 7)  /* (H21) OSPI0_CSn2.GPIO0_13 nINT-RGMII2 / nINT-ETHSW(BB) */
+		>;
+        };
+};
+
+&mcu_spi0 {
+	ksz9477@0 {
+		compatible = "microchip,ksz9477";
+                pinctrl-names = "default";
+                pinctrl-0 = <&main_ksz9477_pins>;
+		reg = <0>;
+		spi-max-frequency = <1000000>;
+
+                reset-gpios = <&main_gpio1 10 GPIO_ACTIVE_LOW>;
+
+		dsa,member = <0 0>;
+
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "ethX3";
+				phy-mode = "internal";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "ethX2";
+				phy-mode = "internal";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "ethX1";
+				phy-mode = "internal";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "ethEM";
+				phy-mode = "internal";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "ethX4";
+				phy-mode = "internal";
+			};
+
+			port@5 {
+                                reg = <5>;
+                                label = "cpu";
+                                ethernet = <&cpsw3g>; /* &eth0 */
+                                phy-mode = "rgmii-txid";
+				tx-internal-delay-ps = <2000>;
+
+                                fixed-link {
+                                    speed = <1000>;
+                                    full-duplex;
+                                };
+                        };
+                };
+        };
+};
+
+&main_i2c1 {
+	eeprom_hw_id_bb: at24c02@54 {
+		status = "disabled";
+		compatible = "atmel,24c02";
+		reg = <0x51>;
+		pagesize = <16>;
+	};
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-interaction.dtsi

@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PFC400 interaction board dtsi for AM62x based WAGO devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+#include "k3-am623-pfc-rs485.dtsi"
+#include "k3-am623-pfc-rtc.dtsi"
+#include "k3-am623-pfc-wled.dtsi"
+
+&mcu_pmx0 {
+	led_reset_pins_default: led-reset-pins-default {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x050, PIN_OUTPUT | INPUT_EN, 7)   /* (A9)  WKUP_I2C0_SDA.GPIO0_20 nRST-LED-DISP */
+		>;
+	};
+};
+
+&main_i2c1 {
+	status = "okay";
+
+	eeprom_hw_id_ib: at24c02@54 {
+		status = "disabled";
+		compatible = "atmel,24c02";
+		reg = <0x54>;
+		pagesize = <16>;
+	};
+
+        /*
+         * NXP PCA9552BS
+         * 16-Bit I²C-Bus LED Driver
+         */
+        led_bar60: pca9552@60 {
+                compatible = "nxp,pca9552";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_reset_pins_default>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x60>;
+
+                lb60_0: sys-red@0 {
+                        label = "sys-red";
+                        reg = <0>;
+                        linux,default-trigger = "timer";
+                };
+
+                lb60_1: sys-green@1 {
+                        label = "sys-green";
+                        reg = <1>;
+                        linux,default-trigger = "timer";
+                };
+
+                lb60_2: sys-blue@2 {
+                        label = "sys-blue";
+                        reg = <2>;
+                };
+
+                lb60_3: run-red@3 {
+                        label = "run-red";
+                        reg = <3>;
+                };
+
+                lb60_4: run-green@4 {
+                        label = "run-green";
+                        reg = <4>;
+                };
+
+                lb60_5: run-blue@5 {
+                        label = "run-blue";
+                        reg = <5>;
+                };
+
+                lb60_6: io-red@6 {
+                        label = "io-red";
+                        reg = <6>;
+                };
+
+                lb60_7: io-green@7 {
+                        label = "io-green";
+                        reg = <7>;
+                };
+
+                lb60_8: io-blue@8 {
+                        label = "io-blue";
+                        reg = <8>;
+                };
+
+                lb60_9: ms-red@9 {
+                        label = "ms-red";
+                        reg = <9>;
+                };
+
+                lb60_10: ms-green@10 {
+                        label = "ms-green";
+                        reg = <10>;
+                };
+
+                lb60_11: ms-blue@11 {
+                        label = "ms-blue";
+                        reg = <11>;
+                };
+
+                lb60_12: usr_r@12 {
+                        label = "trm-red";
+                        reg = <12>;
+                };
+
+                lb60_13: usr_g@13 {
+                        label = "trm-green";
+                        reg = <13>;
+                };
+
+                lb60_14: usr_b@14 {
+                        label = "trm-blue";
+                        reg = <14>;
+                };
+
+                lb60_15: sys-over-red@15 {
+                        label = "sys-over-red";
+                        reg = <15>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+
+        /*
+         * Dynamic NFC/RFID tag IC with 4-Kbit EEPROM
+         *
+         * This driver is not yet upstream but there is a kernel driver available at:
+         * 
+         *      https://github.com/2pecshy/eeprom-ST25DV-linux-driver/tree/master
+         *
+         */
+        st25dv04k: st25dv04k@53 {
+                status = "okay";
+                compatible = "st25dv,st25dv04k";
+                reg = <0x53>;
+        };
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-kbus.dtsi

@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common dtsi for AM62x WAGO based devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+#include "k3-am623-pfc-kbus.dtsi"
+
+/ {
+	/* this name of the gpio-keys device is a
+	 * historical heritage from 3.6.11 kernel.
+	 * the device-name is checked in omsd. So we
+	 * need to adapt this configuration
+	 */
+	oms: PAC-Operating-Mode-Switch {
+		status = "okay";
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&oms_pins_default>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		oms_stop_run: stop_run {
+			label = "RUN";
+			gpios = <&main_gpio0 65 GPIO_ACTIVE_LOW>;
+			linux,code = <1>;
+			linux,input-type = <5>;
+			debounce-interval = <1>;
+		};
+
+		oms_reset_all: reset_all {
+			label = "RESET_ALL";
+			gpios = <&main_gpio1 11 GPIO_ACTIVE_HIGH>;
+			linux,code = <4>;
+			linux,input-type = <1>;
+			debounce-interval = <1>;
+		};
+	};
+};
+
+&leds_gpio {
+	led-0 {
+		pinctrl-0 = <&sd_activity_led_pin>;
+		pinctrl-names = "default";
+		label = "pfc400:sd:mmc0";
+		function = LED_FUNCTION_SD;
+		color = <LED_COLOR_ID_ORANGE>;
+		gpios = <&main_gpio0 31 GPIO_ACTIVE_LOW>;
+		linux,default-trigger = "mmc0";
+		default-state = "on";
+	};
+};
+
+&main_pmx0 {
+	oms_pins_default: oms-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0108, PIN_INPUT, 7) /* (D24) MMC2_DAT3.GPIO0_65     nSTOP-RUN */
+			AM62X_IOPAD(0x01a4, PIN_INPUT, 7) /* (B20) MCASP0_ACLKX.GPIO1_11  IO-RAB    */
+		>;
+	};
+
+	sd_activity_led_pin: sd-activity-led-pin {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 (MMC1.PWR / SDC.LED) */
+		>;
+	};
+};
+
+&main_i2c1 {
+	eeprom_hw_id_kbus: at24c02@50 {
+		status = "disabled";
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-wosm.dtsi

@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PFC400 WOSM dtsi for AM62x based WAGO devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+#include "k3-am623-pfc-750-8xxx-common.dtsi"
+#include "k3-am623-pfc-tpm.dtsi"
+
+/ {
+	model = "WAGO PFC400 750-8400";
+	compatible = "ti,am623-pfc", "ti,am625";
+
+	aliases {
+		usb1 = &usb1;
+		ethernet0 = &cpsw_port2;
+	};
+
+        cpus {
+                cpu@0 {
+                        cpu-supply = <&buck1_30_reg>;
+                };
+
+                cpu@1 {
+                        cpu-supply = <&buck1_30_reg>;
+                };
+
+                cpu@2 {
+                        cpu-supply = <&buck1_30_reg>;
+                };
+
+                cpu@3 {
+                        cpu-supply = <&buck1_30_reg>;
+                };
+        };
+
+	memory@80000000 {
+		device_type = "memory";
+
+		/* 4 GiB RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+		      <0x00000008 0x80000000 0x00000000 0x80000000>;
+	};
+
+	vcc_1v8_sys: regulator-4 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8_sys";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vmain_pd>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	leds_gpio: leds {
+		compatible = "gpio-leds";
+	};
+};
+
+&fss {
+	uio_mram: uio@500000000 {
+		compatible = "uio_pdrv_genirq";
+		linux,uio-name = "UIO_OSPI_MRAM";
+
+		/*
+		 * FSS Memory Region: External Memory Space (Region 3)
+		 * OSPI EVERSPIN MRAM
+		 *
+		 */
+		reg = <0x05 0x00000000 0x01 0x00000000>;
+	};
+};
+
+&mcu_pmx0 {
+	mcu_spi0_pins: mcu-spi0-pins {
+		pinctrl-single,pins = <
+			AM64X_MCU_IOPAD(0x008, PIN_OUTPUT, 0)   /* (A7) MCU_SPI0_CLK SCLK */
+			AM64X_MCU_IOPAD(0x000, PIN_OUTPUT, 0)   /* (E8) MCU_SPI0_CS0 nCS0 */
+			AM64X_MCU_IOPAD(0x00c, PIN_INPUT, 0)    /* (D9) MCU_SPI0_D0  MISO */
+			AM64X_MCU_IOPAD(0x010, PIN_OUTPUT, 0)   /* (C9) MCU_SPI0_D1  MOSI */
+		>;
+	};
+};
+
+&main_pmx0 {
+	main_mdio1_pins_default: main-mdio1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x160,  PIN_OUTPUT,       0) /* (AD24) MDIO0_MDC  not used, just for testing */
+			AM62X_IOPAD(0x15c,  PIN_INPUT_PULLUP, 0) /* (AB22) MDIO0_MDIO not used, just for testing */
+		>;
+	};
+
+	main_rgmii2_pins_default: main-rgmii2-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x184, PIN_INPUT,  0) /* (AE23) RGMII2_RD0 */
+			AM62X_IOPAD(0x188, PIN_INPUT,  0) /* (AB20) RGMII2_RD1 */
+			AM62X_IOPAD(0x18c, PIN_INPUT,  0) /* (AC21) RGMII2_RD2 */
+			AM62X_IOPAD(0x190, PIN_INPUT,  0) /* (AE22) RGMII2_RD3 */
+			AM62X_IOPAD(0x180, PIN_INPUT,  0) /* (AD23) RGMII2_RXC */
+			AM62X_IOPAD(0x17c, PIN_INPUT,  0) /* (AD22) RGMII2_RX_CTL */
+			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
+			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
+			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
+			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
+			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
+			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
+		>;
+	};
+
+	usb1_pins_default: usb1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */
+		>;
+	};
+
+	mram_irq_pins_default: mram-irq-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 (nINT-nVMEM) */
+		>;
+	};
+
+	ospi0_pins_default: ospi0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
+			AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
+			AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
+			AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
+			AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
+			AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
+			AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
+			AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
+			AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
+			AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
+			AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
+		>;
+	};
+};
+
+&watchdog_ext {
+	status = "okay";
+};
+
+&gpmc0 {
+	status = "disabled";
+};
+
+&mcu_spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_spi0_pins>;
+};
+
+&main_spi0 {
+	status = "okay";
+};
+
+&main_spi2 {
+	status = "okay";
+};
+
+&ospi0 {
+	/* The default has also 'cdns,qspi-nor' set which
+	 * sets CQSPI_DISABLE_DAC_MODE in spi-cadence-quadspi.c
+	 * and by this disables the 'Direct access controller' (DAC).
+	 */
+	compatible = "ti,am654-ospi";
+	pinctrl-names = "default";
+	pinctrl-0 = <&ospi0_pins_default>;
+	status = "okay";
+
+        /* Everspin Tech. EM008LXO
+         * Order-No EM008LXOAB320IS1R
+         */
+	mram: mram@0 {
+                pinctrl-names = "default";
+		pinctrl-0 = <&mram_irq_pins_default>;
+
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
+
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-tx-bus-width = <8>;
+		spi-rx-bus-width = <8>;
+		spi-max-frequency = <25000000>;
+		cdns,tshsl-ns = <60>;
+		cdns,tsd2d-ns = <60>;
+		cdns,tchsh-ns = <60>;
+		cdns,tslch-ns = <60>;
+		cdns,read-delay = <4>;
+		cdns,phy-mode;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "ospi.mram.mem";
+				reg = <0x0 0x800000>;
+			};
+		};
+	};
+};
+
+&main_i2c0 {
+	status = "okay";
+
+	eeprom_hw_id_wosm: at24c02@50 {
+		status = "disabled";
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+
+	tps65219: pmic@30 {
+		compatible = "ti,tps65219";
+		reg = <0x30>;
+		system-power-controller;
+
+		buck1-supply = <&vcc_5v0>;
+		buck2-supply = <&vcc_5v0>;
+		buck3-supply = <&vcc_5v0>;
+		ldo1-supply = <&vcc_3v3_sys>;
+		ldo2-supply = <&vcc_1v8_sys>;
+		ldo3-supply = <&vcc_3v3_sys>;
+		ldo4-supply = <&vcc_3v3_sys>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_irq_pins_default>;
+
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <68 IRQ_TYPE_EDGE_FALLING>;
+
+                /* NOTICE:
+                 *
+                 * We could use "tps65219-gpio" here with GPO1 (EN-DCDC-1V8)
+                 * and GPO2 (CARRIER_PWR_EN for SD-Card and I2C1 devices) enabled,
+                 * but will skip it for now and trust the bootloader or TPS-NVM for the
+                 * correct settings correctly.
+                 *
+                 * For now we declare vcc_1v8_sys as being fixed.
+                 *
+                 */
+		regulators {
+			buck1_30_reg: buck1 {
+				regulator-name = "VDD_CORE";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck2_30_reg: buck2 {
+				regulator-name = "VCC3V3";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck3_30_reg: buck3 {
+				regulator-name = "VDD_LPDDR4";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_30_sd_1v8_reg: ldo1 {
+				regulator-name = "VDDSHV_SD_1V8_IO_PMIC";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+			};
+
+			ldo2_30_reg: ldo2 {
+				regulator-name = "VDDAR_CORE";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_30_reg: ldo3 {
+				regulator-name = "VDDA_1V8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_30_reg: ldo4 {
+				regulator-name = "VDDA_2V5";
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&main_i2c1 {
+	status = "okay";
+};
+
+&sdhci0 { /* eMMC */
+	status = "okay";
+};
+
+&sdhci1 { /* SD */
+	status = "okay";
+
+	vmmc-supply = <&vcc_3v3_sys>;
+	vqmmc-supply = <&ldo1_30_sd_1v8_reg>;
+};
+
+&cpsw3g {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mdio1_pins_default
+		     &main_rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+	status = "disabled";
+};
+
+/*
+ * Use a fixed phy for emac2.
+ * that's rgmii2
+ */
+&cpsw_port2 {
+	status = "okay";
+	phy-mode = "rgmii-rxid";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&cpsw3g_mdio {
+	status = "disabled";
+};
+
+&usbss1 {
+	status = "okay";
+	ti,vbus-divider;
+};
+
+&usb1 {
+	status = "okay";
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb1_pins_default>;
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-750-8xxx-common.dtsi

@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common dtsi for AM62x based WAGO devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Copyright (C) 2025 WAGO GmbH & Co. KG <http://global.wago.com>
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-am625.dtsi"
+
+/ {
+	aliases {
+		serial2 = &main_uart0;
+		serial1 = &main_uart2;
+		serial4 = &main_uart4;
+		mmc0 = &sdhci1;
+		mmc1 = &sdhci0;
+		ethernet0 = &cpsw_port1;
+		ethernet1 = &cpsw_port2;
+		usb0 = &usb0;
+		watchdog0 = &main_rti0;
+		watchdog1 = &watchdog_ext;
+		watchdog2 = &main_rti1;
+		eeprom_typelabel = &eeprom_type_label;
+	};
+
+	opp-table {
+		opp-200000000 {
+			opp-microvolt = <750000>;
+		};
+
+		opp-400000000 {
+			opp-microvolt = <750000>;
+		};
+
+		opp-600000000 {
+			opp-microvolt = <750000>;
+		};
+
+		opp-800000000 {
+			opp-microvolt = <750000>;
+		};
+
+		opp-1000000000 {
+			opp-microvolt = <750000>;
+		};
+
+		opp-1250000000 {
+			opp-microvolt = <750000>;
+		};
+
+		opp-1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-microvolt = <850000>;
+			opp-supported-hw = <0x01 0x0004>;
+			clock-latency-ns = <6000000>;
+		};
+	};
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ramoops@9ca00000 {
+			compatible = "ramoops";
+			reg = <0x00 0x9ca00000 0x00 0x00100000>;
+			record-size = <0x8000>;
+			console-size = <0x8000>;
+			ftrace-size = <0x00>;
+			pmsg-size = <0x8000>;
+		};
+
+		secure_tfa_ddr: tfa@9e780000 {
+			reg = <0x00 0x9e780000 0x00 0x80000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9db00000 0x00 0xc00000>;
+			no-map;
+		};
+
+		mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9cb00000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_m4fss_memory_region: m4f-memory@9cc00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9cc00000 0x00 0xe00000>;
+			no-map;
+		};
+	};
+
+	vmain_pd: regulator-0 {
+		/* TPS6522005 Dual PMIC */
+		compatible = "regulator-fixed";
+		regulator-name = "vmain_pd";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_5v0: regulator-1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vmain_pd>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_3v3_sys: regulator-2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_sys";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vmain_pd>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	watchdog_ext: watchdog {
+		compatible = "linux,wdt-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wdg_ext_pins_default>;
+		hw_algo = "toggle";
+		hw_margin_ms = <1120>; /* STWD100xY: min. 1120, typ. 1600 */
+		en-gpios = <&main_gpio0 42 GPIO_ACTIVE_LOW>;
+		gpios = <&main_gpio1 30 GPIO_ACTIVE_LOW>;
+	};
+
+	wsysinit: wsysinit_init {
+		compatible = "wago,sysinit";
+
+		tty,rs232-485 = "ttyS0";
+	};
+};
+
+&main_pmx0 {
+	main_uart0_pins_default: main-uart0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
+			AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+		>;
+	};
+
+	main_uart2_pins_default: main-uart2-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01d0, PIN_INPUT,  3) /* (A15) UART0_CTSn.UART2_RXD */
+			AM62X_IOPAD(0x01d4, PIN_OUTPUT, 3) /* (B15) UART0_RTSn.UART2_TXD */
+		>;
+	};
+
+	main_uart4_pins_default: main-uart4-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0b0, PIN_INPUT, 3) /* (K22) UART4_RXD */
+			AM62X_IOPAD(0x0b4, PIN_OUTPUT, 3) /* (K24) UART4_TXD */
+			AM62X_IOPAD(0x09c, PIN_OUTPUT_PULLDOWN, 7) /* (V25) GPIO0_38 (RS-DE) */
+		>;
+	};
+
+	main_i2c0_pins_default: main-i2c0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
+			AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
+		>;
+	};
+
+	main_i2c1_pins_default: main-i2c1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
+			AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
+		>;
+	};
+
+	main_mmc0_pins_default: main-mmc0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x220, PIN_INPUT,  0) /* (Y3) MMC0_CMD */
+			AM62X_IOPAD(0x218, PIN_OUTPUT, 0) /* (AB1) MMC0_CLK */
+			AM62X_IOPAD(0x214, PIN_INPUT,  0) /* (AA2) MMC0_DAT0 */
+			AM62X_IOPAD(0x210, PIN_INPUT,  0) /* (AA1) MMC0_DAT1 */
+			AM62X_IOPAD(0x20c, PIN_INPUT,  0) /* (AA3) MMC0_DAT2 */
+			AM62X_IOPAD(0x208, PIN_INPUT,  0) /* (Y4) MMC0_DAT3 */
+			AM62X_IOPAD(0x204, PIN_INPUT,  0) /* (AB2) MMC0_DAT4 */
+			AM62X_IOPAD(0x200, PIN_INPUT,  0) /* (AC1) MMC0_DAT5 */
+			AM62X_IOPAD(0x1fc, PIN_INPUT,  0) /* (AD2) MMC0_DAT6 */
+			AM62X_IOPAD(0x1f8, PIN_INPUT,  0) /* (AC2) MMC0_DAT7 */
+		>;
+	};
+
+	main_mmc1_pins_default: main-mmc1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x23c, PIN_INPUT,        0) /* (A21) MMC1_CMD */
+			AM62X_IOPAD(0x234, PIN_OUTPUT,       0) /* (B22) MMC1_CLK */
+			AM62X_IOPAD(0x230, PIN_INPUT,        0) /* (A22) MMC1_DAT0 */
+			AM62X_IOPAD(0x22c, PIN_INPUT,        0) /* (B21) MMC1_DAT1 */
+			AM62X_IOPAD(0x228, PIN_INPUT,        0) /* (C21) MMC1_DAT2 */
+			AM62X_IOPAD(0x224, PIN_INPUT,        0) /* (D22) MMC1_DAT3 */
+			AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
+			AM62X_IOPAD(0x244, PIN_INPUT_PULLUP, 0) /* (C17) MMC1_SDWP */
+		>;
+	};
+
+	main_spi0_pins_default: main-spi0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (A14) SPI0_CLK */
+			AM62X_IOPAD(0x01c0, PIN_INPUT,  0) /* (B13) SPI0_D0  */
+			AM62X_IOPAD(0x01c4, PIN_OUTPUT, 0) /* (B14) SPI0_D1  */
+			AM62X_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (A13) SPI0_CS0 */
+		>;
+
+	};
+
+	main_spi2_pins_default: main-spi2-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01b0, PIN_OUTPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
+			AM62X_IOPAD(0x0194, PIN_INPUT,  1) /* (B19) MCASP0_AXR3.SPI2_D0 */
+			AM62X_IOPAD(0x0198, PIN_OUTPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */
+			AM62X_IOPAD(0x01ac, PIN_OUTPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */
+		>;
+	};
+
+	wdg_ext_pins_default: wdg-ext-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x00ac, PIN_OUTPUT_PULLUP | INPUT_EN, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */
+			AM62X_IOPAD(0x01f0, PIN_OUTPUT, 7) /* (A18) EXT_REFCLK1.GPIO1_30 */
+		>;
+	};
+
+	pmic_irq_pins_default: pmic-irq-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0114, PIN_INPUT, 7) /* (B24) MMC2_DAT0.GPIO0_68 */
+		>;
+	};
+};
+
+&main_uart0 { /* DGB UART */
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+&main_uart2 { /* KBUS Firmware download */
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart2_pins_default>;
+};
+
+&main_uart4 { /* RS485 */
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart4_pins_default>;
+};
+
+&main_i2c0 { /* type label */
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <400000>;
+
+	eeprom_type_label: at24c512@54 {
+		compatible = "atmel,24c512";
+		reg = <0x54>;
+		pagesize = <128>;
+	};
+};
+
+&main_spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_spi0_pins_default>;
+
+	dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
+	dma-names = "tx0", "rx0";
+
+	/*
+	 * When this option is set, the McSPI EOW Interrupt will be used
+	 * to signal when a DMA Transfer is done. This is needed for this
+	 * platform to prevent unpredictable delays resulting from TX/RX
+	 * completions within the UDMA driver.
+	 */
+	use-eow-interrupt;
+};
+
+&main_spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_spi2_pins_default>;
+};
+
+&main_i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c1_pins_default>;
+	clock-frequency = <400000>;
+
+	rtc@52 {
+		compatible = "microcrystal,rv3028";
+		reg = <0x52>;
+		// The backup goldcap is supplied with a higher voltage (+5V)
+		// then the RTC (+3,3) itself. It requires a special setup
+		// to avoid hardware failure.
+		use-goldcap-with-higher-voltage;
+	};
+};
+
+&sdhci0 {
+	/* eMMC */
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mmc0_pins_default>;
+	ti,driver-strength-ohm = <33>;
+	disable-wp;
+};
+
+&sdhci1 {
+        /* SD */
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mmc1_pins_default>;
+	ti,driver-strength-ohm = <33>;
+	disable-wp;
+};
+
+&mailbox0_cluster0 {
+	mbox_m4_0: mbox-m4-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+/*
+ * AM6232 does not have main_rti2, main_rti3, and main_rti15
+ * https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1218039/am623-stuck-in-sd-card-after-boot-up
+ */
+&main_rti2 {    // watchdog@e020000
+    status = "disabled";
+};
+
+&main_rti3 {    // watchdog@e030000
+    status = "disabled";
+};
+
+&main_rti15 {   // watchdog@e0f0000
+    status = "disabled";
+};
+
+&usbss0 {
+	status = "okay";
+	ti,vbus-divider;
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "peripheral";
+};
+
+&mcu_m4fss {
+	mboxes = <&mailbox0_cluster0 &mbox_m4_0>;
+	memory-region = <&mcu_m4fss_dma_memory_region>,
+			<&mcu_m4fss_memory_region>;
+	status = "okay";
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-kbus.dtsi

@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+* Common dtsi for AM62x WAGO based devices
+*
+* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+* Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+*/
+
+&main_pmx0 {
+	kbus_pins_default: kbus-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0100, PIN_INPUT_PULLUP,    7) /* (AC25) VOUT0_VSYNC.GPIO0_63 (kbus,nsync) */
+			AM62X_IOPAD(0x0128, PIN_OUTPUT_PULLDOWN, 7) /* (B23) MMC2_SDWP.GPIO0_72 (kbus,nrst) */
+			AM62X_IOPAD(0x0118, PIN_OUTPUT_PULLUP,   7) /* (D25) MMC2_CLK.GPIO0_69 (kbus,cmdsel) */
+			AM62X_IOPAD(0x0104, PIN_OUTPUT_PULLUP,   7) /* (AC24) VOUT0_PCLK.GPIO0_64 (kbus,nirq) */
+			AM62X_IOPAD(0x0120, PIN_INPUT_PULLUP,    7) /* (C24) MMC2_CMD.GPIO0_70 (kbus,nerr) */
+			AM62X_IOPAD(0x0124, PIN_INPUT_PULLUP,    7) /* (A23) MMC2_SDCD.GPIO0_71 (kbus,nrdy) */
+		>;
+	};
+};
+
+&main_spi0 {
+	spi-rt;
+	spi-rt-prio = <81>;
+
+	kbus@0 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&kbus_pins_default>;
+		compatible = "wago,spi-kbus";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+
+		kbus,reset-on-boot;
+
+		/*
+		 * kbus,cmdsel-gpio is used to signal the need for an update
+		 * while the KBUS slave cpu is being reset. Its low level
+		 * forces an update.
+		 */
+		kbus,force-update-detection;
+
+		/*
+		 * announce used tty-device in /sys/class/wago/system.
+		 * is needed to link this device to /dev/ttyKbus
+		 */
+		/* TODO: check serial device name in user-space */
+		kbus,tty-device = "ttyS1"; /* corresponds to &uart2*/
+
+		/* some should be active low, keep all to high for compatibility reasons */
+		kbus,nrst-gpio   = <&main_gpio0 72 GPIO_ACTIVE_LOW>;
+		kbus,nsync-gpio  = <&main_gpio0 63 GPIO_ACTIVE_HIGH>;
+		kbus,cmdsel-gpio = <&main_gpio0 69 GPIO_ACTIVE_HIGH>;
+		kbus,nirq-gpio   = <&main_gpio0 64 GPIO_ACTIVE_HIGH>;
+		kbus,nerr-gpio   = <&main_gpio0 70 GPIO_ACTIVE_HIGH>;
+		kbus,nrdy-gpio   = <&main_gpio0 71 GPIO_ACTIVE_HIGH>;
+	};
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-rs485.dtsi

@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common dtsi for AM62x WAGO based devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+&main_i2c1 {
+        /*
+         * PCA9538, 8-Bit I/O Expander
+         */
+	io_exp_8bit: io-exp-8bit@71 {
+		compatible = "nxp,pca9538";
+		reg = <0x71>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "RS.TERM-EN", "RS.SLR",
+				  "+5V0-FB-ENA", "IO3",
+				  "BIAS.EN", "BIAS.HIR",
+				  "IO6", "IO7";
+
+                rs485-5v { /* +5V0-FB-ENA */
+                    gpio-hog;
+                    gpios = <2 GPIO_ACTIVE_HIGH>;
+                    output-high;
+                };
+        };
+};
+
+&main_uart4 { /* RS485 Interface */
+	rts-gpios = <&main_gpio0 38 GPIO_ACTIVE_HIGH>;
+	rs485-term-gpios = <&io_exp_8bit 0 GPIO_ACTIVE_HIGH>;
+	rs485-rts-active-high;
+	linux,rs485-enabled-at-boot-time;
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-rtc.dtsi

@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common Real-Time-Clock dtsi for AM62x WAGO based devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+&main_i2c1 {
+	rtc@52 {
+		compatible = "microcrystal,rv3028";
+		reg = <0x52>;
+
+		/* 
+                 * The backup goldcap is supplied with a higher voltage (+5V)
+		 * then the RTC (+3,3) itself. It requires a special setup
+		 * to avoid hardware failure.
+                 */
+		use-goldcap-with-higher-voltage;
+	};
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-tpm.dtsi

@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common Trusted Platform Module dtsi for AM62x based WAGO devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+&main_pmx0 {
+	tpm_pins_default: tpm-pins-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x010c, PIN_INPUT, 7) /* (E23) MMC2_DAT2.GPIO0_66 */
+		>;
+	};
+};
+
+&main_spi2 {
+	SLB9670: SLB9670@0 {
+		status = "disabled";
+		compatible = "infineon,slb9670", "tis,tpm2-spi", "tcg,tpm_tis-spi";
+		reg = <0>;
+		#gpio-cells = <2>;
+		#interrupt-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&tpm_pins_default>;
+		
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <66 IRQ_TYPE_EDGE_FALLING>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		spi-max-frequency = <43000000>;
+	};
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-wled.dtsi

@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common dtsi for AM62x WAGO based devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+&main_spi2 {
+        led-controller@0 {
+            compatible = "worldsemi,ws2812b";
+            reg = <0>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            spi-max-frequency = <2850000>;
+
+            multi-led@0 {
+                reg = <0>;
+                color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
+                color = <LED_COLOR_ID_RGB>;
+                function = LED_FUNCTION_STATUS;
+                function-enumerator = <0>;
+            };
+
+            multi-led@1 {
+                reg = <1>;
+                color = <LED_COLOR_ID_RGB>;
+                function = LED_FUNCTION_STATUS;
+                function-enumerator = <1>;
+            };
+
+            multi-led@2 {
+                reg = <2>;
+                color = <LED_COLOR_ID_RGB>;
+                function = LED_FUNCTION_STATUS;
+                function-enumerator = <2>;
+            };
+
+            multi-led@3 {
+                reg = <3>;
+                color = <LED_COLOR_ID_RGB>;
+                function = LED_FUNCTION_STATUS;
+                function-enumerator = <3>;
+            };
+
+            multi-led@4 {
+                reg = <4>;
+                color = <LED_COLOR_ID_RGB>;
+                function = LED_FUNCTION_STATUS;
+                function-enumerator = <4>;
+            };
+        };
+};

arch/arm64/boot/dts/ti/k3-am62x-pfc.dtsi

@@ -1,910 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Common dtsi for AM62x WAGO based devices
- *
- * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
- *
- * Copyright (C) 2024 WAGO GmbH & Co. KG <http://global.wago.com>
- *     Oleg Karfich <oleg.karfich@wago.com>
- *     Andrej Unrau <andrej.unrau@wago.com>
- */
-
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am625.dtsi"
-
-/ {
-	aliases {
-		serial2 = &main_uart0;
-		serial1 = &main_uart2;
-		serial4 = &main_uart4;
-		mmc0 = &sdhci1;
-		mmc1 = &sdhci0;
-		ethernet0 = &cpsw_port1;
-		ethernet1 = &cpsw_port2;
-		usb0 = &usb0;
-		watchdog0 = &main_rti0;
-		watchdog1 = &watchdog_ext;
-		watchdog2 = &main_rti1;
-	};
-
-	opp-table {
-		opp-200000000 {
-			opp-microvolt = <750000>;
-		};
-
-		opp-400000000 {
-			opp-microvolt = <750000>;
-		};
-
-		opp-600000000 {
-			opp-microvolt = <750000>;
-		};
-
-		opp-800000000 {
-			opp-microvolt = <750000>;
-		};
-
-		opp-1000000000 {
-			opp-microvolt = <750000>;
-		};
-
-		opp-1250000000 {
-			opp-microvolt = <750000>;
-		};
-
-		opp-1400000000 {
-			opp-hz = /bits/ 64 <1400000000>;
-			opp-microvolt = <850000>;
-			opp-supported-hw = <0x01 0x0004>;
-			clock-latency-ns = <6000000>;
-		};
-	};
-
-	chosen {
-		stdout-path = "serial2:115200n8";
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		/* 2G RAM */
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		ramoops@9ca00000 {
-			compatible = "ramoops";
-			reg = <0x00 0x9ca00000 0x00 0x00100000>;
-			record-size = <0x8000>;
-			console-size = <0x8000>;
-			ftrace-size = <0x00>;
-			pmsg-size = <0x8000>;
-		};
-
-		secure_tfa_ddr: tfa@9e780000 {
-			reg = <0x00 0x9e780000 0x00 0x80000>;
-			alignment = <0x1000>;
-			no-map;
-		};
-
-		secure_ddr: optee@9e800000 {
-			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
-			alignment = <0x1000>;
-			no-map;
-		};
-
-		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0x9db00000 0x00 0xc00000>;
-			no-map;
-		};
-	};
-
-	wsysinit: wsysinit_init {
-		compatible = "wago,sysinit";
-
-		tty,rs232-485 = "ttyS0";
-		board,variant = "pfc300";
-	};
-
-	/* this name of the gpio-keys device is a
-	 * historical heritage from 3.6.11 kernel.
-	 * the device-name is checked in omsd. So we
-	 * need to adapt this configuration
-	 */
-	oms: PAC-Operating-Mode-Switch {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&oms_pins_default>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		autorepeat;
-
-		oms_run: run {
-			label = "RUN";
-			gpios = <&main_gpio0 65 GPIO_ACTIVE_LOW>;
-			linux,code = <1>;
-			linux,input-type = <5>;
-			debounce-interval = <1>;
-		};
-
-		oms_stop: stop {
-			label = "STOP";
-			gpios = <&main_gpio1 10 GPIO_ACTIVE_LOW>;
-			linux,code = <2>;
-			linux,input-type = <5>;
-			debounce-interval = <1>;
-		};
-
-		oms_reset: reset {
-			label = "RESET";
-			gpios = <&main_gpio1 12 GPIO_ACTIVE_LOW>;
-			linux,code = <3>;
-			linux,input-type = <1>;
-			debounce-interval = <1>;
-		};
-
-		oms_reset_all: reset_all {
-			label = "RESET_ALL";
-			gpios = <&main_gpio1 11 GPIO_ACTIVE_HIGH>;
-			linux,code = <4>;
-			linux,input-type = <1>;
-			debounce-interval = <1>;
-		};
-	};
-
-	uio_nvram: nvram@51000000 {
-		compatible = "uio_pdrv_genirq";
-		linux,uio-name = "UIO_NVRAM";
-		reg = <0 0x51000000 0 0x00020000>; /* 128k 16bit NVRAM */
-	};
-
-	vmain_pd: regulator-0 {
-		/* TPS6522005 Dual PMIC */
-		compatible = "regulator-fixed";
-		regulator-name = "vmain_pd";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vcc_5v0: regulator-1 {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_5v0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vmain_pd>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vcc_3v3_sys: regulator-2 {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_3v3_sys";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vmain_pd>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vdd_mmc1: regulator-3 {
-		compatible = "regulator-fixed";
-	 	pinctrl-names = "default";
-	 	pinctrl-0 = <&vdd_sd_dv_pins_default>;
-		regulator-name = "vdd_mmc1";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		vin-supply = <&vcc_3v3_sys>;
-		gpio = <&main_gpio0 31 GPIO_ACTIVE_LOW>;
-		enable-active-high;
-		startup-delay-us = <5000>;
-	};
-
-	watchdog_ext: watchdog {
-		compatible = "linux,wdt-gpio";
-		pinctrl-names = "default";
-		pinctrl-0 = <&wdg_ext_pins_default>;
-		hw_algo = "toggle";
-		hw_margin_ms = <1120>; /* STWD100xY: min. 1120, typ. 1600 */
-		en-gpios = <&main_gpio0 42 GPIO_ACTIVE_LOW>;
-		gpios = <&main_gpio1 30 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&main_pmx0 {
-	main_uart0_pins_default: main-uart0-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
-			AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
-		>;
-	};
-
-	main_uart2_pins_default: main-uart2-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x01d0, PIN_INPUT,  3) /* (A15) UART0_CTSn.UART2_RXD */
-			AM62X_IOPAD(0x01d4, PIN_OUTPUT, 3) /* (B15) UART0_RTSn.UART2_TXD */
-		>;
-	};
-
-	main_uart4_pins_default: main-uart4-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x0b0, PIN_INPUT, 3) /* (K22) UART4_RXD */
-			AM62X_IOPAD(0x0b4, PIN_OUTPUT, 3) /* (K24) UART4_TXD */
-			AM62X_IOPAD(0x09c, PIN_OUTPUT_PULLDOWN, 7) /* (V25) GPIO0_38 (RS-DE) */
-		>;
-	};
-
-	main_i2c0_pins_default: main-i2c0-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
-			AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
-		>;
-	};
-
-	main_i2c1_pins_default: main-i2c1-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
-			AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
-		>;
-	};
-
-	main_mmc0_pins_default: main-mmc0-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x220, PIN_INPUT,  0) /* (Y3) MMC0_CMD */
-			AM62X_IOPAD(0x218, PIN_OUTPUT, 0) /* (AB1) MMC0_CLK */
-			AM62X_IOPAD(0x214, PIN_INPUT,  0) /* (AA2) MMC0_DAT0 */
-			AM62X_IOPAD(0x210, PIN_INPUT,  0) /* (AA1) MMC0_DAT1 */
-			AM62X_IOPAD(0x20c, PIN_INPUT,  0) /* (AA3) MMC0_DAT2 */
-			AM62X_IOPAD(0x208, PIN_INPUT,  0) /* (Y4) MMC0_DAT3 */
-			AM62X_IOPAD(0x204, PIN_INPUT,  0) /* (AB2) MMC0_DAT4 */
-			AM62X_IOPAD(0x200, PIN_INPUT,  0) /* (AC1) MMC0_DAT5 */
-			AM62X_IOPAD(0x1fc, PIN_INPUT,  0) /* (AD2) MMC0_DAT6 */
-			AM62X_IOPAD(0x1f8, PIN_INPUT,  0) /* (AC2) MMC0_DAT7 */
-		>;
-	};
-
-	main_mmc1_pins_default: main-mmc1-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x23c, PIN_INPUT,        0) /* (A21) MMC1_CMD */
-			AM62X_IOPAD(0x234, PIN_OUTPUT,       0) /* (B22) MMC1_CLK */
-			AM62X_IOPAD(0x230, PIN_INPUT,        0) /* (A22) MMC1_DAT0 */
-			AM62X_IOPAD(0x22c, PIN_INPUT,        0) /* (B21) MMC1_DAT1 */
-			AM62X_IOPAD(0x228, PIN_INPUT,        0) /* (C21) MMC1_DAT2 */
-			AM62X_IOPAD(0x224, PIN_INPUT,        0) /* (D22) MMC1_DAT3 */
-			AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
-			AM62X_IOPAD(0x244, PIN_INPUT_PULLUP, 0) /* (C17) MMC1_SDWP */
-		>;
-	};
-
-	main_mdio1_pins_default: main-mdio1-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x160,  PIN_OUTPUT,       0) /* (AD24) MDIO0_MDC */
-			AM62X_IOPAD(0x15c,  PIN_INPUT_PULLUP, 0) /* (AB22) MDIO0_MDIO */
-			AM62X_IOPAD(0x019c, PIN_OUTPUT,       7) /* (B18) MCASP0_AXR1.GPIO1_9 */
-		>;
-	};
-
-	main_rgmii1_pins_default: main-rgmii1-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x14c, PIN_INPUT,  0) /* (AB17) RGMII1_RD0 */
-			AM62X_IOPAD(0x150, PIN_INPUT,  0) /* (AC17) RGMII1_RD1 */
-			AM62X_IOPAD(0x154, PIN_INPUT,  0) /* (AB16) RGMII1_RD2 */
-			AM62X_IOPAD(0x158, PIN_INPUT,  0) /* (AA15) RGMII1_RD3 */
-			AM62X_IOPAD(0x148, PIN_INPUT,  0) /* (AD17) RGMII1_RXC */
-			AM62X_IOPAD(0x144, PIN_INPUT,  0) /* (AE17) RGMII1_RX_CTL */
-			AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
-			AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
-			AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
-			AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
-			AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
-			AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
-			AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */
-		>;
-	};
-
-	main_rgmii2_pins_default: main-rgmii2-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x184, PIN_INPUT,  0) /* (AE23) RGMII2_RD0 */
-			AM62X_IOPAD(0x188, PIN_INPUT,  0) /* (AB20) RGMII2_RD1 */
-			AM62X_IOPAD(0x18c, PIN_INPUT,  0) /* (AC21) RGMII2_RD2 */
-			AM62X_IOPAD(0x190, PIN_INPUT,  0) /* (AE22) RGMII2_RD3 */
-			AM62X_IOPAD(0x180, PIN_INPUT,  0) /* (AD23) RGMII2_RXC */
-			AM62X_IOPAD(0x17c, PIN_INPUT,  0) /* (AD22) RGMII2_RX_CTL */
-			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
-			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
-			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
-			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
-			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
-			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
-			AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */
-		>;
-	};
-
-	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
-		>;
-	};
-
-	gpmc_data_pins_default: gpmc-data-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x00bc, PIN_OUTPUT, 1) /* (V24) VOUT0_DATA1.GPMC0_A1    */
-			AM62X_IOPAD(0x00c0, PIN_OUTPUT, 1) /* (W25) VOUT0_DATA2.GPMC0_A2    */
-			AM62X_IOPAD(0x00c4, PIN_OUTPUT, 1) /* (W24) VOUT0_DATA3.GPMC0_A3    */
-			AM62X_IOPAD(0x00c8, PIN_OUTPUT, 1) /* (Y25) VOUT0_DATA4.GPMC0_A4    */
-			AM62X_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (Y24) VOUT0_DATA5.GPMC0_A5    */
-			AM62X_IOPAD(0x00d0, PIN_OUTPUT, 1) /* (Y23) VOUT0_DATA6.GPMC0_A6    */
-			AM62X_IOPAD(0x00d4, PIN_OUTPUT, 1) /* (AA25) VOUT0_DATA7.GPMC0_A7   */
-			AM62X_IOPAD(0x00d8, PIN_OUTPUT, 1) /* (V21) VOUT0_DATA8.GPMC0_A8    */
-			AM62X_IOPAD(0x00dc, PIN_OUTPUT, 1) /* (W21) VOUT0_DATA9.GPMC0_A9    */
-			AM62X_IOPAD(0x00e0, PIN_OUTPUT, 1) /* (V20) VOUT0_DATA10.GPMC0_A10  */
-			AM62X_IOPAD(0x00e4, PIN_OUTPUT, 1) /* (AA23) VOUT0_DATA11.GPMC0_A11 */
-			AM62X_IOPAD(0x00e8, PIN_OUTPUT, 1) /* (AB25) VOUT0_DATA12.GPMC0_A12 */
-			AM62X_IOPAD(0x00ec, PIN_OUTPUT, 1) /* (AA24) VOUT0_DATA13.GPMC0_A13 */
-			AM62X_IOPAD(0x00f0, PIN_OUTPUT, 1) /* (Y22) VOUT0_DATA14.GPMC0_A14  */
-			AM62X_IOPAD(0x00f4, PIN_OUTPUT, 1) /* (AA21) VOUT0_DATA15.GPMC0_A15 */
-			AM62X_IOPAD(0x00f8, PIN_OUTPUT, 1) /* (AB24) VOUT0_HSYNC.GPMC0_A16  */
-		>;
-	};
-
-	gpmc_addr_pins_default: gpmc-addr-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (M25) GPMC0_AD0  */
-			AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (N23) GPMC0_AD1  */
-			AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (N24) GPMC0_AD2  */
-			AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (N25) GPMC0_AD3  */
-			AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (P24) GPMC0_AD4  */
-			AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (P22) GPMC0_AD5  */
-			AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (P21) GPMC0_AD6  */
-			AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (R23) GPMC0_AD7  */
-			AM62X_IOPAD(0x005c, PIN_INPUT, 0) /* (R24) GPMC0_AD8  */
-			AM62X_IOPAD(0x0060, PIN_INPUT, 0) /* (R25) GPMC0_AD9  */
-			AM62X_IOPAD(0x0064, PIN_INPUT, 0) /* (T25) GPMC0_AD10 */
-			AM62X_IOPAD(0x0068, PIN_INPUT, 0) /* (R21) GPMC0_AD11 */
-			AM62X_IOPAD(0x006c, PIN_INPUT, 0) /* (T22) GPMC0_AD12 */
-			AM62X_IOPAD(0x0070, PIN_INPUT, 0) /* (T24) GPMC0_AD13 */
-			AM62X_IOPAD(0x0074, PIN_INPUT, 0) /* (U25) GPMC0_AD14 */
-			AM62X_IOPAD(0x0078, PIN_INPUT, 0) /* (U24) GPMC0_AD15 */
-		>;
-	};
-
-	gpmc_ctrl_pins_default: gpmc-ctrl-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x0094, PIN_OUTPUT, 0) /* (N20) GPMC0_BE1n     */
-			AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (M21) GPMC0_CSn0     */
-			AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (L24) GPMC0_OEn_REn  */
-			AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L25) GPMC0_WEn      */
-			AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (M24) GPMC0_BE0n_CLE */
-		>;
-	};
-
-	oms_pins_default: oms-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x0108, PIN_INPUT, 7) /* (D24) MMC2_DAT3.GPIO0_65 */
-			AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
-			AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */
-			AM62X_IOPAD(0x01a4, PIN_INPUT, 7) /* (B20) MCASP0_ACLKX.GPIO1_11 */
-		>;
-	};
-
-	main_spi0_pins_default: main-spi0-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (A14) SPI0_CLK */
-			AM62X_IOPAD(0x01c0, PIN_INPUT,  0) /* (B13) SPI0_D0  */
-			AM62X_IOPAD(0x01c4, PIN_OUTPUT, 0) /* (B14) SPI0_D1  */
-			AM62X_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (A13) SPI0_CS0 */
-		>;
-
-	};
-
-	main_spi2_pins_default: main-spi2-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x01b0, PIN_OUTPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
-			AM62X_IOPAD(0x0194, PIN_INPUT,  1) /* (B19) MCASP0_AXR3.SPI2_D0 */
-			AM62X_IOPAD(0x0198, PIN_INPUT,  1) /* (A19) MCASP0_AXR2.SPI2_D1 */
-			AM62X_IOPAD(0x01ac, PIN_OUTPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */
-		>;
-	};
-
-	tpm_pins_default: tpm-pins-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x010c, PIN_INPUT, 7) /* (E23) MMC2_DAT2.GPIO0_66 */
-		>;
-	};
-
-	kbus_pins_default: kbus-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x0100, PIN_INPUT_PULLUP,    7) /* (AC25) VOUT0_VSYNC.GPIO0_63 (kbus,nsync) */
-			AM62X_IOPAD(0x0128, PIN_OUTPUT_PULLDOWN, 7) /* (B23) MMC2_SDWP.GPIO0_72 (kbus,nrst) */
-			AM62X_IOPAD(0x0118, PIN_OUTPUT_PULLUP,   7) /* (D25) MMC2_CLK.GPIO0_69 (kbus,cmdsel) */
-			AM62X_IOPAD(0x0104, PIN_OUTPUT_PULLUP,   7) /* (AC24) VOUT0_PCLK.GPIO0_64 (kbus,nirq) */
-			AM62X_IOPAD(0x0120, PIN_INPUT_PULLUP,    7) /* (C24) MMC2_CMD.GPIO0_70 (kbus,nerr) */
-			AM62X_IOPAD(0x0124, PIN_INPUT_PULLUP,    7) /* (A23) MMC2_SDCD.GPIO0_71 (kbus,nrdy) */
-		>;
-	};
-
-	wdg_ext_pins_default: wdg-ext-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x00ac, PIN_OUTPUT_PULLUP | INPUT_EN, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */
-			AM62X_IOPAD(0x01f0, PIN_OUTPUT, 7) /* (A18) EXT_REFCLK1.GPIO1_30 */
-		>;
-	};
-
-	pmic_irq_pins_default: pmic-irq-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x0114, PIN_INPUT, 7) /* (B24) MMC2_DAT0.GPIO0_68 */
-		>;
-	};
-};
-
-&gpmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&gpmc_data_pins_default>, <&gpmc_addr_pins_default>, <&gpmc_ctrl_pins_default>;
-
-	num-cs = <4>;
-	num-waitpins = <4>;
-	ranges = <
-		0 0 0x00 0x51000000 0x01000000	/* CS0: NVRAM, 16M */
-	>;
-
-	nvram: nor@0,0 { /* NVRAM Device 128k */
-		reg = <0 0 0x01000000>;
-		bank-width = <2>; /* 1: 8bit, 2: 16bit */
-		gpmc,sync-clk-ps = <0>;
-		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <50>;
-		gpmc,cs-wr-off-ns = <30>;
-		gpmc,adv-on-ns = <0>;
-		gpmc,adv-rd-off-ns = <0>;
-		gpmc,adv-wr-off-ns = <0>;
-		gpmc,oe-on-ns = <0>;
-		gpmc,oe-off-ns = <50>;
-		gpmc,we-on-ns = <0>;
-		gpmc,we-off-ns = <30>;
-		gpmc,rd-cycle-ns = <50>;
-		gpmc,wr-cycle-ns = <30>;
-		gpmc,access-ns = <40>;
-		gpmc,wr-access-ns = <10>;
-		gpmc,wr-data-mux-bus-ns = <0>;
-		gpmc,cycle2cycle-delay-ns = <10>;
-		gpmc,cycle2cycle-samecsen;
-		gpmc,cycle2cycle-diffcsen;
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-};
-
-&main_uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart0_pins_default>;
-};
-
-&main_uart2 { /* KBUS Firmware download */
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart2_pins_default>;
-};
-
-&main_uart4 { /* RS485 Interface */
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart4_pins_default>;
-
-	rts-gpios = <&main_gpio0 38 GPIO_ACTIVE_HIGH>;
-	rs485-term-gpios = <&rs485 0 GPIO_ACTIVE_HIGH>;
-	rs485-rts-active-high;
-	linux,rs485-enabled-at-boot-time;
-};
-
-&main_i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c0_pins_default>;
-	clock-frequency = <400000>;
-
-	eeprom: at24c512@54 {
-		compatible = "atmel,24c512";
-		reg = <0x54>;
-		pagesize = <128>;
-	};
-
-	led_bar60: pca9552@60 {
-		compatible = "nxp,pca9552";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x60>;
-
-		lb60_0: sys-red@0 {
-			label = "sys-red";
-			reg = <0>;
-			linux,default-trigger = "timer";
-		};
-
-		lb60_1: sys-green@1 {
-			label = "sys-green";
-			reg = <1>;
-			linux,default-trigger = "timer";
-		};
-
-		lb60_2: run-red@2 {
-			label = "run-red";
-			reg = <2>;
-		};
-
-		lb60_3: run-green@3 {
-			label = "run-green";
-			reg = <3>;
-		};
-
-		lb60_4: io-red@4 {
-			label = "io-red";
-			reg = <4>;
-		};
-
-		lb60_5: io-green@5 {
-			label = "io-green";
-			reg = <5>;
-		};
-
-		lb60_6: ms-red@6 {
-			label = "ms-red";
-			reg = <6>;
-		};
-
-		lb60_7: ms-green@7 {
-			label = "ms-green";
-			reg = <7>;
-		};
-
-		lb60_8: ns-red@8 {
-			label = "ns-red";
-			reg = <8>;
-		};
-
-		lb60_9: ns-green@9 {
-			label = "ns-green";
-			reg = <9>;
-		};
-
-		lb60_10: usr_r@10 {
-			label = "trm-red";
-			reg = <10>;
-		};
-
-		lb60_11: usr_g@11 {
-			label = "trm-green";
-			reg = <11>;
-		};
-
-		lb60_15: sys-over-red@15 {
-			label = "sys-over-red";
-			reg = <15>;
-			linux,default-trigger = "default-on";
-		};
-	};
-
-	led_bar61: pca9552@61 {
-		compatible = "nxp,pca9552";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x61>;
-
-		lb61_0: u6-red@0 {
-			label = "u6-red";
-			reg = <0>;
-		};
-
-		lb61_1: u6-green@1 {
-			label = "u6-green";
-			reg = <1>;
-		};
-
-		lb61_2: u5-red@2 {
-			label = "u5-red";
-			reg = <2>;
-		};
-
-		lb61_3: u5-green@3 {
-			label = "u5-green";
-			reg = <3>;
-		};
-
-		lb61_4: u4-red@4 {
-			label = "u4-red";
-			reg = <4>;
-		};
-
-		lb61_5: u4-green@5 {
-			label = "u4-green";
-			reg = <5>;
-		};
-
-		lb61_6: u3-red@6 {
-			label = "u3-red";
-			reg = <6>;
-		};
-
-		lb61_7: u3-green@7 {
-			label = "u3-green";
-			reg = <7>;
-		};
-
-		lb61_8: u2-red@8 {
-			label = "u2-red";
-			reg = <8>;
-		};
-
-		lb61_9: u2-green@9 {
-			label = "u2-green";
-			reg = <9>;
-		};
-
-		lb61_10: u1-red@10 {
-			label = "u1-red";
-			reg = <10>;
-		};
-
-		lb61_11: u1-green@11 {
-			label = "u1-green";
-			reg = <11>;
-		};
-	};
-
-	tps65219_30: pmic@30 {
-		compatible = "ti,tps65219";
-		reg = <0x30>;
-		system-power-controller;
-
-		buck1-supply = <&vcc_5v0>;
-		buck2-supply = <&vcc_5v0>;
-		buck3-supply = <&vcc_5v0>;
-		ldo1-supply = <&vcc_3v3_sys>;
-		ldo2-supply = <&vcc_3v3_sys>;
-		ldo3-supply = <&vcc_5v0>;
-		ldo4-supply = <&vcc_5v0>;
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_irq_pins_default>;
-
-		interrupt-parent = <&main_gpio0>;
-		interrupts = <68 IRQ_TYPE_EDGE_FALLING>;
-
-		regulators {
-			buck1_30_reg: buck1 {
-				regulator-name = "VDD_CORE";
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <850000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck2_30_reg: buck2 {
-				regulator-name = "VCC1V8_SYS";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck3_30_reg: buck3 {
-				regulator-name = "VCC3V3_SYS";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo1_30_reg: ldo1 {
-				regulator-name = "VCC3V3_SDC";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-			};
-
-			ldo2_30_reg: ldo2 {
-				regulator-name = "VDDA_1V8";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-};
-
-&main_spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_spi0_pins_default>;
-
-	spi-rt;
-	spi-rt-prio = <81>;
-	dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
-	dma-names = "tx0", "rx0";
-
-	/*
-	 * When this option is set, the McSPI EOW Interrupt will be used
-	 * to signal when a DMA Transfer is done. This is needed for this
-	 * platform to prevent unpredictable delays resulting from TX/RX
-	 * completions within the UDMA driver.
-	 */
-	use-eow-interrupt;
-
-	kbus@0 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&kbus_pins_default>;
-		compatible = "wago,spi-kbus";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-
-		kbus,reset-on-boot;
-
-		/*
-		 * kbus,cmdsel-gpio is used to signal the need for an update
-		 * while the KBUS slave cpu is being reset. Its low level
-		 * forces an update.
-		 */
-		kbus,force-update-detection;
-
-		/*
-		 * announce used tty-device in /sys/class/wago/system.
-		 * is needed to link this device to /dev/ttyKbus
-		 */
-		/* TODO: check serial device name in user-space */
-		kbus,tty-device = "ttyS1"; /* corresponds to &uart2*/
-
-		/* some should be active low, keep all to high for compatibility reasons */
-		kbus,nrst-gpio   = <&main_gpio0 72 GPIO_ACTIVE_LOW>;
-		kbus,nsync-gpio  = <&main_gpio0 63 GPIO_ACTIVE_HIGH>;
-		kbus,cmdsel-gpio = <&main_gpio0 69 GPIO_ACTIVE_HIGH>;
-		kbus,nirq-gpio   = <&main_gpio0 64 GPIO_ACTIVE_HIGH>;
-		kbus,nerr-gpio   = <&main_gpio0 70 GPIO_ACTIVE_HIGH>;
-		kbus,nrdy-gpio   = <&main_gpio0 71 GPIO_ACTIVE_HIGH>;
-	};
-
-};
-
-&main_spi2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_spi2_pins_default>;
-	
-	SLB9670: SLB9670@0 {
-		compatible = "infineon,slb9670", "tis,tpm2-spi", "tcg,tpm_tis-spi";
-		reg = <0>;
-		#gpio-cells = <2>;
-		#interrupt-cells = <2>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&tpm_pins_default>;
-		
-		interrupt-parent = <&main_gpio0>;
-		interrupts = <66 IRQ_TYPE_EDGE_FALLING>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		spi-max-frequency = <43000000>;
-	};
-};
-
-&main_i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c1_pins_default>;
-	clock-frequency = <400000>;
-
-	rtc@52 {
-		compatible = "microcrystal,rv3028";
-		reg = <0x52>;
-		// The backup goldcap is supplied with a higher voltage (+5V)
-		// then the RTC (+3,3) itself. It requires a special setup
-		// to avoid hardware failure.
-		use-goldcap-with-higher-voltage;
-	};
-
-	rs485: rs485@71 {
-		compatible = "nxp,pca9538";
-		reg = <0x71>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		gpio-line-names = "RS.TERM-EN", "RS.SLR",
-				  "+5V0-FB-ENA", "MP200",
-				  "BIAS.EN", "BIAS.HIR",
-				  "MP201", "MP202";
-
-		rs485-5v {
-			gpio-hog;
-			gpios = <2 GPIO_ACTIVE_HIGH>;
-			output-high;
-		};
-	};
-};
-
-&sdhci0 {
-	/* eMMC */
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_mmc0_pins_default>;
-	ti,driver-strength-ohm = <33>;
-	disable-wp;
-};
-
-&sdhci1 {
-	/* SD */
-	vmmc-supply = <&vdd_mmc1>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_mmc1_pins_default>;
-	ti,driver-strength-ohm = <33>;
-	cap-sd-highspeed;
-	no-1-8-v;
-};
-
-&cpsw3g {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_mdio1_pins_default
-		     &main_rgmii1_pins_default
-		     &main_rgmii2_pins_default>;
-};
-
-&cpsw_port1 {
-	phy-mode = "rgmii-rxid";
-	phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw_port2 {
-	phy-mode = "rgmii-rxid";
-	phy-handle = <&cpsw3g_phy1>;
-};
-
-&cpsw3g_mdio {
-        reset-gpios = <&main_gpio1 9 GPIO_ACTIVE_LOW>;
-        reset-delay-us = <10>;
-        reset-post-delay-us = <10000>;
-
-	cpsw3g_phy0: ethernet-phy@0 {
-		// ADIN1300
-		compatible = "ethernet-phy-id0283.bc30";
-
-		reg = <0>;
-		adi,rx-internal-delay-ps = <2000>;
-	};
-
-	cpsw3g_phy1: ethernet-phy@1 {
-		// ADIN1300
-		compatible = "ethernet-phy-id0283.bc30";
-
-		reg = <1>;
-		adi,rx-internal-delay-ps = <2000>;
-	};
-};
-
-&mailbox0_cluster0 {
-	mbox_m4_0: mbox-m4-0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-};
-
-/*
- * AM6232 does not have main_rti2, main_rti3, and main_rti15
- * https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1218039/am623-stuck-in-sd-card-after-boot-up
- */
-&main_rti2 {    // watchdog@e020000
-    status = "disabled";
-};
-
-&main_rti3 {    // watchdog@e030000
-    status = "disabled";
-};
-
-&main_rti15 {   // watchdog@e0f0000
-    status = "disabled";
-};
-
-&usbss0 {
-	ti,vbus-divider;
-};
-
-&usb0 {
-	dr_mode = "peripheral";
-};

arch/arm64/configs/am6xxx_defconfig

@@ -131,6 +131,7 @@ CONFIG_BRIDGE_EBT_T_FILTER=m
 CONFIG_BRIDGE_EBT_T_NAT=m
 CONFIG_BRIDGE=y
 CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_NET_DSA=y
 CONFIG_VLAN_8021Q=m
 CONFIG_VLAN_8021Q_GVRP=y
 CONFIG_NET_SCHED=y
@@ -149,7 +150,6 @@ CONFIG_NET_ACT_POLICE=m
 CONFIG_NET_ACT_GACT=m
 CONFIG_NET_ACT_MIRRED=m
 CONFIG_NET_ACT_GATE=m
-CONFIG_NET_SWITCHDEV=y
 CONFIG_CGROUP_NET_PRIO=y
 # CONFIG_WIRELESS is not set
 CONFIG_PAGE_POOL_STATS=y
@@ -161,10 +161,12 @@ CONFIG_VEXPRESS_CONFIG=y
 CONFIG_MHI_BUS=m
 CONFIG_ARM_SCMI_PROTOCOL=y
 CONFIG_ARM_SCPI_PROTOCOL=y
-CONFIG_MTD=m
+CONFIG_MTD=y
+CONFIG_MTD_OF_PARTS=m
 CONFIG_MTD_PHYSMAP=m
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_PLATRAM=m
+CONFIG_MTD_SPI_NOR=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=m
 CONFIG_SRAM=y
@@ -172,6 +174,7 @@ CONFIG_SRAM=y
 CONFIG_EEPROM_AT24=y
 CONFIG_SCSI=y
 # CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_SCSI_SAS_LIBSAS=y
 # CONFIG_SCSI_LOWLEVEL is not set
@@ -182,6 +185,8 @@ CONFIG_IPVLAN=m
 CONFIG_VXLAN=m
 CONFIG_TUN=y
 CONFIG_VETH=m
+CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=y
+CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=y
 # CONFIG_NET_VENDOR_ALACRITECH is not set
 # CONFIG_NET_VENDOR_AMAZON is not set
 # CONFIG_NET_VENDOR_AMD is not set
@@ -252,6 +257,7 @@ CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_OMAP=y
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_SERIAL_OMAP_MODBUS is not set
+CONFIG_RPMSG_TTY=y
 CONFIG_HW_RANDOM=y
 CONFIG_TCG_TPM=y
 CONFIG_TCG_TIS=y
@@ -263,7 +269,6 @@ CONFIG_I2C_MUX_PCA954x=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
 CONFIG_I2C_OMAP=y
 CONFIG_SPI=y
-# CONFIG_SPI_MEM is not set
 CONFIG_SPI_CADENCE_QUADSPI=y
 CONFIG_SPI_DESIGNWARE=y
 CONFIG_SPI_OMAP24XX=y
@@ -297,14 +302,20 @@ CONFIG_REGULATOR_TPS65219=y
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 # CONFIG_USB_DEFAULT_PERSIST is not set
+CONFIG_USB_OTG=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_MUSB_HDRC=y
 CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
 # CONFIG_USB_DWC3_KEYSTONE is not set
 CONFIG_NOP_USB_XCEIV=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=32
 CONFIG_USB_CONFIGFS=m
 CONFIG_USB_CONFIGFS_SERIAL=y
 CONFIG_USB_CONFIGFS_ACM=y
@@ -317,6 +328,7 @@ CONFIG_USB_CONFIGFS_EEM=y
 CONFIG_USB_CONFIGFS_MASS_STORAGE=y
 CONFIG_USB_CONFIGFS_F_FS=y
 CONFIG_USB_FUNCTIONFS=m
+CONFIG_USB_MASS_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=32
 CONFIG_MMC_ARMMMCI=y
@@ -326,7 +338,10 @@ CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_AM654=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CLASS_MULTICOLOR=y
+CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_PCA955X=y
+CONFIG_LEDS_WS2812B=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
@@ -356,6 +371,14 @@ CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
 CONFIG_IOMMU_IO_PGTABLE_DART=y
 CONFIG_ARM_SMMU=y
 CONFIG_ARM_SMMU_V3=y
+CONFIG_REMOTEPROC=y
+CONFIG_REMOTEPROC_CDEV=y
+CONFIG_TI_K3_DSP_REMOTEPROC=y
+CONFIG_TI_K3_M4_REMOTEPROC=y
+CONFIG_TI_K3_R5_REMOTEPROC=y
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_CTRL=y
+CONFIG_RPMSG_VIRTIO=y
 CONFIG_SOC_BRCMSTB=y
 CONFIG_TI_SCI_PM_DOMAINS=y
 CONFIG_PM_DEVFREQ=y
@@ -387,7 +410,6 @@ CONFIG_NTFS3_FS=m
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_HUGETLBFS=y
-CONFIG_CONFIGFS_FS=y
 CONFIG_SQUASHFS=y
 CONFIG_PSTORE=y
 CONFIG_PSTORE_CONSOLE=y
@@ -436,8 +458,6 @@ CONFIG_SYSTEM_TRUSTED_KEYRING=y
 CONFIG_PACKING=y
 CONFIG_INDIRECT_PIO=y
 CONFIG_CRC_CCITT=m
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC64_ROCKSOFT=y
 CONFIG_CRC_ITU_T=y
 CONFIG_CRC7=y
 CONFIG_CRC8=y
@@ -450,4 +470,6 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
 CONFIG_FUNCTION_TRACER=y
+CONFIG_SAMPLES=y
+CONFIG_SAMPLE_RPMSG_CLIENT=m
 CONFIG_MEMTEST=y

drivers/leds/rgb/Kconfig

@@ -51,4 +51,15 @@ config LEDS_MT6370_RGB
 	  This driver can also be built as a module. If so, the module
 	  will be called "leds-mt6370-rgb".
 
+config LEDS_WS2812B
+	tristate "SPI driven WS2812B RGB LED support"
+	depends on OF
+	depends on SPI
+	help
+	  This option enables support for driving daisy-chained WS2812B RGB
+	  LED chips using SPI bus. This driver simulates the single-wire
+	  protocol by sending bits over the SPI MOSI pin. For this to work,
+	  the SPI frequency should be 2.105MHz~2.85MHz and the controller
+	  needs to transfer all the bytes continuously.
+
 endif # LEDS_CLASS_MULTICOLOR

drivers/leds/rgb/Makefile

@@ -4,3 +4,4 @@ obj-$(CONFIG_LEDS_GROUP_MULTICOLOR)	+= leds-group-multicolor.o
 obj-$(CONFIG_LEDS_PWM_MULTICOLOR)	+= leds-pwm-multicolor.o
 obj-$(CONFIG_LEDS_QCOM_LPG)		+= leds-qcom-lpg.o
 obj-$(CONFIG_LEDS_MT6370_RGB)		+= leds-mt6370-rgb.o
+obj-$(CONFIG_LEDS_WS2812B)		+= leds-ws2812b.o

drivers/leds/rgb/leds-ws2812b.c

@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * WorldSemi WS2812B individually-addressable LED driver using SPI
+ *
+ * Copyright 2022 Chuanhong Guo <gch981213@gmail.com>
+ *
+ * This driver simulates WS2812B protocol using SPI MOSI pin. A one pulse
+ * is transferred as 3'b110 and a zero pulse is 3'b100. For this driver to
+ * work properly, the SPI frequency should be 2.105MHz~2.85MHz and it needs
+ * to transfer all the bytes continuously.
+ */
+
+#include <linux/led-class-multicolor.h>
+#include <linux/leds.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/property.h>
+#include <linux/spi/spi.h>
+#include <linux/mutex.h>
+
+/*
+ * 3 spi bytes per color + 1 padding
+ * to fit the 32bit spi tx register alignment
+ * where 24bit transfer is used.
+ */
+#define WS2812B_BYTES_PER_COLOR 4
+#define WS2812B_NUM_COLORS 3
+
+/*
+ * A continuous 0 for 250us+ as the 'reset' signal.
+ * The number of bytes has to be 32bit-aligned.
+ */
+#define WS2812B_RESET_LEN 116
+
+struct ws2812b_led {
+	struct led_classdev_mc mc_cdev;
+	struct mc_subled subled[WS2812B_NUM_COLORS];
+	int cascade;
+};
+
+struct ws2812b_priv {
+	struct led_classdev ldev;
+	struct spi_device *spi;
+	struct mutex mutex;
+	int num_leds;
+	size_t data_len;
+	u8 *data_buf;
+	struct ws2812b_led leds[];
+};
+
+/**
+ * ws2812b_set_byte - convert a byte of data to 3-byte SPI data for pulses
+ * @priv: pointer to the private data structure
+ * @offset: offset of the target byte in the data stream
+ * @val: 1-byte data to be set
+ *
+ * WS2812B receives a stream of bytes from DI, takes the first 3 byte as LED
+ * brightness and pases the rest to the next LED through the DO pin.
+ * This function assembles a single byte of data to the LED:
+ * A bit is represented with a pulse of specific length. A long pulse is a 1
+ * and a short pulse is a 0.
+ * SPI transfers data continuously, MSB first. We can send 3'b100 to create a
+ * 0 pulse and 3'b110 for a 1 pulse. In this way, a byte of data takes up 3
+ * bytes in a SPI transfer:
+ *  1x0 1x0 1x0 1x0 1x0 1x0 1x0 1x0
+ * Let's rearrange it in 8 bits:
+ *  1x01x01x 01x01x01 x01x01x0
+ * The higher 3 bits, middle 2 bits and lower 3 bits are represented with the
+ * 1st, 2nd and 3rd byte in the SPI transfer respectively.
+ * There are only 8 combinations for 3 bits and 4 for 2 bits, so we can create
+ * a lookup table for the 3 bytes.
+ * e.g. For 0x6b -> 2'b01101011:
+ *  Bit 7-5: 3'b011 -> 10011011 -> 0x9b
+ *  Bit 4-3: 2'b01  -> 01001101 -> 0x4d
+ *  Bit 2-0: 3'b011 -> 00110110 -> 0x36
+ */
+static void ws2812b_set_byte(struct ws2812b_priv *priv, size_t offset, u8 val)
+{
+	/* The lookup table for Bit 7-5 4-3 2-0 */
+	const u8 h3b[] = { 0x92, 0x93, 0x9a, 0x9b, 0xd2, 0xd3, 0xda, 0xdb };
+	const u8 m2b[] = { 0x49, 0x4d, 0x69, 0x6d };
+	const u8 l3b[] = { 0x24, 0x26, 0x34, 0x36, 0xa4, 0xa6, 0xb4, 0xb6 };
+	u8 *p = priv->data_buf + WS2812B_RESET_LEN + (offset * WS2812B_BYTES_PER_COLOR);
+
+	p[3] = 0xff; /* extra byte to fit the 32bit alignment */
+	p[2] = h3b[val >> 5]; /* Bit 7-5 */
+	p[1] = m2b[(val >> 3) & 0x3]; /* Bit 4-3 */
+	p[0] = l3b[val & 0x7]; /* Bit 2-0 */
+
+	pr_debug("%s:%d - var %d, offset %u, p[i] 0x%x 0x%x 0x%x 0x%x.",
+		__func__, __LINE__,
+		val, (u32) offset, p[0], p[1], p[2], p[3]);
+}
+
+static void ws2812b_setup_spi(struct ws2812b_priv *priv)
+{
+	/* As we send 3-byte spi data chunks to represent
+	 * one pulse byte it makes sense to increase word
+	 * size to 24 bit.
+	 */
+	priv->spi->bits_per_word = 24;
+
+	/* do the actual spi setup */
+	spi_setup(priv->spi);
+}
+
+static int ws2812b_set(struct led_classdev *cdev,
+		       enum led_brightness brightness)
+{
+	struct led_classdev_mc *mc_cdev = lcdev_to_mccdev(cdev);
+	struct ws2812b_led *led =
+		container_of(mc_cdev, struct ws2812b_led, mc_cdev);
+	struct ws2812b_priv *priv = dev_get_drvdata(cdev->dev->parent);
+	int ret;
+	int i;
+
+	led_mc_calc_color_components(mc_cdev, brightness);
+
+	pr_debug("%s:%d - brightness %d, led->cascade %d, subled[i].brightness %d %d %d priv->data_len %u.",
+		__func__, __LINE__,
+		brightness, led->cascade,
+		led->subled[0].brightness,
+		led->subled[1].brightness,
+		led->subled[2].brightness,
+		(u32) priv->data_len);
+
+	mutex_lock(&priv->mutex);
+	for (i = 0; i < WS2812B_NUM_COLORS; i++)
+		ws2812b_set_byte(priv, led->cascade * WS2812B_NUM_COLORS + i,
+				 led->subled[i].brightness);
+	ret = spi_write(priv->spi, priv->data_buf, priv->data_len);
+	mutex_unlock(&priv->mutex);
+
+	print_hex_dump_bytes("ws2812b_set:", DUMP_PREFIX_OFFSET,
+			     priv->data_buf, priv->data_len);
+
+	return ret;
+}
+
+static int ws2812b_probe(struct spi_device *spi)
+{
+	struct device *dev = &spi->dev;
+	int cur_led = 0;
+	struct ws2812b_priv *priv;
+	struct fwnode_handle *led_node;
+	int num_leds, i, cnt, ret;
+
+	num_leds = device_get_child_node_count(dev);
+
+	priv = devm_kzalloc(dev, struct_size(priv, leds, num_leds), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	priv->data_len =
+		num_leds * WS2812B_BYTES_PER_COLOR * WS2812B_NUM_COLORS +
+		WS2812B_RESET_LEN;
+	priv->data_buf = kzalloc(priv->data_len, GFP_KERNEL);
+	if (!priv->data_buf)
+		return -ENOMEM;
+
+	for (i = 0; i < num_leds * WS2812B_NUM_COLORS; i++)
+		ws2812b_set_byte(priv, i, 0);
+
+	mutex_init(&priv->mutex);
+	priv->num_leds = num_leds;
+	priv->spi = spi;
+
+	device_for_each_child_node(dev, led_node) {
+		struct led_init_data init_data = {
+			.fwnode = led_node,
+		};
+		/* WS2812B LEDs usually come with GRB color */
+		u32 color_idx[WS2812B_NUM_COLORS] = {
+			LED_COLOR_ID_GREEN,
+			LED_COLOR_ID_RED,
+			LED_COLOR_ID_BLUE,
+		};
+		u32 cascade;
+
+		ret = fwnode_property_read_u32(led_node, "reg", &cascade);
+		if (ret) {
+			dev_err(dev, "failed to obtain numerical LED index for %s",
+				fwnode_get_name(led_node));
+			goto ERR_UNREG_LEDS;
+		}
+		if (cascade >= num_leds) {
+			dev_err(dev, "LED index of %s is larger than the number of LEDs.",
+				fwnode_get_name(led_node));
+			ret = -EINVAL;
+			goto ERR_UNREG_LEDS;
+		}
+
+		cnt = fwnode_property_count_u32(led_node, "color-index");
+		if (cnt > 0 && cnt <= WS2812B_NUM_COLORS)
+			fwnode_property_read_u32_array(led_node, "color-index",
+						       color_idx, (size_t)cnt);
+
+		priv->leds[cur_led].mc_cdev.subled_info =
+			priv->leds[cur_led].subled;
+		priv->leds[cur_led].mc_cdev.num_colors = WS2812B_NUM_COLORS;
+		priv->leds[cur_led].mc_cdev.led_cdev.max_brightness = 255;
+		priv->leds[cur_led].mc_cdev.led_cdev.brightness_set_blocking = ws2812b_set;
+
+		for (i = 0; i < WS2812B_NUM_COLORS; i++) {
+			priv->leds[cur_led].subled[i].color_index = color_idx[i];
+			priv->leds[cur_led].subled[i].intensity = 255;
+		}
+
+		priv->leds[cur_led].cascade = cascade;
+
+		ret = led_classdev_multicolor_register_ext(
+			dev, &priv->leds[cur_led].mc_cdev, &init_data);
+		if (ret) {
+			dev_err(dev, "registration of %s failed.",
+				fwnode_get_name(led_node));
+			goto ERR_UNREG_LEDS;
+		}
+		cur_led++;
+	}
+
+	spi_set_drvdata(spi, priv);
+
+	ws2812b_setup_spi(priv);
+
+	return 0;
+ERR_UNREG_LEDS:
+	for (; cur_led >= 0; cur_led--)
+		led_classdev_multicolor_unregister(&priv->leds[cur_led].mc_cdev);
+	mutex_destroy(&priv->mutex);
+	kfree(priv->data_buf);
+	return ret;
+}
+
+static void ws2812b_remove(struct spi_device *spi)
+{
+	struct ws2812b_priv *priv = spi_get_drvdata(spi);
+	int cur_led;
+
+	for (cur_led = priv->num_leds - 1; cur_led >= 0; cur_led--)
+		led_classdev_multicolor_unregister(&priv->leds[cur_led].mc_cdev);
+	kfree(priv->data_buf);
+	mutex_destroy(&priv->mutex);
+}
+
+static const struct spi_device_id ws2812b_spi_ids[] = {
+	{ "ws2812b" },
+	{},
+};
+MODULE_DEVICE_TABLE(spi, ws2812b_spi_ids);
+
+static const struct of_device_id ws2812b_dt_ids[] = {
+	{ .compatible = "worldsemi,ws2812b" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, ws2812b_dt_ids);
+
+static struct spi_driver ws2812b_driver = {
+	.probe		= ws2812b_probe,
+	.remove		= ws2812b_remove,
+	.id_table	= ws2812b_spi_ids,
+	.driver = {
+		.name		= KBUILD_MODNAME,
+		.of_match_table	= ws2812b_dt_ids,
+	},
+};
+
+module_spi_driver(ws2812b_driver);
+
+MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
+MODULE_DESCRIPTION("WS2812B LED driver using SPI");
+MODULE_LICENSE("GPL");

drivers/mtd/spi-nor/core.c

@@ -2003,6 +2003,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = {
 	&spi_nor_eon,
 	&spi_nor_esmt,
 	&spi_nor_everspin,
+	&spi_mram_everspin,
 	&spi_nor_fujitsu,
 	&spi_nor_gigadevice,
 	&spi_nor_intel,

drivers/mtd/spi-nor/core.h

@@ -635,6 +635,7 @@ extern const struct spi_nor_manufacturer spi_nor_catalyst;
 extern const struct spi_nor_manufacturer spi_nor_eon;
 extern const struct spi_nor_manufacturer spi_nor_esmt;
 extern const struct spi_nor_manufacturer spi_nor_everspin;
+extern const struct spi_nor_manufacturer spi_mram_everspin;
 extern const struct spi_nor_manufacturer spi_nor_fujitsu;
 extern const struct spi_nor_manufacturer spi_nor_gigadevice;
 extern const struct spi_nor_manufacturer spi_nor_intel;

drivers/mtd/spi-nor/everspin.c

@@ -8,6 +8,248 @@
 
 #include "core.h"
 
+/* flash_info mfr_flag. Used to read proprietary FSR register. */
+#define USE_FSR		BIT(0)
+
+#define SPINOR_OP_RDFSR		0x70	/* Read flag status register */
+#define SPINOR_OP_CLFSR		0x50	/* Clear flag status register */
+#define SPINOR_OP_MT_DTR_RD	0xfd	/* Fast Read opcode in DTR mode */
+#define SPINOR_OP_MT_RD_ANY_REG	0x85	/* Read volatile register */
+#define SPINOR_OP_MT_WR_ANY_REG	0x81	/* Write volatile register */
+#define SPINOR_REG_MT_CFR0V	0x00	/* For setting octal DTR mode */
+#define SPINOR_REG_MT_CFR1V	0x01	/* For setting dummy cycles */
+#define SPINOR_REG_MT_CFR1V_DEF	0x1f	/* Default dummy cycles */
+#define SPINOR_MT_OCT_DTR	0xe7	/* Enable Octal DTR. */
+#define SPINOR_MT_EXSPI		0xff	/* Enable Extended SPI (default) */
+
+/* Flag Status Register bits */
+#define FSR_READY		BIT(7)	/* Device status, 0 = Busy, 1 = Ready */
+#define FSR_E_ERR		BIT(5)	/* Erase operation status */
+#define FSR_P_ERR		BIT(4)	/* Program operation status */
+#define FSR_CRC_ERR		BIT(3)	/* CRC Error status */
+#define FSR_PT_ERR		BIT(1)	/* Protection error bit */
+#define FSR_4B_ADDR		BIT(0)	/* 3 or 4 Byte Addressing Mode */
+
+
+/* Everspin SPI NOR flash operations. */
+#define EVERSPIN_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf)		\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0),		\
+		   SPI_MEM_OP_ADDR(naddr, addr, 0),			\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
+
+#define EVERSPIN_RDFSR_OP(buf)						\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),			\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_IN(1, buf, 0))
+
+#define EVERSPIN_CLFSR_OP						\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0),			\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
+
+static int everspin_nor_octal_dtr_en(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	u8 *buf = nor->bouncebuf;
+	int ret;
+
+	/* Use 8 dummy cycles for memory array reads. */
+	*buf = 8;
+	op = (struct spi_mem_op)
+		EVERSPIN_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR1V, 1, buf);
+	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+	if (ret)
+		return ret;
+
+	buf[0] = SPINOR_MT_OCT_DTR;
+	op = (struct spi_mem_op)
+		EVERSPIN_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 1, buf);
+	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+	if (ret)
+		return ret;
+
+	/* Read flash ID to make sure the switch was successful. */
+	ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR);
+	if (ret) {
+		dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
+		return ret;
+	}
+
+	if (memcmp(buf, nor->info->id, nor->info->id_len))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int everspin_nor_octal_dtr_dis(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	u8 *buf = nor->bouncebuf;
+	int ret;
+
+	/*
+	 * The register is 1-byte wide, but 1-byte transactions are not allowed
+	 * in 8D-8D-8D mode. The next register is the dummy cycle configuration
+	 * register. Since the transaction needs to be at least 2 bytes wide,
+	 * set the next register to its default value. This also makes sense
+	 * because the value was changed when enabling 8D-8D-8D mode, it should
+	 * be reset when disabling.
+	 */
+	buf[0] = SPINOR_MT_EXSPI;
+	buf[1] = SPINOR_REG_MT_CFR1V_DEF;
+	op = (struct spi_mem_op)
+		EVERSPIN_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 2, buf);
+	ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
+	if (ret)
+		return ret;
+
+	/* Read flash ID to make sure the switch was successful. */
+	ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
+	if (ret) {
+		dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);
+		return ret;
+	}
+
+	if (memcmp(buf, nor->info->id, nor->info->id_len))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int everspin_nor_octal_dtr(struct spi_nor *nor, bool enable)
+{
+	return enable ? everspin_nor_octal_dtr_en(nor) :
+			everspin_nor_octal_dtr_dis(nor);
+}
+
+
+/**
+ * everspin_nor_read_fsr() - Read the Flag Status Register.
+ * @nor:	pointer to 'struct spi_nor'
+ * @fsr:	pointer to a DMA-able buffer where the value of the
+ *              Flag Status Register will be written. Should be at least 2
+ *              bytes.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int everspin_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
+{
+	int ret;
+
+	if (nor->spimem) {
+		struct spi_mem_op op = EVERSPIN_RDFSR_OP(fsr);
+
+		if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
+			op.addr.nbytes = nor->params->rdsr_addr_nbytes;
+			op.dummy.nbytes = nor->params->rdsr_dummy;
+			/*
+			 * We don't want to read only one byte in DTR mode. So,
+			 * read 2 and then discard the second byte.
+			 */
+			op.data.nbytes = 2;
+		}
+
+		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+		ret = spi_mem_exec_op(nor->spimem, &op);
+	} else {
+		ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr,
+						      1);
+	}
+
+	if (ret)
+		dev_dbg(nor->dev, "error %d reading FSR\n", ret);
+
+	return ret;
+}
+
+/**
+ * everspin_nor_clear_fsr() - Clear the Flag Status Register.
+ * @nor:	pointer to 'struct spi_nor'.
+ */
+static void everspin_nor_clear_fsr(struct spi_nor *nor)
+{
+	int ret;
+
+	if (nor->spimem) {
+		struct spi_mem_op op = EVERSPIN_CLFSR_OP;
+
+		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+		ret = spi_mem_exec_op(nor->spimem, &op);
+	} else {
+		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR,
+						       NULL, 0);
+	}
+
+	if (ret)
+		dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
+}
+
+/**
+ * everspin_nor_ready() - Query the Status Register as well as the Flag Status
+ * Register to see if the flash is ready for new commands. If there are any
+ * errors in the FSR clear them.
+ * @nor:	pointer to 'struct spi_nor'.
+ *
+ * Return: 1 if ready, 0 if not ready, -errno on errors.
+ */
+static int everspin_nor_ready(struct spi_nor *nor)
+{
+	int sr_ready, ret;
+
+	sr_ready = spi_nor_sr_ready(nor);
+	if (sr_ready < 0)
+		return sr_ready;
+
+	ret = everspin_nor_read_fsr(nor, nor->bouncebuf);
+	if (ret) {
+		/*
+		 * Some controllers, such as Intel SPI, do not support low
+		 * level operations such as reading the flag status
+		 * register. They only expose small amount of high level
+		 * operations to the software. If this is the case we use
+		 * only the status register value.
+		 */
+		return ret == -EOPNOTSUPP ? sr_ready : ret;
+	}
+
+	if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
+		if (nor->bouncebuf[0] & FSR_E_ERR)
+			dev_err(nor->dev, "Erase operation failed.\n");
+		else
+			dev_err(nor->dev, "Program operation failed.\n");
+
+		if (nor->bouncebuf[0] & FSR_PT_ERR)
+			dev_err(nor->dev,
+				"Attempted to modify a protected sector.\n");
+
+		if (nor->bouncebuf[0] & FSR_CRC_ERR)
+			dev_err(nor->dev,
+				"Computed CRC did not match the user provided CRC code.\n");
+
+		everspin_nor_clear_fsr(nor);
+
+		/*
+		 * WEL bit remains set to one when an erase or page program
+		 * error occurs. Issue a Write Disable command to protect
+		 * against inadvertent writes that can possibly corrupt the
+		 * contents of the memory.
+		 */
+		ret = spi_nor_write_disable(nor);
+		if (ret)
+			return ret;
+
+		return -EIO;
+	}
+
+	return sr_ready && !!(nor->bouncebuf[0] & FSR_READY);
+}
+
 static const struct flash_info everspin_nor_parts[] = {
 	/* Everspin */
 	{ "mr25h128", CAT25_INFO(16 * 1024, 1, 256, 2) },
@@ -16,8 +258,90 @@ static const struct flash_info everspin_nor_parts[] = {
 	{ "mr25h40",  CAT25_INFO(512 * 1024, 1, 256, 3) },
 };
 
+static const struct flash_info everspin_mram_parts[] = {
+	/* Everspin */
+	{ "em256lx",  INFO(0x6bbb19, 0, 32 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em128lx",  INFO(0x6bbb18, 0, 16 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em064lx",  INFO(0x6bbb17, 0, 8 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em032lx",  INFO(0x6bbb16, 0, 4 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em016lx",  INFO(0x6bbb15, 0, 2 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em008lx",  INFO(0x6bbb14, 0, 1 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+};
+
+static void everspin_mram_default_init(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	u8 *buf = nor->bouncebuf;
+
+	/* Use 8 dummy cycles for memory array reads. */
+	*buf = 8;
+	op = (struct spi_mem_op)
+		EVERSPIN_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf);
+	spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+
+	nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
+	nor->params->rdsr_dummy = 8;
+	nor->params->rdsr_addr_nbytes = 0;
+	// nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
+	nor->params->addr_nbytes = 4;
+	nor->params->set_octal_dtr = everspin_nor_octal_dtr;
+
+	if (nor->info->mfr_flags & USE_FSR)
+		nor->params->ready = everspin_nor_ready;
+
+	/* Status Register has only 8 Bits */
+	nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+
+	/*
+	 * The BFPT quad enable field is set to a reserved value so the quad
+	 * enable function is ignored by spi_nor_parse_bfpt(). Make sure we
+	 * disable it.
+	 */
+	nor->params->quad_enable = NULL;
+}
+
+static int everspin_mram_late_init(struct spi_nor *nor)
+{
+	/* Set Read and Write settings. */
+	nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8;
+	spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_1_8_8],
+				  0, 8, SPINOR_OP_READ_1_8_8,
+				  SNOR_PROTO_1_8_8);
+
+	nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_1_8_8;
+	spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_1_8_8],
+				SPINOR_OP_PP_1_8_8,
+				SNOR_PROTO_1_8_8);
+
+	return 0;
+}
+
+static const struct spi_nor_fixups everspin_mram_fixups = {
+	.default_init = everspin_mram_default_init,
+	.late_init = everspin_mram_late_init,
+};
+
 const struct spi_nor_manufacturer spi_nor_everspin = {
 	.name = "everspin",
 	.parts = everspin_nor_parts,
 	.nparts = ARRAY_SIZE(everspin_nor_parts),
 };
+
+const struct spi_nor_manufacturer spi_mram_everspin = {
+	.name = "everspin_mram",
+	.parts = everspin_mram_parts,
+	.nparts = ARRAY_SIZE(everspin_mram_parts),
+	.fixups = &everspin_mram_fixups,
+};

drivers/net/dsa/microchip/ksz9477.c

@@ -174,6 +174,7 @@ int ksz9477_reset_switch(struct ksz_device *dev)
 			   SPI_AUTO_EDGE_DETECTION, 0);
 
 	/* default configuration */
+	/* TWx: REG_SW_LUE_CTRL_1 = Switch Lookup Engine Control 1 Register */
 	ksz_write8(dev, REG_SW_LUE_CTRL_1,
 		   SW_AGING_ENABLE | SW_LINK_AUTO_AGING | SW_SRC_ADDR_FILTER);
 
@@ -195,6 +196,62 @@ int ksz9477_reset_switch(struct ksz_device *dev)
 		data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ;
 	ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8);
 
+	{
+		u16 data16;
+
+		/* REGS
+		 *
+		 * Write MMD - Device Address 2h, Register 00h = 0010h to enable single-LED mode.
+		 *
+		 * REG_PORT_PHY_MMD_SETUP      - Write the PHY MMD Setup Register with 0002h
+		 * REG_PORT_PHY_MMD_INDEX_DATA - Write the PHY MMD Data Register with 0000h
+		 *			       - Write the PHY MMD Setup Register with 4002h
+		 *			       - Write the PHY MMD Data Register with 0010h
+		 *
+		 *
+		 */
+
+		/* WRITE */
+		for (int i = 1; i <= 5; i++) {
+
+			/* skip EM port 3(4) */
+			if (i == 4)
+				continue;
+
+			/* Read <MMD LED Mode Register> for Port i */
+			ksz_write16(dev, REG_PORT_PHY_MMD_SETUP |
+				    (i << 12), 0x0002);
+			ksz_write16(dev, REG_PORT_PHY_MMD_INDEX_DATA |
+				    (i << 12), 0x0000);
+			ksz_write16(dev, REG_PORT_PHY_MMD_SETUP |
+				    (i << 12), 0x4002);
+			ksz_write16(dev, REG_PORT_PHY_MMD_INDEX_DATA |
+				    (i << 12), 0x0011);
+
+			/* Due to Errata Module 19 this workaround is needed to
+			 * enable single-led mode. It has also to be a 32bit
+			 * write.
+			 */
+			ksz_write32(dev, REG_PORT_PHY_DIGITAL_DEBUG_3 |
+				    (i << 12), 0xfa000300);
+
+			pr_info("TWx %s:%d - Port %d: Wrote MMD LED Mode Register: 0x%x\n.",
+				__func__, __LINE__, i, 0x0011);
+		}
+
+		/* READ */
+		for (int i = 1; i <= 5; i++) {
+			/* Read <MMD LED Mode Register> for Port i */
+			ksz_write16(dev, REG_PORT_PHY_MMD_SETUP | (i << 12), 0x0002);
+			ksz_write16(dev, REG_PORT_PHY_MMD_INDEX_DATA | (i << 12), 0x0000);
+			ksz_write16(dev, REG_PORT_PHY_MMD_SETUP | (i << 12), 0x4002);
+			ksz_read16(dev, REG_PORT_PHY_MMD_INDEX_DATA | (i << 12), &data16);
+
+			pr_info("TWx %s:%d - Port %d: MMD LED Mode Register: 0x%x\n.",
+				__func__, __LINE__, i, data16);
+		}
+	}
+
 	return 0;
 }
 

drivers/remoteproc/Kconfig

@@ -339,6 +339,19 @@ config TI_K3_DSP_REMOTEPROC
 	  It's safe to say N here if you're not interested in utilizing
 	  the DSP slave processors.
 
+config TI_K3_M4_REMOTEPROC
+	tristate "TI K3 M4 remoteproc support"
+	depends on ARCH_K3 || COMPILE_TEST
+	select MAILBOX
+	select OMAP2PLUS_MBOX
+	help
+	  Say m here to support TI's M4 remote processor subsystems
+	  on various TI K3 family of SoCs through the remote processor
+	  framework.
+
+	  It's safe to say N here if you're not interested in utilizing
+	  a remote processor.
+
 config TI_K3_R5_REMOTEPROC
 	tristate "TI K3 R5 remoteproc support"
 	depends on ARCH_K3

drivers/remoteproc/Makefile

@@ -37,5 +37,6 @@ obj-$(CONFIG_ST_REMOTEPROC)		+= st_remoteproc.o
 obj-$(CONFIG_ST_SLIM_REMOTEPROC)	+= st_slim_rproc.o
 obj-$(CONFIG_STM32_RPROC)		+= stm32_rproc.o
 obj-$(CONFIG_TI_K3_DSP_REMOTEPROC)	+= ti_k3_dsp_remoteproc.o
+obj-$(CONFIG_TI_K3_M4_REMOTEPROC)	+= ti_k3_m4_remoteproc.o
 obj-$(CONFIG_TI_K3_R5_REMOTEPROC)	+= ti_k3_r5_remoteproc.o
 obj-$(CONFIG_XLNX_R5_REMOTEPROC)	+= xlnx_r5_remoteproc.o

drivers/remoteproc/omap_remoteproc.h

@@ -59,7 +59,9 @@ enum omap_rp_mbox_messages {
 	RP_MBOX_SUSPEND_SYSTEM	= 0xFFFFFF11,
 	RP_MBOX_SUSPEND_ACK	= 0xFFFFFF12,
 	RP_MBOX_SUSPEND_CANCEL	= 0xFFFFFF13,
-	RP_MBOX_END_MSG		= 0xFFFFFF14,
+	RP_MBOX_SHUTDOWN        = 0xFFFFFF14,
+	RP_MBOX_SHUTDOWN_ACK    = 0xFFFFFF15,
+	RP_MBOX_END_MSG		= 0xFFFFFF16,
 };
 
 #endif /* _OMAP_RPMSG_H */

drivers/spi/spi-cadence-quadspi.c

@@ -29,6 +29,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/spi-mem.h>
 #include <linux/timer.h>
+#include <linux/string.h>
 
 #define CQSPI_NAME			"cadence-qspi"
 #define CQSPI_MAX_CHIPSELECT		16
@@ -1276,6 +1277,10 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
 	 */
 	if (!op->cmd.dtr && cqspi->use_direct_mode &&
 	    cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {
+		pr_info("TWx: %s:%d - Writing <%lu> bytes with offset <%lld> to ahb_base <%p>\n",
+			__func__, __LINE__, len, to, cqspi->ahb_base + to);
+		print_hex_dump(KERN_INFO, "TWx write buf:", DUMP_PREFIX_OFFSET,
+			       16, 1, buf, len, true);
 		memcpy_toio(cqspi->ahb_base + to, buf, len);
 		return cqspi_wait_idle(cqspi);
 	}
@@ -1701,6 +1706,10 @@ static int cqspi_probe(struct platform_device *pdev)
 	struct cqspi_st *cqspi;
 	int ret;
 	int irq;
+	const u_char *test_buf = "TWX-111-000";
+	loff_t to;
+
+	pr_info("TWx: %s:%d.\n", __func__, __LINE__);
 
 	host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi));
 	if (!host) {
@@ -1752,6 +1761,20 @@ static int cqspi_probe(struct platform_device *pdev)
 	cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
 	cqspi->ahb_size = resource_size(res_ahb);
 
+	pr_info("TWx: %s:%d ahb_base %p.\n",
+		__func__, __LINE__,
+		cqspi->ahb_base);
+
+	pr_info("TWx: %s:%d mmap_phys_base %pad\n",
+		__func__, __LINE__,
+		&cqspi->mmap_phys_base);
+
+	/* print_hex_dump_bytes("TWx 64 byte ahb_base dump:", DUMP_PREFIX_OFFSET,
+			     cqspi->ahb_base, 64); */
+
+	print_hex_dump(KERN_INFO, "TWx ahb_base:", DUMP_PREFIX_OFFSET,
+		       16, 1, cqspi->ahb_base, 64, true);
+
 	init_completion(&cqspi->transfer_complete);
 
 	/* Obtain IRQ line. */
@@ -1874,7 +1897,27 @@ static int cqspi_probe(struct platform_device *pdev)
 		goto probe_setup_failed;
 	}
 
+	pr_info("TWx: %s:%d cqspi->use_direct_mode (%s).\n",
+		__func__, __LINE__,
+		cqspi->use_direct_mode ? "enabled" : "disabled");
+	pr_info("TWx: %s:%d cqspi->use_direct_mode_wr (%s).\n",
+		__func__, __LINE__,
+		cqspi->use_direct_mode_wr ? "enabled" : "disabled");
+
+	to = 5;
+
+	pr_info("TWx: %s:%d - Writing %s, size %lu to ahb_base %lld\n",
+		__func__, __LINE__,
+		test_buf, strlen(test_buf), to);
+
+	memcpy_toio(cqspi->ahb_base + to, test_buf, strlen(test_buf));
+	cqspi_wait_idle(cqspi);
+
+	print_hex_dump(KERN_INFO, "TWx ahb_base:", DUMP_PREFIX_OFFSET,
+		       16, 1, cqspi->ahb_base, 64, true);
+
 	return 0;
+
 probe_setup_failed:
 	cqspi_controller_enable(cqspi, 0);
 probe_reset_failed:

drivers/spi/spi-kbus.c

@@ -52,7 +52,7 @@ static struct cdev kbus_cdev;
 /* sysfs */
 extern struct class *wsysinit_sysfs_class;
 extern struct device *wsysinit_sysfs_device;
-static struct device *kbus_device;
+static struct device *kbus_device = NULL;
 
 int kbus_wait_for_gpio(int gpio)
 {
@@ -185,19 +185,26 @@ static struct task_struct *find_dma_task(void)
 
 void kbus_boost_dma_task(u8 enable)
 {
-	struct kbus_drv_data *kdrvdata = dev_get_drvdata(kbus_device);
-	struct sched_param boost_param = {
-		.sched_priority = enable ? kdrvdata->kbus_dma_boost_prio :
-					   kdrvdata->kbus_dma_normal_prio
-	};
+	struct kbus_drv_data *kdrvdata = NULL;
+	struct sched_param boost_param;
 
-	if (kdrvdata->dma_task) {
-		if ((enable && !kdrvdata->kbus_dma_boost_en) ||
-		    (!enable && kdrvdata->kbus_dma_boost_en)) {
-			kdrvdata->kbus_dma_boost_en =
-				!kdrvdata->kbus_dma_boost_en;
-			sched_setscheduler(kdrvdata->dma_task, SCHED_FIFO,
-					   &boost_param);
+	if (kbus_device) {
+		kdrvdata = dev_get_drvdata(kbus_device);
+
+		if (kdrvdata) {
+			boost_param.sched_priority = enable ?
+				kdrvdata->kbus_dma_boost_prio :
+				kdrvdata->kbus_dma_normal_prio;
+
+			if (kdrvdata->dma_task) {
+				if ((enable && !kdrvdata->kbus_dma_boost_en) ||
+				    (!enable && kdrvdata->kbus_dma_boost_en)) {
+					kdrvdata->kbus_dma_boost_en =
+						!kdrvdata->kbus_dma_boost_en;
+					sched_setscheduler(kdrvdata->dma_task, SCHED_FIFO,
+							   &boost_param);
+				}
+			}
 		}
 	}
 }

drivers/spi/spi-omap2-mcspi.c

@@ -657,9 +657,11 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 	int			wait_res;
 
 #ifdef CONFIG_SPI_KBUS_OMAP_EXTENSION
-	trace_pxc_kbus(__func__, "enter");
+	if (spi->dev.driver == &kbus_driver.driver) {
+		trace_pxc_kbus(__func__, "enter");
 
-	kbus_boost_dma_task(1);
+		kbus_boost_dma_task(1);
+	}
 #endif
 
 	mcspi = spi_controller_get_devdata(spi->controller);
@@ -777,9 +779,11 @@ omap2_mcspi_txrx_dma_eow(struct spi_device *spi, struct spi_transfer *xfer)
 	int ret;
 
 #ifdef CONFIG_SPI_KBUS_OMAP_EXTENSION
-	trace_pxc_kbus(__func__, "enter");
+	if (spi->dev.driver == &kbus_driver.driver) {
+		trace_pxc_kbus(__func__, "enter");
 
-	kbus_boost_dma_task(1);
+		kbus_boost_dma_task(1);
+	}
 #endif
 
 	mcspi = spi_controller_get_devdata(spi->controller);
@@ -866,10 +870,12 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 	word_len = cs->word_len;
 
 #ifdef CONFIG_SPI_KBUS_OMAP_EXTENSION
-	trace_pxc_kbus(__func__, "enter");
-	kbus_dbg("%s[%d]: count: %d\n", __func__,__LINE__, count);
+	if (spi->dev.driver == &kbus_driver.driver) {
+		trace_pxc_kbus(__func__, "enter");
+		kbus_dbg("%s[%d]: count: %d\n", __func__,__LINE__, count);
 
-	kbus_boost_dma_task(0);
+		kbus_boost_dma_task(0);
+	}
 #endif
 
 	l = mcspi_cached_chconf0(spi);

drivers/spi/spi.c

@@ -2926,7 +2926,7 @@ struct spi_controller *__spi_alloc_controller(struct device *dev,
 	mutex_init(&ctlr->io_mutex);
 	mutex_init(&ctlr->add_lock);
 	ctlr->bus_num = -1;
-	ctlr->num_chipselect = 1;
+	ctlr->num_chipselect = 4;
 	ctlr->slave = slave;
 	if (IS_ENABLED(CONFIG_SPI_SLAVE) && slave)
 		ctlr->dev.class = &spi_slave_class;

drivers/uio/uio.c

@@ -730,19 +730,25 @@ static int uio_mmap_physical(struct vm_area_struct *vma)
 	int mi = uio_find_mem_index(vma);
 	struct uio_mem *mem;
 
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
+
 	if (mi < 0)
 		return -EINVAL;
 	mem = idev->info->mem + mi;
 
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 	if (mem->addr & ~PAGE_MASK)
 		return -ENODEV;
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 	if (vma->vm_end - vma->vm_start > mem->size)
 		return -EINVAL;
 
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 	vma->vm_ops = &uio_physical_vm_ops;
 	if (idev->info->mem[mi].memtype == UIO_MEM_PHYS)
 		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 	/*
 	 * We cannot use the vm_iomap_memory() helper here,
 	 * because vma->vm_pgoff is the map index we looked
@@ -800,10 +806,13 @@ static int uio_mmap(struct file *filep, struct vm_area_struct *vma)
 	switch (idev->info->mem[mi].memtype) {
 	case UIO_MEM_IOVA:
 	case UIO_MEM_PHYS:
+		pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 		ret = uio_mmap_physical(vma);
+		pr_info("TWx: %s:%d ret = %d\n",__func__, __LINE__, ret);
 		break;
 	case UIO_MEM_LOGICAL:
 	case UIO_MEM_VIRTUAL:
+		pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 		ret = uio_mmap_logical(vma);
 		break;
 	default: