save changes

Signed-off-by: Heinrich Toews <ht@twx-software.de>

arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-wosm.dtsi

@@ -53,6 +53,24 @@
 		regulator-always-on;
 		regulator-boot-on;
 	};
+
+	leds_gpio: leds {
+		compatible = "gpio-leds";
+	};
+};
+
+&fss {
+	uio_mram: uio@500000000 {
+		compatible = "uio_pdrv_genirq";
+		linux,uio-name = "UIO_OSPI_MRAM";
+
+		/*
+		 * FSS Memory Region: External Memory Space (Region 3)
+		 * OSPI EVERSPIN MRAM
+		 *
+		 */
+		reg = <0x05 0x00000000 0x01 0x00000000>;
+	};
 };
 
 &mcu_pmx0 {
@@ -161,14 +179,24 @@
 		reg = <0x0>;
 		spi-tx-bus-width = <8>;
 		spi-rx-bus-width = <8>;
-		spi-max-frequency = <200000000>;
-                m25p,fast-read;
-
+		spi-max-frequency = <25000000>;
 		cdns,tshsl-ns = <60>;
 		cdns,tsd2d-ns = <60>;
 		cdns,tchsh-ns = <60>;
 		cdns,tslch-ns = <60>;
-		cdns,read-delay = <0>;
+		cdns,read-delay = <4>;
+		cdns,phy-mode;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "ospi.mram.mem";
+				reg = <0x0 0x800000>;
+			};
+		};
 	};
 };
 

arch/arm64/boot/dts/ti/k3-am623-pfc-750-8xxx-common.dtsi

@@ -236,7 +236,7 @@
 		pinctrl-single,pins = <
 			AM62X_IOPAD(0x01b0, PIN_OUTPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
 			AM62X_IOPAD(0x0194, PIN_INPUT,  1) /* (B19) MCASP0_AXR3.SPI2_D0 */
-			AM62X_IOPAD(0x0198, PIN_INPUT,  1) /* (A19) MCASP0_AXR2.SPI2_D1 */
+			AM62X_IOPAD(0x0198, PIN_OUTPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */
 			AM62X_IOPAD(0x01ac, PIN_OUTPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */
 		>;
 	};

arch/arm64/configs/am6xxx_defconfig

@@ -163,10 +163,12 @@ CONFIG_VEXPRESS_CONFIG=y
 CONFIG_MHI_BUS=m
 CONFIG_ARM_SCMI_PROTOCOL=y
 CONFIG_ARM_SCPI_PROTOCOL=y
-CONFIG_MTD=m
+CONFIG_MTD=y
+CONFIG_MTD_OF_PARTS=m
 CONFIG_MTD_PHYSMAP=m
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_PLATRAM=m
+CONFIG_MTD_SPI_NOR=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=m
 CONFIG_SRAM=y
@@ -269,7 +271,6 @@ CONFIG_I2C_MUX_PCA954x=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
 CONFIG_I2C_OMAP=y
 CONFIG_SPI=y
-# CONFIG_SPI_MEM is not set
 CONFIG_SPI_CADENCE_QUADSPI=y
 CONFIG_SPI_DESIGNWARE=y
 CONFIG_SPI_OMAP24XX=y

drivers/mtd/spi-nor/core.c

@@ -2003,6 +2003,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = {
 	&spi_nor_eon,
 	&spi_nor_esmt,
 	&spi_nor_everspin,
+	&spi_mram_everspin,
 	&spi_nor_fujitsu,
 	&spi_nor_gigadevice,
 	&spi_nor_intel,

drivers/mtd/spi-nor/core.h

@@ -635,6 +635,7 @@ extern const struct spi_nor_manufacturer spi_nor_catalyst;
 extern const struct spi_nor_manufacturer spi_nor_eon;
 extern const struct spi_nor_manufacturer spi_nor_esmt;
 extern const struct spi_nor_manufacturer spi_nor_everspin;
+extern const struct spi_nor_manufacturer spi_mram_everspin;
 extern const struct spi_nor_manufacturer spi_nor_fujitsu;
 extern const struct spi_nor_manufacturer spi_nor_gigadevice;
 extern const struct spi_nor_manufacturer spi_nor_intel;

drivers/mtd/spi-nor/everspin.c

@@ -8,6 +8,248 @@
 
 #include "core.h"
 
+/* flash_info mfr_flag. Used to read proprietary FSR register. */
+#define USE_FSR		BIT(0)
+
+#define SPINOR_OP_RDFSR		0x70	/* Read flag status register */
+#define SPINOR_OP_CLFSR		0x50	/* Clear flag status register */
+#define SPINOR_OP_MT_DTR_RD	0xfd	/* Fast Read opcode in DTR mode */
+#define SPINOR_OP_MT_RD_ANY_REG	0x85	/* Read volatile register */
+#define SPINOR_OP_MT_WR_ANY_REG	0x81	/* Write volatile register */
+#define SPINOR_REG_MT_CFR0V	0x00	/* For setting octal DTR mode */
+#define SPINOR_REG_MT_CFR1V	0x01	/* For setting dummy cycles */
+#define SPINOR_REG_MT_CFR1V_DEF	0x1f	/* Default dummy cycles */
+#define SPINOR_MT_OCT_DTR	0xe7	/* Enable Octal DTR. */
+#define SPINOR_MT_EXSPI		0xff	/* Enable Extended SPI (default) */
+
+/* Flag Status Register bits */
+#define FSR_READY		BIT(7)	/* Device status, 0 = Busy, 1 = Ready */
+#define FSR_E_ERR		BIT(5)	/* Erase operation status */
+#define FSR_P_ERR		BIT(4)	/* Program operation status */
+#define FSR_CRC_ERR		BIT(3)	/* CRC Error status */
+#define FSR_PT_ERR		BIT(1)	/* Protection error bit */
+#define FSR_4B_ADDR		BIT(0)	/* 3 or 4 Byte Addressing Mode */
+
+
+/* Everspin SPI NOR flash operations. */
+#define EVERSPIN_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf)		\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0),		\
+		   SPI_MEM_OP_ADDR(naddr, addr, 0),			\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
+
+#define EVERSPIN_RDFSR_OP(buf)						\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),			\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_IN(1, buf, 0))
+
+#define EVERSPIN_CLFSR_OP						\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0),			\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
+
+static int everspin_nor_octal_dtr_en(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	u8 *buf = nor->bouncebuf;
+	int ret;
+
+	/* Use 8 dummy cycles for memory array reads. */
+	*buf = 8;
+	op = (struct spi_mem_op)
+		EVERSPIN_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR1V, 1, buf);
+	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+	if (ret)
+		return ret;
+
+	buf[0] = SPINOR_MT_OCT_DTR;
+	op = (struct spi_mem_op)
+		EVERSPIN_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 1, buf);
+	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+	if (ret)
+		return ret;
+
+	/* Read flash ID to make sure the switch was successful. */
+	ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR);
+	if (ret) {
+		dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
+		return ret;
+	}
+
+	if (memcmp(buf, nor->info->id, nor->info->id_len))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int everspin_nor_octal_dtr_dis(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	u8 *buf = nor->bouncebuf;
+	int ret;
+
+	/*
+	 * The register is 1-byte wide, but 1-byte transactions are not allowed
+	 * in 8D-8D-8D mode. The next register is the dummy cycle configuration
+	 * register. Since the transaction needs to be at least 2 bytes wide,
+	 * set the next register to its default value. This also makes sense
+	 * because the value was changed when enabling 8D-8D-8D mode, it should
+	 * be reset when disabling.
+	 */
+	buf[0] = SPINOR_MT_EXSPI;
+	buf[1] = SPINOR_REG_MT_CFR1V_DEF;
+	op = (struct spi_mem_op)
+		EVERSPIN_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 2, buf);
+	ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
+	if (ret)
+		return ret;
+
+	/* Read flash ID to make sure the switch was successful. */
+	ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
+	if (ret) {
+		dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);
+		return ret;
+	}
+
+	if (memcmp(buf, nor->info->id, nor->info->id_len))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int everspin_nor_octal_dtr(struct spi_nor *nor, bool enable)
+{
+	return enable ? everspin_nor_octal_dtr_en(nor) :
+			everspin_nor_octal_dtr_dis(nor);
+}
+
+
+/**
+ * everspin_nor_read_fsr() - Read the Flag Status Register.
+ * @nor:	pointer to 'struct spi_nor'
+ * @fsr:	pointer to a DMA-able buffer where the value of the
+ *              Flag Status Register will be written. Should be at least 2
+ *              bytes.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int everspin_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
+{
+	int ret;
+
+	if (nor->spimem) {
+		struct spi_mem_op op = EVERSPIN_RDFSR_OP(fsr);
+
+		if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
+			op.addr.nbytes = nor->params->rdsr_addr_nbytes;
+			op.dummy.nbytes = nor->params->rdsr_dummy;
+			/*
+			 * We don't want to read only one byte in DTR mode. So,
+			 * read 2 and then discard the second byte.
+			 */
+			op.data.nbytes = 2;
+		}
+
+		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+		ret = spi_mem_exec_op(nor->spimem, &op);
+	} else {
+		ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr,
+						      1);
+	}
+
+	if (ret)
+		dev_dbg(nor->dev, "error %d reading FSR\n", ret);
+
+	return ret;
+}
+
+/**
+ * everspin_nor_clear_fsr() - Clear the Flag Status Register.
+ * @nor:	pointer to 'struct spi_nor'.
+ */
+static void everspin_nor_clear_fsr(struct spi_nor *nor)
+{
+	int ret;
+
+	if (nor->spimem) {
+		struct spi_mem_op op = EVERSPIN_CLFSR_OP;
+
+		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+		ret = spi_mem_exec_op(nor->spimem, &op);
+	} else {
+		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR,
+						       NULL, 0);
+	}
+
+	if (ret)
+		dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
+}
+
+/**
+ * everspin_nor_ready() - Query the Status Register as well as the Flag Status
+ * Register to see if the flash is ready for new commands. If there are any
+ * errors in the FSR clear them.
+ * @nor:	pointer to 'struct spi_nor'.
+ *
+ * Return: 1 if ready, 0 if not ready, -errno on errors.
+ */
+static int everspin_nor_ready(struct spi_nor *nor)
+{
+	int sr_ready, ret;
+
+	sr_ready = spi_nor_sr_ready(nor);
+	if (sr_ready < 0)
+		return sr_ready;
+
+	ret = everspin_nor_read_fsr(nor, nor->bouncebuf);
+	if (ret) {
+		/*
+		 * Some controllers, such as Intel SPI, do not support low
+		 * level operations such as reading the flag status
+		 * register. They only expose small amount of high level
+		 * operations to the software. If this is the case we use
+		 * only the status register value.
+		 */
+		return ret == -EOPNOTSUPP ? sr_ready : ret;
+	}
+
+	if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
+		if (nor->bouncebuf[0] & FSR_E_ERR)
+			dev_err(nor->dev, "Erase operation failed.\n");
+		else
+			dev_err(nor->dev, "Program operation failed.\n");
+
+		if (nor->bouncebuf[0] & FSR_PT_ERR)
+			dev_err(nor->dev,
+				"Attempted to modify a protected sector.\n");
+
+		if (nor->bouncebuf[0] & FSR_CRC_ERR)
+			dev_err(nor->dev,
+				"Computed CRC did not match the user provided CRC code.\n");
+
+		everspin_nor_clear_fsr(nor);
+
+		/*
+		 * WEL bit remains set to one when an erase or page program
+		 * error occurs. Issue a Write Disable command to protect
+		 * against inadvertent writes that can possibly corrupt the
+		 * contents of the memory.
+		 */
+		ret = spi_nor_write_disable(nor);
+		if (ret)
+			return ret;
+
+		return -EIO;
+	}
+
+	return sr_ready && !!(nor->bouncebuf[0] & FSR_READY);
+}
+
 static const struct flash_info everspin_nor_parts[] = {
 	/* Everspin */
 	{ "mr25h128", CAT25_INFO(16 * 1024, 1, 256, 2) },
@@ -16,8 +258,90 @@ static const struct flash_info everspin_nor_parts[] = {
 	{ "mr25h40",  CAT25_INFO(512 * 1024, 1, 256, 3) },
 };
 
+static const struct flash_info everspin_mram_parts[] = {
+	/* Everspin */
+	{ "em256lx",  INFO(0x6bbb19, 0, 32 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em128lx",  INFO(0x6bbb18, 0, 16 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em064lx",  INFO(0x6bbb17, 0, 8 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em032lx",  INFO(0x6bbb16, 0, 4 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em016lx",  INFO(0x6bbb15, 0, 2 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em008lx",  INFO(0x6bbb14, 0, 1 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+};
+
+static void everspin_mram_default_init(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	u8 *buf = nor->bouncebuf;
+
+	/* Use 8 dummy cycles for memory array reads. */
+	*buf = 8;
+	op = (struct spi_mem_op)
+		EVERSPIN_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf);
+	spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+
+	nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
+	nor->params->rdsr_dummy = 8;
+	nor->params->rdsr_addr_nbytes = 0;
+	// nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
+	nor->params->addr_nbytes = 4;
+	nor->params->set_octal_dtr = everspin_nor_octal_dtr;
+
+	if (nor->info->mfr_flags & USE_FSR)
+		nor->params->ready = everspin_nor_ready;
+
+	/* Status Register has only 8 Bits */
+	nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+
+	/*
+	 * The BFPT quad enable field is set to a reserved value so the quad
+	 * enable function is ignored by spi_nor_parse_bfpt(). Make sure we
+	 * disable it.
+	 */
+	nor->params->quad_enable = NULL;
+}
+
+static int everspin_mram_late_init(struct spi_nor *nor)
+{
+	/* Set Read and Write settings. */
+	nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8;
+	spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_1_8_8],
+				  0, 8, SPINOR_OP_READ_1_8_8,
+				  SNOR_PROTO_1_8_8);
+
+	nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_1_8_8;
+	spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_1_8_8],
+				SPINOR_OP_PP_1_8_8,
+				SNOR_PROTO_1_8_8);
+
+	return 0;
+}
+
+static const struct spi_nor_fixups everspin_mram_fixups = {
+	.default_init = everspin_mram_default_init,
+	.late_init = everspin_mram_late_init,
+};
+
 const struct spi_nor_manufacturer spi_nor_everspin = {
 	.name = "everspin",
 	.parts = everspin_nor_parts,
 	.nparts = ARRAY_SIZE(everspin_nor_parts),
 };
+
+const struct spi_nor_manufacturer spi_mram_everspin = {
+	.name = "everspin_mram",
+	.parts = everspin_mram_parts,
+	.nparts = ARRAY_SIZE(everspin_mram_parts),
+	.fixups = &everspin_mram_fixups,
+};

drivers/spi/spi-cadence-quadspi.c

@@ -29,6 +29,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/spi-mem.h>
 #include <linux/timer.h>
+#include <linux/string.h>
 
 #define CQSPI_NAME			"cadence-qspi"
 #define CQSPI_MAX_CHIPSELECT		16
@@ -1276,6 +1277,10 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
 	 */
 	if (!op->cmd.dtr && cqspi->use_direct_mode &&
 	    cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {
+		pr_info("TWx: %s:%d - Writing <%lu> bytes with offset <%lld> to ahb_base <%p>\n",
+			__func__, __LINE__, len, to, cqspi->ahb_base + to);
+		print_hex_dump(KERN_INFO, "TWx write buf:", DUMP_PREFIX_OFFSET,
+			       16, 1, buf, len, true);
 		memcpy_toio(cqspi->ahb_base + to, buf, len);
 		return cqspi_wait_idle(cqspi);
 	}
@@ -1701,6 +1706,10 @@ static int cqspi_probe(struct platform_device *pdev)
 	struct cqspi_st *cqspi;
 	int ret;
 	int irq;
+	const u_char *test_buf = "TWX-111-000";
+	loff_t to;
+
+	pr_info("TWx: %s:%d.\n", __func__, __LINE__);
 
 	host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi));
 	if (!host) {
@@ -1752,6 +1761,20 @@ static int cqspi_probe(struct platform_device *pdev)
 	cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
 	cqspi->ahb_size = resource_size(res_ahb);
 
+	pr_info("TWx: %s:%d ahb_base %p.\n",
+		__func__, __LINE__,
+		cqspi->ahb_base);
+
+	pr_info("TWx: %s:%d mmap_phys_base %pad\n",
+		__func__, __LINE__,
+		&cqspi->mmap_phys_base);
+
+	/* print_hex_dump_bytes("TWx 64 byte ahb_base dump:", DUMP_PREFIX_OFFSET,
+			     cqspi->ahb_base, 64); */
+
+	print_hex_dump(KERN_INFO, "TWx ahb_base:", DUMP_PREFIX_OFFSET,
+		       16, 1, cqspi->ahb_base, 64, true);
+
 	init_completion(&cqspi->transfer_complete);
 
 	/* Obtain IRQ line. */
@@ -1874,7 +1897,27 @@ static int cqspi_probe(struct platform_device *pdev)
 		goto probe_setup_failed;
 	}
 
+	pr_info("TWx: %s:%d cqspi->use_direct_mode (%s).\n",
+		__func__, __LINE__,
+		cqspi->use_direct_mode ? "enabled" : "disabled");
+	pr_info("TWx: %s:%d cqspi->use_direct_mode_wr (%s).\n",
+		__func__, __LINE__,
+		cqspi->use_direct_mode_wr ? "enabled" : "disabled");
+
+	to = 5;
+
+	pr_info("TWx: %s:%d - Writing %s, size %lu to ahb_base %lld\n",
+		__func__, __LINE__,
+		test_buf, strlen(test_buf), to);
+
+	memcpy_toio(cqspi->ahb_base + to, test_buf, strlen(test_buf));
+	cqspi_wait_idle(cqspi);
+
+	print_hex_dump(KERN_INFO, "TWx ahb_base:", DUMP_PREFIX_OFFSET,
+		       16, 1, cqspi->ahb_base, 64, true);
+
 	return 0;
+
 probe_setup_failed:
 	cqspi_controller_enable(cqspi, 0);
 probe_reset_failed:

drivers/spi/spi.c

@@ -2926,7 +2926,7 @@ struct spi_controller *__spi_alloc_controller(struct device *dev,
 	mutex_init(&ctlr->io_mutex);
 	mutex_init(&ctlr->add_lock);
 	ctlr->bus_num = -1;
-	ctlr->num_chipselect = 1;
+	ctlr->num_chipselect = 4;
 	ctlr->slave = slave;
 	if (IS_ENABLED(CONFIG_SPI_SLAVE) && slave)
 		ctlr->dev.class = &spi_slave_class;

drivers/uio/uio.c

@@ -730,19 +730,25 @@ static int uio_mmap_physical(struct vm_area_struct *vma)
 	int mi = uio_find_mem_index(vma);
 	struct uio_mem *mem;
 
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
+
 	if (mi < 0)
 		return -EINVAL;
 	mem = idev->info->mem + mi;
 
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 	if (mem->addr & ~PAGE_MASK)
 		return -ENODEV;
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 	if (vma->vm_end - vma->vm_start > mem->size)
 		return -EINVAL;
 
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 	vma->vm_ops = &uio_physical_vm_ops;
 	if (idev->info->mem[mi].memtype == UIO_MEM_PHYS)
 		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 	/*
 	 * We cannot use the vm_iomap_memory() helper here,
 	 * because vma->vm_pgoff is the map index we looked
@@ -800,10 +806,13 @@ static int uio_mmap(struct file *filep, struct vm_area_struct *vma)
 	switch (idev->info->mem[mi].memtype) {
 	case UIO_MEM_IOVA:
 	case UIO_MEM_PHYS:
+		pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 		ret = uio_mmap_physical(vma);
+		pr_info("TWx: %s:%d ret = %d\n",__func__, __LINE__, ret);
 		break;
 	case UIO_MEM_LOGICAL:
 	case UIO_MEM_VIRTUAL:
+		pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 		ret = uio_mmap_logical(vma);
 		break;
 	default: