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phy: phy-rockchip-samsung-hdptx: Supplement some register names with their full version

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Complete the register names of CMN_REG(0081) and CMN_REG(0087) to their
full version, and it can help to better match the datasheet.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250205105157.580060-3-damon.ding@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Damon Ding
2025-02-05 18:51:55 +08:00
committed by Vinod Koul
parent 2947c8065e
commit f706024107
1 changed files with 3 additions and 3 deletions
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drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+3 -3
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@@ -82,14 +82,14 @@
#define ROPLL_SSC_EN BIT(0)
/* CMN_REG(0081) */
#define OVRD_PLL_CD_CLK_EN BIT(8)
#define PLL_CD_HSCLK_EAST_EN BIT(0)
#define ANA_PLL_CD_HSCLK_EAST_EN BIT(0)
/* CMN_REG(0086) */
#define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4)
#define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1)
#define PLL_PCG_CLK_EN BIT(0)
/* CMN_REG(0087) */
#define PLL_FRL_MODE_EN BIT(3)
#define PLL_TX_HS_CLK_EN BIT(2)
#define ANA_PLL_FRL_MODE_EN BIT(3)
#define ANA_PLL_TX_HS_CLK_EN BIT(2)
/* CMN_REG(0089) */
#define LCPLL_ALONE_MODE BIT(1)
/* CMN_REG(0097) */