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drm/amd/display: Adjust codestyle for dcn31 and hdcp_msg

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This commit just update the code style in two if conditions and in an
static array.

Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rodrigo Siqueira
2024-04-18 11:15:11 -06:00
committed by Alex Deucher
parent 6b042da49c
commit f1bf3bc6cb
2 changed files with 5 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+4 -4
View File
@@ -645,9 +645,9 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
s[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
}
if (clk_table->num_entries) {
if (clk_table->num_entries)
dcn3_1_soc.num_states = clk_table->num_entries;
}
memcpy(dcn3_1_soc.clock_limits, s, sizeof(dcn3_1_soc.clock_limits));
@@ -797,9 +797,9 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
s[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
}
if (clk_table->num_entries) {
if (clk_table->num_entries)
dcn3_16_soc.num_states = clk_table->num_entries;
}
memcpy(dcn3_16_soc.clock_limits, s, sizeof(dcn3_16_soc.clock_limits));
drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
+1 -1
View File
@@ -70,7 +70,7 @@ static const bool hdcp_cmd_is_read[HDCP_MESSAGE_ID_MAX] = {
[HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = false,
[HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = true,
[HDCP_MESSAGE_ID_READ_RXSTATUS] = true,
[HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = false
[HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = false,
};
static const uint8_t hdcp_i2c_offsets[HDCP_MESSAGE_ID_MAX] = {