staging: comedi: ni_stc.h: tidy up the windowed_regs_67xx_61xx
Rename the CamelCase. For aesthetics, convert the enum into defines. Use the BIT() macro to define the bits. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
94f0cbb99a
commit
ef3915435c
@@ -1091,7 +1091,7 @@ static int ni_ao_prep_fifo(struct comedi_device *dev,
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/* reset fifo */
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ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
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if (devpriv->is_6xxx)
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ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
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ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
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/* load some data */
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nbytes = comedi_buf_read_n_available(s);
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@@ -2736,9 +2736,9 @@ static int ni_ao_insn_write(struct comedi_device *dev,
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int i;
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if (devpriv->is_6xxx) {
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ni_ao_win_outw(dev, 1 << chan, AO_Immediate_671x);
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ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
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reg = DACx_Direct_Data_671x(chan);
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reg = NI671X_DAC_DIRECT_DATA_REG(chan);
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} else if (devpriv->is_m_series) {
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reg = NI_M_DAC_DIRECT_DATA_REG(chan);
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} else {
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@@ -2838,7 +2838,7 @@ static int ni_ao_inttrig(struct comedi_device *dev,
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#ifdef PCIDMA
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ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
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if (devpriv->is_6xxx)
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ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
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ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
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ret = ni_ao_setup_MITE_dma(dev);
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if (ret)
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return ret;
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@@ -2910,7 +2910,8 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
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if (devpriv->is_6xxx) {
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ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
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ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
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NI611X_AO_MISC_REG);
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bits = 0;
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for (i = 0; i < cmd->chanlist_len; i++) {
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@@ -2918,9 +2919,9 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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chan = CR_CHAN(cmd->chanlist[i]);
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bits |= 1 << chan;
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ni_ao_win_outw(dev, chan, AO_Waveform_Generation_611x);
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ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
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}
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ni_ao_win_outw(dev, bits, AO_Timed_611x);
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ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
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}
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ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
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@@ -3227,8 +3228,9 @@ static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
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for (i = 0; i < s->n_chan; ++i)
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immediate_bits |= 1 << i;
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ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x);
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ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
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ni_ao_win_outw(dev, immediate_bits, NI671X_AO_IMMEDIATE_REG);
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ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
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NI611X_AO_MISC_REG);
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}
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ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
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@@ -3708,9 +3710,9 @@ static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
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for (i = 0; i < s->n_chan; i++) {
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ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
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AO_Configuration_2_67xx);
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NI67XX_AO_CFG2_REG);
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}
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ni_ao_win_outw(dev, 0x0, AO_Later_Single_Point_Updates);
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ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
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}
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static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
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@@ -4472,8 +4474,8 @@ static int cs5529_wait_for_idle(struct comedi_device *dev)
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int i;
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for (i = 0; i < timeout; i++) {
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status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
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if ((status & CSS_ADC_BUSY) == 0)
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status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
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if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
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break;
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set_current_state(TASK_INTERRUPTIBLE);
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if (schedule_timeout(1))
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@@ -4491,13 +4493,14 @@ static void cs5529_command(struct comedi_device *dev, unsigned short value)
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static const int timeout = 100;
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int i;
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ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
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ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
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/* give time for command to start being serially clocked into cs5529.
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* this insures that the CSS_ADC_BUSY bit will get properly
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* this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
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* set before we exit this function.
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*/
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for (i = 0; i < timeout; i++) {
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if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
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if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
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NI67XX_CAL_STATUS_BUSY)
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break;
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udelay(1);
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}
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@@ -4519,18 +4522,18 @@ static int cs5529_do_conversion(struct comedi_device *dev,
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"timeout or signal in cs5529_do_conversion()\n");
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return -ETIME;
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}
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status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
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if (status & CSS_OSC_DETECT) {
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status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
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if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
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dev_err(dev->class_dev,
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"cs5529 conversion error, status CSS_OSC_DETECT\n");
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return -EIO;
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}
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if (status & CSS_OVERRANGE) {
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if (status & NI67XX_CAL_STATUS_OVERRANGE) {
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dev_err(dev->class_dev,
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"cs5529 conversion error, overrange (ignoring)\n");
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}
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if (data) {
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*data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
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*data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
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/* cs5529 returns 16 bit signed data in bipolar mode */
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*data ^= (1 << 15);
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}
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@@ -4554,7 +4557,7 @@ static int cs5529_ai_insn_read(struct comedi_device *dev,
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channel_select = INTERNAL_REF;
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else
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channel_select = CR_CHAN(insn->chanspec);
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ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
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ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
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for (n = 0; n < insn->n; n++) {
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retval = cs5529_do_conversion(dev, &sample);
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@@ -4568,10 +4571,8 @@ static int cs5529_ai_insn_read(struct comedi_device *dev,
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static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
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unsigned int reg_select_bits)
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{
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ni_ao_win_outw(dev, ((value >> 16) & 0xff),
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CAL_ADC_Config_Data_High_Word_67xx);
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ni_ao_win_outw(dev, (value & 0xffff),
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CAL_ADC_Config_Data_Low_Word_67xx);
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ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
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ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
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reg_select_bits &= CS5529_CMD_REG_MASK;
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cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
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if (cs5529_wait_for_idle(dev))
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@@ -650,32 +650,27 @@
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#define NI6143_RELEASE_DATE_REG 0x54 /* w32 */
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#define NI6143_RELEASE_OLDEST_DATE_REG 0x58 /* w32 */
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/* 671x, 611x registers */
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/* 671xi, 611x windowed ao registers */
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enum windowed_regs_67xx_61xx {
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AO_Immediate_671x = 0x11, /* W 16 */
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AO_Timed_611x = 0x10, /* W 16 */
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AO_FIFO_Offset_Load_611x = 0x13, /* W32 */
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AO_Later_Single_Point_Updates = 0x14, /* W 16 */
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AO_Waveform_Generation_611x = 0x15, /* W 16 */
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AO_Misc_611x = 0x16, /* W 16 */
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AO_Calibration_Channel_Select_67xx = 0x17, /* W 16 */
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AO_Configuration_2_67xx = 0x18, /* W 16 */
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CAL_ADC_Command_67xx = 0x19, /* W 8 */
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CAL_ADC_Status_67xx = 0x1a, /* R 8 */
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CAL_ADC_Data_67xx = 0x1b, /* R 16 */
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CAL_ADC_Config_Data_High_Word_67xx = 0x1c, /* RW 16 */
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CAL_ADC_Config_Data_Low_Word_67xx = 0x1d, /* RW 16 */
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};
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static inline unsigned int DACx_Direct_Data_671x(int channel)
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{
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return channel;
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}
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enum AO_Misc_611x_Bits {
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CLEAR_WG = 1,
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};
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/*
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* 671x, 611x windowed ao registers
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*/
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#define NI671X_DAC_DIRECT_DATA_REG(x) (0x00 + (x)) /* w16 */
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#define NI611X_AO_TIMED_REG 0x10 /* w16 */
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#define NI671X_AO_IMMEDIATE_REG 0x11 /* w16 */
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#define NI611X_AO_FIFO_OFFSET_LOAD_REG 0x13 /* w32 */
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#define NI67XX_AO_SP_UPDATES_REG 0x14 /* w16 */
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#define NI611X_AO_WAVEFORM_GEN_REG 0x15 /* w16 */
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#define NI611X_AO_MISC_REG 0x16 /* w16 */
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#define NI611X_AO_MISC_CLEAR_WG BIT(0)
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#define NI67XX_AO_CAL_CHAN_SEL_REG 0x17 /* w16 */
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#define NI67XX_AO_CFG2_REG 0x18 /* w16 */
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#define NI67XX_CAL_CMD_REG 0x19 /* w16 */
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#define NI67XX_CAL_STATUS_REG 0x1a /* r8 */
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#define NI67XX_CAL_STATUS_BUSY BIT(0)
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#define NI67XX_CAL_STATUS_OSC_DETECT BIT(1)
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#define NI67XX_CAL_STATUS_OVERRANGE BIT(2)
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#define NI67XX_CAL_DATA_REG 0x1b /* r16 */
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#define NI67XX_CAL_CFG_HI_REG 0x1c /* rw16 */
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#define NI67XX_CAL_CFG_LO_REG 0x1d /* rw16 */
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#define CS5529_CMD_CB BIT(7)
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#define CS5529_CMD_SINGLE_CONV BIT(6)
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@@ -718,12 +713,6 @@ enum AO_Misc_611x_Bits {
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#define CS5529_CFG_CALIB_OFFSET_SYS CS5529_CFG_CALIB(5)
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#define CS5529_CFG_CALIB_GAIN_SYS CS5529_CFG_CALIB(6)
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enum cs5529_status_bits {
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CSS_ADC_BUSY = 0x1,
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CSS_OSC_DETECT = 0x2, /* indicates adc error */
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CSS_OVERRANGE = 0x4,
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};
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/*
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This is stuff unique to the NI E series drivers,
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but I thought I'd put it here anyway.
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