ASoC: mediatek: mt8365: Add audio clock control support
Add audio clock wrapper and audio tuner control. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://patch.msgid.link/20240226-audio-i350-v7-5-6518d953a141@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Alexandre Mergnat
committed by
Mark Brown
Mark Brown
parent
38c7c9ddc7
commit
ef307b40b7
@@ -0,0 +1,421 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek 8365 AFE clock control
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*
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* Copyright (c) 2024 MediaTek Inc.
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* Authors: Jia Zeng <jia.zeng@mediatek.com>
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* Alexandre Mergnat <amergnat@baylibre.com>
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*/
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#include "mt8365-afe-clk.h"
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#include "mt8365-afe-common.h"
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#include "mt8365-reg.h"
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#include "../common/mtk-base-afe.h"
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#include <linux/device.h>
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#include <linux/mfd/syscon.h>
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static const char *aud_clks[MT8365_CLK_NUM] = {
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[MT8365_CLK_TOP_AUD_SEL] = "top_audio_sel",
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[MT8365_CLK_AUD_I2S0_M] = "audio_i2s0_m",
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[MT8365_CLK_AUD_I2S1_M] = "audio_i2s1_m",
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[MT8365_CLK_AUD_I2S2_M] = "audio_i2s2_m",
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[MT8365_CLK_AUD_I2S3_M] = "audio_i2s3_m",
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[MT8365_CLK_ENGEN1] = "engen1",
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[MT8365_CLK_ENGEN2] = "engen2",
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[MT8365_CLK_AUD1] = "aud1",
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[MT8365_CLK_AUD2] = "aud2",
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[MT8365_CLK_I2S0_M_SEL] = "i2s0_m_sel",
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[MT8365_CLK_I2S1_M_SEL] = "i2s1_m_sel",
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[MT8365_CLK_I2S2_M_SEL] = "i2s2_m_sel",
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[MT8365_CLK_I2S3_M_SEL] = "i2s3_m_sel",
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[MT8365_CLK_CLK26M] = "top_clk26m_clk",
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};
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int mt8365_afe_init_audio_clk(struct mtk_base_afe *afe)
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{
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size_t i;
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
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afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
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if (IS_ERR(afe_priv->clocks[i])) {
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dev_err(afe->dev, "%s devm_clk_get %s fail\n",
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__func__, aud_clks[i]);
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return PTR_ERR(afe_priv->clocks[i]);
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}
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}
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return 0;
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}
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void mt8365_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
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{
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if (clk)
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clk_disable_unprepare(clk);
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}
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int mt8365_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
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unsigned int rate)
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{
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int ret;
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if (clk) {
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ret = clk_set_rate(clk, rate);
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if (ret) {
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dev_err(afe->dev, "Failed to set rate\n");
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return ret;
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}
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}
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return 0;
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}
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int mt8365_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
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struct clk *parent)
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{
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int ret;
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if (clk && parent) {
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ret = clk_set_parent(clk, parent);
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if (ret) {
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dev_err(afe->dev, "Failed to set parent\n");
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return ret;
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}
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}
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return 0;
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}
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static unsigned int get_top_cg_reg(unsigned int cg_type)
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{
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switch (cg_type) {
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case MT8365_TOP_CG_AFE:
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case MT8365_TOP_CG_I2S_IN:
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case MT8365_TOP_CG_22M:
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case MT8365_TOP_CG_24M:
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case MT8365_TOP_CG_INTDIR_CK:
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case MT8365_TOP_CG_APLL2_TUNER:
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case MT8365_TOP_CG_APLL_TUNER:
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case MT8365_TOP_CG_SPDIF:
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case MT8365_TOP_CG_TDM_OUT:
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case MT8365_TOP_CG_TDM_IN:
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case MT8365_TOP_CG_ADC:
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case MT8365_TOP_CG_DAC:
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case MT8365_TOP_CG_DAC_PREDIS:
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case MT8365_TOP_CG_TML:
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return AUDIO_TOP_CON0;
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case MT8365_TOP_CG_I2S1_BCLK:
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case MT8365_TOP_CG_I2S2_BCLK:
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case MT8365_TOP_CG_I2S3_BCLK:
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case MT8365_TOP_CG_I2S4_BCLK:
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case MT8365_TOP_CG_DMIC0_ADC:
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case MT8365_TOP_CG_DMIC1_ADC:
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case MT8365_TOP_CG_DMIC2_ADC:
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case MT8365_TOP_CG_DMIC3_ADC:
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case MT8365_TOP_CG_CONNSYS_I2S_ASRC:
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case MT8365_TOP_CG_GENERAL1_ASRC:
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case MT8365_TOP_CG_GENERAL2_ASRC:
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case MT8365_TOP_CG_TDM_ASRC:
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return AUDIO_TOP_CON1;
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default:
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return 0;
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}
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}
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static unsigned int get_top_cg_mask(unsigned int cg_type)
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{
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switch (cg_type) {
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case MT8365_TOP_CG_AFE:
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return AUD_TCON0_PDN_AFE;
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case MT8365_TOP_CG_I2S_IN:
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return AUD_TCON0_PDN_I2S_IN;
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case MT8365_TOP_CG_22M:
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return AUD_TCON0_PDN_22M;
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case MT8365_TOP_CG_24M:
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return AUD_TCON0_PDN_24M;
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case MT8365_TOP_CG_INTDIR_CK:
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return AUD_TCON0_PDN_INTDIR;
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case MT8365_TOP_CG_APLL2_TUNER:
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return AUD_TCON0_PDN_APLL2_TUNER;
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case MT8365_TOP_CG_APLL_TUNER:
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return AUD_TCON0_PDN_APLL_TUNER;
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case MT8365_TOP_CG_SPDIF:
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return AUD_TCON0_PDN_SPDIF;
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case MT8365_TOP_CG_TDM_OUT:
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return AUD_TCON0_PDN_TDM_OUT;
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case MT8365_TOP_CG_TDM_IN:
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return AUD_TCON0_PDN_TDM_IN;
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case MT8365_TOP_CG_ADC:
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return AUD_TCON0_PDN_ADC;
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case MT8365_TOP_CG_DAC:
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return AUD_TCON0_PDN_DAC;
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case MT8365_TOP_CG_DAC_PREDIS:
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return AUD_TCON0_PDN_DAC_PREDIS;
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case MT8365_TOP_CG_TML:
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return AUD_TCON0_PDN_TML;
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case MT8365_TOP_CG_I2S1_BCLK:
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return AUD_TCON1_PDN_I2S1_BCLK;
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case MT8365_TOP_CG_I2S2_BCLK:
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return AUD_TCON1_PDN_I2S2_BCLK;
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case MT8365_TOP_CG_I2S3_BCLK:
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return AUD_TCON1_PDN_I2S3_BCLK;
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case MT8365_TOP_CG_I2S4_BCLK:
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return AUD_TCON1_PDN_I2S4_BCLK;
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case MT8365_TOP_CG_DMIC0_ADC:
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return AUD_TCON1_PDN_DMIC0_ADC;
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case MT8365_TOP_CG_DMIC1_ADC:
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return AUD_TCON1_PDN_DMIC1_ADC;
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case MT8365_TOP_CG_DMIC2_ADC:
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return AUD_TCON1_PDN_DMIC2_ADC;
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case MT8365_TOP_CG_DMIC3_ADC:
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return AUD_TCON1_PDN_DMIC3_ADC;
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case MT8365_TOP_CG_CONNSYS_I2S_ASRC:
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return AUD_TCON1_PDN_CONNSYS_I2S_ASRC;
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case MT8365_TOP_CG_GENERAL1_ASRC:
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return AUD_TCON1_PDN_GENERAL1_ASRC;
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case MT8365_TOP_CG_GENERAL2_ASRC:
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return AUD_TCON1_PDN_GENERAL2_ASRC;
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case MT8365_TOP_CG_TDM_ASRC:
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return AUD_TCON1_PDN_TDM_ASRC;
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default:
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return 0;
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}
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}
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static unsigned int get_top_cg_on_val(unsigned int cg_type)
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{
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return 0;
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}
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static unsigned int get_top_cg_off_val(unsigned int cg_type)
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{
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return get_top_cg_mask(cg_type);
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}
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int mt8365_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
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{
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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unsigned int reg = get_top_cg_reg(cg_type);
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unsigned int mask = get_top_cg_mask(cg_type);
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unsigned int val = get_top_cg_on_val(cg_type);
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unsigned long flags;
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spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
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afe_priv->top_cg_ref_cnt[cg_type]++;
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if (afe_priv->top_cg_ref_cnt[cg_type] == 1)
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regmap_update_bits(afe->regmap, reg, mask, val);
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spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
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return 0;
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}
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int mt8365_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
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{
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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unsigned int reg = get_top_cg_reg(cg_type);
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unsigned int mask = get_top_cg_mask(cg_type);
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unsigned int val = get_top_cg_off_val(cg_type);
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unsigned long flags;
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spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
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afe_priv->top_cg_ref_cnt[cg_type]--;
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if (afe_priv->top_cg_ref_cnt[cg_type] == 0)
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regmap_update_bits(afe->regmap, reg, mask, val);
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else if (afe_priv->top_cg_ref_cnt[cg_type] < 0)
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afe_priv->top_cg_ref_cnt[cg_type] = 0;
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spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
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return 0;
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}
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int mt8365_afe_enable_main_clk(struct mtk_base_afe *afe)
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{
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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clk_prepare_enable(afe_priv->clocks[MT8365_CLK_TOP_AUD_SEL]);
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mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_AFE);
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mt8365_afe_enable_afe_on(afe);
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return 0;
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}
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int mt8365_afe_disable_main_clk(struct mtk_base_afe *afe)
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{
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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mt8365_afe_disable_afe_on(afe);
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mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_AFE);
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mt8365_afe_disable_clk(afe, afe_priv->clocks[MT8365_CLK_TOP_AUD_SEL]);
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return 0;
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}
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int mt8365_afe_emi_clk_on(struct mtk_base_afe *afe)
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{
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return 0;
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}
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int mt8365_afe_emi_clk_off(struct mtk_base_afe *afe)
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{
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return 0;
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}
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int mt8365_afe_enable_afe_on(struct mtk_base_afe *afe)
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{
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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unsigned long flags;
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spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
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afe_priv->afe_on_ref_cnt++;
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if (afe_priv->afe_on_ref_cnt == 1)
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regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
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spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
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return 0;
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}
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int mt8365_afe_disable_afe_on(struct mtk_base_afe *afe)
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{
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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unsigned long flags;
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spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
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afe_priv->afe_on_ref_cnt--;
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if (afe_priv->afe_on_ref_cnt == 0)
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regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
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else if (afe_priv->afe_on_ref_cnt < 0)
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afe_priv->afe_on_ref_cnt = 0;
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spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
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return 0;
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}
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int mt8365_afe_hd_engen_enable(struct mtk_base_afe *afe, bool apll1)
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{
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if (apll1)
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regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
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AFE_22M_PLL_EN, AFE_22M_PLL_EN);
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else
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regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
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AFE_24M_PLL_EN, AFE_24M_PLL_EN);
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return 0;
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}
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int mt8365_afe_hd_engen_disable(struct mtk_base_afe *afe, bool apll1)
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{
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if (apll1)
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regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
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AFE_22M_PLL_EN, ~AFE_22M_PLL_EN);
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else
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regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
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AFE_24M_PLL_EN, ~AFE_24M_PLL_EN);
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return 0;
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}
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int mt8365_afe_enable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll)
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{
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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mutex_lock(&afe_priv->afe_clk_mutex);
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afe_priv->apll_tuner_ref_cnt[apll]++;
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if (afe_priv->apll_tuner_ref_cnt[apll] != 1) {
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mutex_unlock(&afe_priv->afe_clk_mutex);
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return 0;
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}
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if (apll == MT8365_AFE_APLL1) {
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regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,
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AFE_APLL_TUNER_CFG_MASK, 0x432);
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regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,
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AFE_APLL_TUNER_CFG_EN_MASK, 0x1);
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} else {
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regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,
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AFE_APLL_TUNER_CFG1_MASK, 0x434);
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regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,
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AFE_APLL_TUNER_CFG1_EN_MASK, 0x1);
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}
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mutex_unlock(&afe_priv->afe_clk_mutex);
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return 0;
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}
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int mt8365_afe_disable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll)
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{
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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mutex_lock(&afe_priv->afe_clk_mutex);
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afe_priv->apll_tuner_ref_cnt[apll]--;
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if (afe_priv->apll_tuner_ref_cnt[apll] == 0) {
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if (apll == MT8365_AFE_APLL1)
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regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,
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AFE_APLL_TUNER_CFG_EN_MASK, 0x0);
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else
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regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,
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AFE_APLL_TUNER_CFG1_EN_MASK, 0x0);
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} else if (afe_priv->apll_tuner_ref_cnt[apll] < 0) {
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afe_priv->apll_tuner_ref_cnt[apll] = 0;
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}
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mutex_unlock(&afe_priv->afe_clk_mutex);
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return 0;
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}
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int mt8365_afe_enable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll)
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{
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struct mt8365_afe_private *afe_priv = afe->platform_priv;
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if (apll == MT8365_AFE_APLL1) {
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if (clk_prepare_enable(afe_priv->clocks[MT8365_CLK_ENGEN1])) {
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dev_info(afe->dev, "%s Failed to enable ENGEN1 clk\n",
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__func__);
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return 0;
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}
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mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_22M);
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mt8365_afe_hd_engen_enable(afe, true);
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mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_APLL_TUNER);
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mt8365_afe_enable_apll_tuner_cfg(afe, MT8365_AFE_APLL1);
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} else {
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if (clk_prepare_enable(afe_priv->clocks[MT8365_CLK_ENGEN2])) {
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dev_info(afe->dev, "%s Failed to enable ENGEN2 clk\n",
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__func__);
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return 0;
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}
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mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_24M);
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mt8365_afe_hd_engen_enable(afe, false);
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mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_APLL2_TUNER);
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mt8365_afe_enable_apll_tuner_cfg(afe, MT8365_AFE_APLL2);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8365_afe_disable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll)
|
||||
{
|
||||
struct mt8365_afe_private *afe_priv = afe->platform_priv;
|
||||
|
||||
if (apll == MT8365_AFE_APLL1) {
|
||||
mt8365_afe_disable_apll_tuner_cfg(afe, MT8365_AFE_APLL1);
|
||||
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_APLL_TUNER);
|
||||
mt8365_afe_hd_engen_disable(afe, true);
|
||||
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_22M);
|
||||
clk_disable_unprepare(afe_priv->clocks[MT8365_CLK_ENGEN1]);
|
||||
} else {
|
||||
mt8365_afe_disable_apll_tuner_cfg(afe, MT8365_AFE_APLL2);
|
||||
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_APLL2_TUNER);
|
||||
mt8365_afe_hd_engen_disable(afe, false);
|
||||
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_24M);
|
||||
clk_disable_unprepare(afe_priv->clocks[MT8365_CLK_ENGEN2]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,32 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* MediaTek 8365 AFE clock control definitions
|
||||
*
|
||||
* Copyright (c) 2024 MediaTek Inc.
|
||||
* Authors: Jia Zeng <jia.zeng@mediatek.com>
|
||||
* Alexandre Mergnat <amergnat@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef _MT8365_AFE_UTILS_H_
|
||||
#define _MT8365_AFE_UTILS_H_
|
||||
|
||||
struct mtk_base_afe;
|
||||
struct clk;
|
||||
|
||||
int mt8365_afe_init_audio_clk(struct mtk_base_afe *afe);
|
||||
void mt8365_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||
int mt8365_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, unsigned int rate);
|
||||
int mt8365_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, struct clk *parent);
|
||||
int mt8365_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type);
|
||||
int mt8365_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type);
|
||||
int mt8365_afe_enable_main_clk(struct mtk_base_afe *afe);
|
||||
int mt8365_afe_disable_main_clk(struct mtk_base_afe *afe);
|
||||
int mt8365_afe_emi_clk_on(struct mtk_base_afe *afe);
|
||||
int mt8365_afe_emi_clk_off(struct mtk_base_afe *afe);
|
||||
int mt8365_afe_enable_afe_on(struct mtk_base_afe *afe);
|
||||
int mt8365_afe_disable_afe_on(struct mtk_base_afe *afe);
|
||||
int mt8365_afe_enable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll);
|
||||
int mt8365_afe_disable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll);
|
||||
int mt8365_afe_enable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll);
|
||||
int mt8365_afe_disable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll);
|
||||
#endif
|
||||
Reference in New Issue
Block a user