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drm/rockchip: vop3: update acm info when it change

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When update acm info, it need disable acm function in the first frame,
then update the acm info and enable acm function in the second frame.
If the acm info is not changed between 2 frames, it don't need update.

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Iaedead2fad5951844ca07b037c3588071499e50a
This commit is contained in:
Zhang Yubing
2022-12-20 17:40:08 +08:00
committed by Tao Huang
parent ce5da098c4
commit e847ed9deb
6 changed files with 66 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+31
View File
@@ -184,6 +184,37 @@ struct rockchip_dsc_sink_cap {
u16 target_bits_per_pixel_x16;
};
#define ACM_GAIN_LUT_HY_LENGTH (9*17)
#define ACM_GAIN_LUT_HY_TOTAL_LENGTH (ACM_GAIN_LUT_HY_LENGTH * 3)
#define ACM_GAIN_LUT_HS_LENGTH (13*17)
#define ACM_GAIN_LUT_HS_TOTAL_LENGTH (ACM_GAIN_LUT_HS_LENGTH * 3)
#define ACM_DELTA_LUT_H_LENGTH 65
#define ACM_DELTA_LUT_H_TOTAL_LENGTH (ACM_DELTA_LUT_H_LENGTH * 3)
struct post_acm {
s16 delta_lut_h[ACM_DELTA_LUT_H_TOTAL_LENGTH];
s16 gain_lut_hy[ACM_GAIN_LUT_HY_TOTAL_LENGTH];
s16 gain_lut_hs[ACM_GAIN_LUT_HS_TOTAL_LENGTH];
u16 y_gain;
u16 h_gain;
u16 s_gain;
u16 acm_enable;
};
struct post_csc {
u16 hue;
u16 saturation;
u16 contrast;
u16 brightness;
u16 r_gain;
u16 g_gain;
u16 b_gain;
u16 r_offset;
u16 g_offset;
u16 b_offset;
u16 csc_enable;
};
struct rockchip_crtc_state {
struct drm_crtc_state base;
int vp_id;
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-31
View File
@@ -597,37 +597,6 @@ enum vop_hdr_format {
HDR_FORMAT_MAX,
};
#define ACM_GAIN_LUT_HY_LENGTH (9*17)
#define ACM_GAIN_LUT_HY_TOTAL_LENGTH (ACM_GAIN_LUT_HY_LENGTH * 3)
#define ACM_GAIN_LUT_HS_LENGTH (13*17)
#define ACM_GAIN_LUT_HS_TOTAL_LENGTH (ACM_GAIN_LUT_HS_LENGTH * 3)
#define ACM_DELTA_LUT_H_LENGTH 65
#define ACM_DELTA_LUT_H_TOTAL_LENGTH (ACM_DELTA_LUT_H_LENGTH * 3)
struct post_acm {
s16 delta_lut_h[ACM_DELTA_LUT_H_TOTAL_LENGTH];
s16 gain_lut_hy[ACM_GAIN_LUT_HY_TOTAL_LENGTH];
s16 gain_lut_hs[ACM_GAIN_LUT_HS_TOTAL_LENGTH];
u16 y_gain;
u16 h_gain;
u16 s_gain;
u16 acm_enable;
};
struct post_csc {
u16 hue;
u16 saturation;
u16 contrast;
u16 brightness;
u16 r_gain;
u16 g_gain;
u16 b_gain;
u16 r_offset;
u16 g_offset;
u16 b_offset;
u16 csc_enable;
};
struct post_csc_coef {
s32 csc_coef00;
s32 csc_coef01;
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+32 -13
View File
@@ -770,6 +770,9 @@ struct vop2_video_port {
*/
enum vop2_layer_phy_id primary_plane_phy_id;
struct post_acm acm_info;
struct post_csc csc_info;
/**
* @refresh_rate_change: indicate whether refresh rate change
*/
@@ -9505,18 +9508,25 @@ static void vop3_post_acm_config(struct drm_crtc *crtc, struct post_acm *acm)
u32 value;
int i;
if (!acm) {
writel(0x2, vop2->acm_regs + RK3528_ACM_CTRL);
VOP_MODULE_SET(vop2, vp, acm_bypass_en, 1);
writel(0, vop2->acm_regs + RK3528_ACM_CTRL);
VOP_MODULE_SET(vop2, vp, acm_bypass_en, 0);
if (!acm || !acm->acm_enable)
return;
}
writel(1, vop2->acm_regs + RK3528_ACM_FETCH_START);
/*
* If acm update parameters, it need disable acm in the first frame,
* then update parameters and enable acm in second frame.
*/
vop2_cfg_done(crtc);
readx_poll_timeout(readl, vop2->acm_regs + RK3528_ACM_CTRL, value, !value, 200, 50000);
value = (acm->acm_enable & 0x1) + ((adjusted_mode->hdisplay & 0xfff) << 8) +
value = RK3528_ACM_ENABLE + ((adjusted_mode->hdisplay & 0xfff) << 8) +
((adjusted_mode->vdisplay & 0xfff) << 20);
writel(value, vop2->acm_regs + RK3528_ACM_CTRL);
VOP_MODULE_SET(vop2, vp, acm_bypass_en, acm->acm_enable ? 0 : 1);
writel(1, vop2->acm_regs + RK3528_ACM_FETCH_START);
value = (acm->y_gain & 0x3ff) + ((acm->h_gain << 10) & 0xffc00) +
((acm->s_gain << 20) & 0x3ff00000);
@@ -9555,14 +9565,23 @@ static void vop3_post_acm_config(struct drm_crtc *crtc, struct post_acm *acm)
static void vop3_post_config(struct drm_crtc *crtc)
{
struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
struct vop2_video_port *vp = to_vop2_video_port(crtc);
struct post_acm *acm;
struct post_csc *csc;
acm = vcstate->acm_lut_data ? (struct post_acm *)vcstate->acm_lut_data->data : NULL;
vop3_post_acm_config(crtc, acm);
csc = vcstate->post_csc_data ? (struct post_csc *)vcstate->post_csc_data->data : NULL;
vop3_post_csc_config(crtc, acm, csc);
if (csc && memcmp(&vp->csc_info, csc, sizeof(struct post_csc)))
memcpy(&vp->csc_info, csc, sizeof(struct post_csc));
vop3_post_csc_config(crtc, &vp->acm_info, &vp->csc_info);
acm = vcstate->acm_lut_data ? (struct post_acm *)vcstate->acm_lut_data->data : NULL;
if (acm && memcmp(&vp->acm_info, acm, sizeof(struct post_acm))) {
memcpy(&vp->acm_info, acm, sizeof(struct post_acm));
vop3_post_acm_config(crtc, &vp->acm_info);
} else if (crtc->state->active_changed) {
vop3_post_acm_config(crtc, &vp->acm_info);
}
}
static void vop2_cfg_update(struct drm_crtc *crtc,
@@ -9623,10 +9642,10 @@ static void vop2_cfg_update(struct drm_crtc *crtc,
if (vp_data->feature & VOP_FEATURE_OVERSCAN)
vop2_post_config(crtc);
spin_unlock(&vop2->reg_lock);
if (vp_data->feature & (VOP_FEATURE_POST_ACM | VOP_FEATURE_POST_CSC))
vop3_post_config(crtc);
spin_unlock(&vop2->reg_lock);
}
static void vop2_sleep_scan_line_time(struct vop2_video_port *vp, int scan_line)
drivers/gpu/drm/rockchip/rockchip_post_csc.c
-1
View File
@@ -5,7 +5,6 @@
*/
#include "rockchip_post_csc.h"
#include "rockchip_drm_drv.h"
#define PQ_CSC_HUE_TABLE_NUM 256
#define PQ_CSC_MODE_COEF_COMMENT_LEN 32
drivers/gpu/drm/rockchip/rockchip_post_csc.h
+1
View File
@@ -9,6 +9,7 @@
#define _ROCKCHIP_POST_CSC_H
#include <drm/drm_crtc.h>
#include "rockchip_drm_drv.h"
#include "rockchip_drm_vop.h"
int rockchip_calc_post_csc(struct post_csc *csc, struct post_csc_coef *csc_coef,
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
+2
View File
@@ -1759,6 +1759,8 @@
/* RK3588 ACM register definition */
#define RK3528_ACM_CTRL 0x0000
#define RK3528_ACM_ENABLE BIT(0)
#define RK3528_ACM_BYPASS BIT(1)
#define RK3528_ACM_DELTA_RANGE 0x0004
#define RK3528_ACM_FETCH_START 0x0008
#define RK3528_ACM_DEBUG_POINT0 0x0010