serial: Airoha SoC UART and HSUART support
Support for Airoha AN7581 SoC UART and HSUART baud rate calculation routine. Signed-off-by: Benjamin Larsson <benjamin.larsson@genexis.eu> Link: https://lore.kernel.org/r/20250119130105.2833517-3-benjamin.larsson@genexis.eu Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Greg Kroah-Hartman
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@@ -314,6 +314,21 @@ static inline int serial8250_in_MCR(struct uart_8250_port *up)
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return mctrl;
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}
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/* uart_config[] table port type defines */
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/* Airoha UART */
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#define PORT_AIROHA 124
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/* Airoha HSUART */
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#define PORT_AIROHA_HS 125
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#ifdef CONFIG_SERIAL_8250_AIROHA
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void airoha8250_set_baud_rate(struct uart_port *port,
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unsigned int baud, unsigned int hs);
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#else
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static inline void airoha8250_set_baud_rate(struct uart_port *port,
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unsigned int baud, unsigned int hs) { }
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#endif
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#ifdef CONFIG_SERIAL_8250_PNP
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int serial8250_pnp_init(void);
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void serial8250_pnp_exit(void);
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@@ -0,0 +1,81 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Airoha UART baud rate calculation function
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*
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* Copyright (c) 2025 Genexis Sweden AB
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* Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
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*/
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#include "8250.h"
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/* The Airoha UART is 16550-compatible except for the baud rate calculation. */
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/* Airoha UART registers */
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#define UART_AIROHA_BRDL 0
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#define UART_AIROHA_BRDH 1
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#define UART_AIROHA_XINCLKDR 10
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#define UART_AIROHA_XYD 11
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#define XYD_Y 65000
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#define XINDIV_CLOCK 20000000
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#define UART_BRDL_20M 0x01
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#define UART_BRDH_20M 0x00
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static const int clock_div_tab[] = { 10, 4, 2};
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static const int clock_div_reg[] = { 4, 2, 1};
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/**
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* airoha8250_set_baud_rate() - baud rate calculation routine
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* @port: uart port
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* @baud: requested uart baud rate
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* @hs: uart type selector, 0 for regular uart and 1 for high-speed uart
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*
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* crystal_clock = 20 MHz (fixed frequency)
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* xindiv_clock = crystal_clock / clock_div
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* (x/y) = XYD, 32 bit register with 16 bits of x and then 16 bits of y
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* clock_div = XINCLK_DIVCNT (default set to 10 (0x4)),
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* - 3 bit register [ 1, 2, 4, 8, 10, 12, 16, 20 ]
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*
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* baud_rate = ((xindiv_clock) * (x/y)) / ([BRDH,BRDL] * 16)
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*
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* Selecting divider needs to fulfill
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* 1.8432 MHz <= xindiv_clk <= APB clock / 2
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* The clocks are unknown but a divider of value 1 did not result in a valid
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* waveform.
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*
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* XYD_y seems to need to be larger then XYD_x for proper waveform generation.
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* Setting [BRDH,BRDL] to [0,1] and XYD_y to 65000 gives even values
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* for usual baud rates.
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*/
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void airoha8250_set_baud_rate(struct uart_port *port,
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unsigned int baud, unsigned int hs)
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{
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struct uart_8250_port *up = up_to_u8250p(port);
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unsigned int xyd_x, nom, denom;
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int i;
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/* set DLAB to access the baud rate divider registers (BRDH, BRDL) */
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serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
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/* set baud rate calculation defaults */
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/* set BRDIV ([BRDH,BRDL]) to 1 */
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serial_port_out(port, UART_AIROHA_BRDL, UART_BRDL_20M);
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serial_port_out(port, UART_AIROHA_BRDH, UART_BRDH_20M);
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/* calculate XYD_x and XINCLKDR register by searching
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* through a table of crystal_clock divisors
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*
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* for the HSUART xyd_x needs to be scaled by a factor of 2
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*/
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for (i = 0 ; i < ARRAY_SIZE(clock_div_tab) ; i++) {
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denom = (XINDIV_CLOCK/40) / clock_div_tab[i];
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nom = baud * (XYD_Y/40);
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xyd_x = ((nom/denom) << 4) >> hs;
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if (xyd_x < XYD_Y)
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break;
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}
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serial_port_out(port, UART_AIROHA_XINCLKDR, clock_div_reg[i]);
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serial_port_out(port, UART_AIROHA_XYD, (xyd_x<<16) | XYD_Y);
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/* unset DLAB */
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serial_port_out(port, UART_LCR, up->lcr);
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}
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@@ -341,6 +341,8 @@ static const struct of_device_id of_platform_serial_table[] = {
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{ .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
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{ .compatible = "nuvoton,wpcm450-uart", .data = (void *)PORT_NPCM, },
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{ .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, },
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{ .compatible = "airoha,airoha-uart", .data = (void *)PORT_AIROHA, },
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{ .compatible = "airoha,airoha-hsuart", .data = (void *)PORT_AIROHA_HS, },
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{ /* end of list */ },
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};
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MODULE_DEVICE_TABLE(of, of_platform_serial_table);
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@@ -319,6 +319,24 @@ static const struct serial8250_config uart_config[] = {
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.rxtrig_bytes = {1, 8, 16, 30},
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.flags = UART_CAP_FIFO | UART_CAP_AFE,
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},
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/* From here on after additional uart config port defines are placed in 8250.h
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*/
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[PORT_AIROHA] = {
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.name = "Airoha UART",
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.fifo_size = 8,
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.tx_loadsz = 1,
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.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | UART_FCR_CLEAR_RCVR,
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.rxtrig_bytes = {1, 4},
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.flags = UART_CAP_FIFO,
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},
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[PORT_AIROHA_HS] = {
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.name = "Airoha HSUART",
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.fifo_size = 128,
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.tx_loadsz = 128,
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.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | UART_FCR_CLEAR_RCVR,
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.rxtrig_bytes = {1, 4},
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.flags = UART_CAP_FIFO,
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},
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};
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/* Uart divisor latch read */
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@@ -2865,6 +2883,14 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
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serial8250_set_divisor(port, baud, quot, frac);
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/*
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* Airoha SoCs have custom registers for baud rate settings
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*/
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if (port->type == PORT_AIROHA)
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airoha8250_set_baud_rate(port, baud, 0);
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if (port->type == PORT_AIROHA_HS)
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airoha8250_set_baud_rate(port, baud, 1);
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/*
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* LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
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* is written without DLAB set, this mode will be disabled.
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@@ -356,6 +356,16 @@ config SERIAL_8250_ACORN
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system, say Y to this option. The driver can handle 1, 2, or 3 port
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cards. If unsure, say N.
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config SERIAL_8250_AIROHA
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tristate "Airoha UART support"
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depends on (ARCH_AIROHA || COMPILE_TEST) && OF && SERIAL_8250
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help
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Selecting this option enables an Airoha SoC specific baud rate
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calculation routine on an otherwise 16550 compatible UART hardware.
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If you have an Airoha based board and want to use the serial port,
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say Y to this option. If unsure, say N.
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config SERIAL_8250_BCM2835AUX
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tristate "BCM2835 auxiliar mini UART support"
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depends on ARCH_BCM2835 || COMPILE_TEST
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@@ -20,6 +20,7 @@ obj-$(CONFIG_SERIAL_8250_CONSOLE) += 8250_early.o
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obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o
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obj-$(CONFIG_SERIAL_8250_ACORN) += 8250_acorn.o
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obj-$(CONFIG_SERIAL_8250_AIROHA) += 8250_airoha.o
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obj-$(CONFIG_SERIAL_8250_ASPEED_VUART) += 8250_aspeed_vuart.o
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obj-$(CONFIG_SERIAL_8250_BCM2835AUX) += 8250_bcm2835aux.o
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obj-$(CONFIG_SERIAL_8250_BCM7271) += 8250_bcm7271.o
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