arm64: dts: freescale: add TQMa8MPQL on MBa8MP-RAS314
This adds support for TQMa8MPQL module on MBa8MP-RAS314 board. Signed-off-by: Martin Schmiedel <Martin.Schmiedel@tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Martin Schmiedel
committed by
Shawn Guo
Shawn Guo
parent
2fca3b6ba3
commit
ddabb3ce3f
@@ -178,6 +178,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb
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@@ -0,0 +1,906 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (c) 2023-2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
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* D-82229 Seefeld, Germany.
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* Author: Martin Schmiedel
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* Author: Alexander Stein
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*/
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/dts-v1/;
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include <dt-bindings/pwm/pwm.h>
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#include "imx8mp-tqma8mpql.dtsi"
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/ {
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model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MP-RAS314";
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compatible = "tq,imx8mp-tqma8mpql-mba8mp-ras314", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
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chassis-type = "embedded";
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chosen {
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stdout-path = &uart4;
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};
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aliases {
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mmc0 = &usdhc3;
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mmc1 = &usdhc2;
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mmc2 = &usdhc1;
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rtc0 = &pcf85063;
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rtc1 = &snvs_rtc;
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};
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/* X8 */
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backlight_lvds: backlight {
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compatible = "pwm-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_backlight>;
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pwms = <&pwm2 0 5000000 0>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <7>;
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power-supply = <®_vcc_12v0>;
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enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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/* X7 + X8 */
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display: display {
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/*
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* Display is not fixed, so compatible has to be added from
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* DT overlay
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*/
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lvdsdisplay>;
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power-supply = <®_vcc_3v3>;
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enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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backlight = <&backlight_lvds>;
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status = "disabled";
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpioled>;
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led-1 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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function-enumerator = <0>;
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gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
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};
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led-2 {
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_STATUS;
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function-enumerator = <1>;
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gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
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};
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};
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hdmi-connector {
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compatible = "hdmi-connector";
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label = "X9";
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type = "a";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&hdmi_tx_out>;
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};
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};
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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reg_vcc_3v3: regulator-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "V_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_vcc_5v0: regulator-5v0 {
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compatible = "regulator-fixed";
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regulator-name = "V_5V0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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reg_vcc_12v0: regulator-12v0 {
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compatible = "regulator-fixed";
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regulator-name = "V_12V";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0 0x38000000>;
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alloc-ranges = <0 0x40000000 0 0xB0000000>;
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linux,cma-default;
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};
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};
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rfkill {
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compatible = "rfkill-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rfkill>;
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label = "rfkill-pcie-wlan";
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radio-type = "wlan";
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shutdown-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
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};
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sound {
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compatible = "fsl,imx-audio-tlv320aic32x4";
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model = "tq-mba8mp-ras314";
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audio-cpu = <&sai5>;
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audio-codec = <&tlv320aic3x04>;
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audio-routing =
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"IN3_L", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"Headphone Jack", "HPL",
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"Headphone Jack", "HPR";
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};
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};
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&ecspi3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3>;
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cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio1 6 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy3>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy3: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos_phy>;
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reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
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reset-assert-us = <500000>;
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reset-deassert-us = <50000>;
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enet-phy-lane-no-swap;
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interrupt-parent = <&gpio4>;
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interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,dp83867-rxctrl-strap-quirk;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec_phy>;
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reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
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reset-assert-us = <500000>;
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reset-deassert-us = <50000>;
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enet-phy-lane-no-swap;
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interrupt-parent = <&gpio4>;
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interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,dp83867-rxctrl-strap-quirk;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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};
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};
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};
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&gpio1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio1>;
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gpio-line-names = "WIFI_PMIC_EN", "LVDS_RESET#", "", "",
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"", "", "GPIO8", "",
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"", "", "", "",
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"", "", "GPIO12", "GPIO13",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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wifi-pmic-en-hog {
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gpio-hog;
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gpios = <0 0>;
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output-high;
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line-name = "WIFI_PMIC_EN";
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};
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};
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&gpio2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio2>;
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gpio-line-names = "GPIO22", "GPIO23", "GPIO24", "GPIO25",
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"GPIO26", "GPIO27", "CAM_GPIO1", "CAM_GPIO2",
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"", "", "GPIO1", "GPIO0",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpio3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio3>;
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gpio-line-names = "", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"TEMP_EVENT#", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpio4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio4>;
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gpio-line-names = "", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"HDMI_OC#", "GPIO14", "GPIO15", "GPIO16",
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"GPIO17", "PCIE_WAKE#", "GPIO19", "GPIO20",
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"PCIE_PERST#", "", "", "";
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pewake-hog {
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gpio-hog;
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gpios = <25 0>;
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input;
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line-name = "PCIE_WAKE#";
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};
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};
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&gpio5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpt1_gpio>,
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<&pinctrl_gpt2_gpio>, <&pinctrl_gpt3_gpio>;
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gpio-line-names = "", "GPIO18", "", "GPIO3",
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"GPIO2", "GPIO21", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "GPIO5", "GPIO6",
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"", "", "GPIO11", "GPIO10",
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"GPIO9", "GPIO7", "", "GPIO4",
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"", "", "", "";
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};
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&gpt1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpt1>;
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status = "disabled";
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};
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&gpt2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpt2>;
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status = "disabled";
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};
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&gpt3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpt3>;
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status = "disabled";
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};
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&hdmi_pvi {
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status = "okay";
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};
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&hdmi_tx {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hdmi>;
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status = "okay";
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ports {
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port@1 {
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hdmi_tx_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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};
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};
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&hdmi_tx_phy {
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status = "okay";
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};
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/* X5 + X6 Camera & Display interface */
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&i2c2 {
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clock-frequency = <384000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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};
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/* X1 ID_I2C */
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&i2c3 {
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clock-frequency = <384000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c3>;
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pinctrl-1 = <&pinctrl_i2c3_gpio>;
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scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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};
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&i2c4 {
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clock-frequency = <384000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c4>;
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pinctrl-1 = <&pinctrl_i2c4_gpio>;
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scl-gpios = <&gpio5 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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tlv320aic3x04: audio-codec@18 {
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compatible = "ti,tlv320aic32x4";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tlv320aic3x04>;
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reg = <0x18>;
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clock-names = "mclk";
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clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>;
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reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
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iov-supply = <®_vcc_3v3>;
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ldoin-supply = <®_vcc_3v3>;
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};
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};
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/* X1 I2C */
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&i2c5 {
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clock-frequency = <384000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c5>;
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pinctrl-1 = <&pinctrl_i2c5_gpio>;
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scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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};
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/* X1 I2C on GPIO24/GPIO25 */
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&i2c6 {
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clock-frequency = <384000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c6>;
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pinctrl-1 = <&pinctrl_i2c6_gpio>;
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scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "disabled";
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};
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&lcdif3 {
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status = "okay";
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};
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&pcf85063 {
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/* RTC_EVENT# is connected on MBa8MP-RAS314 */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcf85063>;
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interrupt-parent = <&gpio3>;
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interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
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};
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&pcie_phy {
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clocks = <&hsio_blk_ctrl>;
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clock-names = "ref";
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie>;
|
||||
reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai5>;
|
||||
assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
|
||||
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
|
||||
assigned-clock-rates = <12288000>;
|
||||
fsl,sai-mclk-direction-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* X1 UART1 */
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
uart-has-rtscts;
|
||||
assigned-clocks = <&clk IMX8MP_CLK_UART1>;
|
||||
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
uart-has-rtscts;
|
||||
assigned-clocks = <&clk IMX8MP_CLK_UART2>;
|
||||
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "nxp,88w8987-bt";
|
||||
};
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
assigned-clocks = <&clk IMX8MP_CLK_UART3>;
|
||||
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
/* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
fsl,disable-port-power-control;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_1 {
|
||||
fsl,disable-port-power-control;
|
||||
fsl,permanently-attached;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy0 {
|
||||
vbus-supply = <®_vcc_5v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy1 {
|
||||
vbus-supply = <®_vcc_5v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_0 {
|
||||
dr_mode = "peripheral";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbhub>;
|
||||
status = "okay";
|
||||
|
||||
hub_2_0: hub@1 {
|
||||
compatible = "usb451,8142";
|
||||
reg = <1>;
|
||||
peer-hub = <&hub_3_0>;
|
||||
reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
|
||||
vdd-supply = <®_vcc_3v3>;
|
||||
};
|
||||
|
||||
hub_3_0: hub@2 {
|
||||
compatible = "usb451,8140";
|
||||
reg = <2>;
|
||||
peer-hub = <&hub_2_0>;
|
||||
reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
|
||||
vdd-supply = <®_vcc_3v3>;
|
||||
};
|
||||
};
|
||||
|
||||
/* X1 SD card on GPIO22-GPIO27 */
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
disable-wp;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
no-mmc;
|
||||
no-sdio;
|
||||
disable-wp;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_backlight: backlightgrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi3: ecspi3grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x140>,
|
||||
<MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x140>,
|
||||
<MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>,
|
||||
<MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x140>,
|
||||
<MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi3_gpio: ecspi3gpiogrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x80>,
|
||||
<MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x80>,
|
||||
<MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x80>,
|
||||
<MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x80>,
|
||||
<MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x80>;
|
||||
};
|
||||
|
||||
pinctrl_eqos: eqosgrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>,
|
||||
<MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>,
|
||||
<MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>,
|
||||
<MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>,
|
||||
<MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>,
|
||||
<MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>,
|
||||
<MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>,
|
||||
<MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>,
|
||||
<MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>,
|
||||
<MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>,
|
||||
<MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>,
|
||||
<MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>,
|
||||
<MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>,
|
||||
<MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_eqos_phy: eqosphygrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>,
|
||||
<MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>,
|
||||
<MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>,
|
||||
<MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>,
|
||||
<MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>,
|
||||
<MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>,
|
||||
<MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>,
|
||||
<MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>,
|
||||
<MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>,
|
||||
<MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>,
|
||||
<MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>,
|
||||
<MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>,
|
||||
<MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>,
|
||||
<MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>,
|
||||
<MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_fec_phy: fecphygrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>,
|
||||
<MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>;
|
||||
};
|
||||
|
||||
pinctrl_gpioled: gpioledgrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x14>,
|
||||
<MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_gpio1: gpio1grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x14>,
|
||||
<MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_gpio2: gpio2grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x94>,
|
||||
<MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x94>,
|
||||
<MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x94>,
|
||||
<MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x94>,
|
||||
<MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x94>,
|
||||
<MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x94>,
|
||||
<MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x94>,
|
||||
<MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x94>;
|
||||
};
|
||||
|
||||
pinctrl_gpio3: gpio3grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x180>;
|
||||
};
|
||||
|
||||
pinctrl_gpio4: gpio4grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x80>,
|
||||
/* PCIE_WAKE# */
|
||||
<MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>,
|
||||
<MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x94>,
|
||||
<MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x94>;
|
||||
};
|
||||
|
||||
pinctrl_gpio5: gpio5grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x80>,
|
||||
<MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x80>;
|
||||
};
|
||||
|
||||
pinctrl_hdmi: hdmigrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>,
|
||||
<MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>,
|
||||
<MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>,
|
||||
<MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000154>;
|
||||
};
|
||||
|
||||
pinctrl_gpt1: gpt1grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_gpt1_gpio: gpt1gpiogrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x80>;
|
||||
};
|
||||
|
||||
pinctrl_gpt2: gpt2grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_gpt2_gpio: gpt2gpiogrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>;
|
||||
};
|
||||
|
||||
pinctrl_gpt3: gpt3grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_gpt3_gpio: gpt3gpiogrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x80>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>,
|
||||
<MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_gpio: i2c2-gpiogrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>,
|
||||
<MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x400001e2>,
|
||||
<MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x400001e2>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3_gpio: i2c3-gpiogrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x400001e2>,
|
||||
<MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x400001e2>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x400001e2>,
|
||||
<MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x400001e2>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4_gpio: i2c4-gpiogrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x400001e2>,
|
||||
<MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x400001e2>;
|
||||
};
|
||||
|
||||
pinctrl_i2c5: i2c5grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001e2>,
|
||||
<MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001e2>;
|
||||
};
|
||||
|
||||
pinctrl_i2c5_gpio: i2c5-gpiogrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x400001e2>,
|
||||
<MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x400001e2>;
|
||||
};
|
||||
|
||||
pinctrl_i2c6: i2c6grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>,
|
||||
<MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>;
|
||||
};
|
||||
|
||||
pinctrl_i2c6_gpio: i2c6-gpiogrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>,
|
||||
<MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>;
|
||||
};
|
||||
|
||||
pinctrl_pcf85063: pcf85063grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x80>;
|
||||
};
|
||||
|
||||
pinctrl_pcie: pciegrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60>,
|
||||
<MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x94>;
|
||||
};
|
||||
|
||||
pinctrl_lvdsdisplay: lvdsdisplaygrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x10>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3_gpio: pwm3grpiogrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4: pwm4grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4_gpio: pwm4grpiogrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>;
|
||||
};
|
||||
|
||||
pinctrl_rfkill: rfkillgrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_sai5: sai5grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x94>,
|
||||
<MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x94>,
|
||||
<MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x94>,
|
||||
<MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x94>,
|
||||
<MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x94>;
|
||||
};
|
||||
|
||||
pinctrl_tlv320aic3x04: tlv320aic3x04grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x180>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x14>,
|
||||
<MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x14>,
|
||||
<MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x14>,
|
||||
<MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_uart1_gpio: uart1gpiogrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x80>,
|
||||
<MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x80>,
|
||||
<MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x80>,
|
||||
<MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x80>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x14>,
|
||||
<MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x14>,
|
||||
<MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x14>,
|
||||
<MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x14>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>,
|
||||
<MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>,
|
||||
<MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>;
|
||||
};
|
||||
|
||||
pinctrl_usbhub: usbhubgrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x192>,
|
||||
<MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d2>,
|
||||
<MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d2>,
|
||||
<MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d2>,
|
||||
<MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d2>,
|
||||
<MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d2>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>,
|
||||
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>,
|
||||
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>,
|
||||
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>,
|
||||
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>,
|
||||
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>,
|
||||
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
|
||||
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
|
||||
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
|
||||
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
|
||||
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
|
||||
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
|
||||
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
|
||||
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
|
||||
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
|
||||
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
|
||||
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
|
||||
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
|
||||
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>;
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user