media: i2c: imx214: Move imx214_pll_update to imx214_ctrls_init
It is more logical to call the PLL update in imx214_ctrls_init(). So let's move it there. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: André Apitzsch <git@apitzsch.eu> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
André Apitzsch
committed by
Hans Verkuil
Hans Verkuil
parent
8bd24a43cc
commit
db967cc41f
+110
-109
@@ -881,6 +881,109 @@ static const struct v4l2_ctrl_ops imx214_ctrl_ops = {
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.s_ctrl = imx214_set_ctrl,
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};
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static int imx214_pll_calculate(struct imx214 *imx214, struct ccs_pll *pll,
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unsigned int link_freq)
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{
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struct ccs_pll_limits limits = {
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.min_ext_clk_freq_hz = 6000000,
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.max_ext_clk_freq_hz = 27000000,
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.vt_fr = {
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.min_pre_pll_clk_div = 1,
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.max_pre_pll_clk_div = 15,
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/* Value is educated guess as we don't have a spec */
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.min_pll_ip_clk_freq_hz = 6000000,
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/* Value is educated guess as we don't have a spec */
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.max_pll_ip_clk_freq_hz = 12000000,
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.min_pll_multiplier = 12,
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.max_pll_multiplier = 1200,
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.min_pll_op_clk_freq_hz = 338000000,
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.max_pll_op_clk_freq_hz = 1200000000,
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},
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.vt_bk = {
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.min_sys_clk_div = 2,
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.max_sys_clk_div = 4,
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.min_pix_clk_div = 5,
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.max_pix_clk_div = 10,
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.min_pix_clk_freq_hz = 30000000,
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.max_pix_clk_freq_hz = 120000000,
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},
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.op_bk = {
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.min_sys_clk_div = 1,
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.max_sys_clk_div = 2,
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.min_pix_clk_div = 6,
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.max_pix_clk_div = 10,
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.min_pix_clk_freq_hz = 30000000,
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.max_pix_clk_freq_hz = 120000000,
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},
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.min_line_length_pck_bin = IMX214_PPL_DEFAULT,
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.min_line_length_pck = IMX214_PPL_DEFAULT,
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};
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unsigned int num_lanes = imx214->bus_cfg.bus.mipi_csi2.num_data_lanes;
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/*
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* There are no documented constraints on the sys clock frequency, for
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* either branch. Recover them based on the PLL output clock frequency
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* and sys_clk_div limits on one hand, and the pix clock frequency and
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* the pix_clk_div limits on the other hand.
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*/
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limits.vt_bk.min_sys_clk_freq_hz =
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max(limits.vt_fr.min_pll_op_clk_freq_hz / limits.vt_bk.max_sys_clk_div,
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limits.vt_bk.min_pix_clk_freq_hz * limits.vt_bk.min_pix_clk_div);
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limits.vt_bk.max_sys_clk_freq_hz =
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min(limits.vt_fr.max_pll_op_clk_freq_hz / limits.vt_bk.min_sys_clk_div,
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limits.vt_bk.max_pix_clk_freq_hz * limits.vt_bk.max_pix_clk_div);
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limits.op_bk.min_sys_clk_freq_hz =
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max(limits.vt_fr.min_pll_op_clk_freq_hz / limits.op_bk.max_sys_clk_div,
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limits.op_bk.min_pix_clk_freq_hz * limits.op_bk.min_pix_clk_div);
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limits.op_bk.max_sys_clk_freq_hz =
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min(limits.vt_fr.max_pll_op_clk_freq_hz / limits.op_bk.min_sys_clk_div,
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limits.op_bk.max_pix_clk_freq_hz * limits.op_bk.max_pix_clk_div);
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memset(pll, 0, sizeof(*pll));
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pll->bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY;
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pll->op_lanes = num_lanes;
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pll->vt_lanes = num_lanes;
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pll->csi2.lanes = num_lanes;
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pll->binning_horizontal = 1;
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pll->binning_vertical = 1;
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pll->scale_m = 1;
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pll->scale_n = 1;
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pll->bits_per_pixel =
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IMX214_CSI_DATA_FORMAT_RAW10 & IMX214_BITS_PER_PIXEL_MASK;
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pll->flags = CCS_PLL_FLAG_LANE_SPEED_MODEL;
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pll->link_freq = link_freq;
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pll->ext_clk_freq_hz = clk_get_rate(imx214->xclk);
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return ccs_pll_calculate(imx214->dev, &limits, pll);
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}
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static int imx214_pll_update(struct imx214 *imx214)
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{
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u64 link_freq;
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int ret;
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link_freq = imx214->bus_cfg.link_frequencies[imx214->link_freq->val];
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ret = imx214_pll_calculate(imx214, &imx214->pll, link_freq);
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if (ret) {
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dev_err(imx214->dev, "PLL calculations failed: %d\n", ret);
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return ret;
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}
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ret = v4l2_ctrl_s_ctrl_int64(imx214->pixel_rate,
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imx214->pll.pixel_rate_pixel_array);
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if (ret) {
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dev_err(imx214->dev, "failed to set pixel rate\n");
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return ret;
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}
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return 0;
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}
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static int imx214_ctrls_init(struct imx214 *imx214)
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{
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static const struct v4l2_area unit_size = {
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@@ -1003,6 +1106,13 @@ static int imx214_ctrls_init(struct imx214 *imx214)
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return ret;
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}
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ret = imx214_pll_update(imx214);
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if (ret < 0) {
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v4l2_ctrl_handler_free(ctrl_hdlr);
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dev_err(imx214->dev, "failed to update PLL\n");
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return ret;
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}
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imx214->sd.ctrl_handler = ctrl_hdlr;
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return 0;
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@@ -1115,109 +1225,6 @@ err_rpm_put:
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return ret;
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}
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static int imx214_pll_calculate(struct imx214 *imx214, struct ccs_pll *pll,
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unsigned int link_freq)
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{
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struct ccs_pll_limits limits = {
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.min_ext_clk_freq_hz = 6000000,
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.max_ext_clk_freq_hz = 27000000,
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.vt_fr = {
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.min_pre_pll_clk_div = 1,
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.max_pre_pll_clk_div = 15,
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/* Value is educated guess as we don't have a spec */
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.min_pll_ip_clk_freq_hz = 6000000,
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/* Value is educated guess as we don't have a spec */
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.max_pll_ip_clk_freq_hz = 12000000,
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.min_pll_multiplier = 12,
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.max_pll_multiplier = 1200,
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.min_pll_op_clk_freq_hz = 338000000,
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.max_pll_op_clk_freq_hz = 1200000000,
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},
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.vt_bk = {
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.min_sys_clk_div = 2,
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.max_sys_clk_div = 4,
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.min_pix_clk_div = 5,
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.max_pix_clk_div = 10,
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.min_pix_clk_freq_hz = 30000000,
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.max_pix_clk_freq_hz = 120000000,
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},
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.op_bk = {
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.min_sys_clk_div = 1,
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.max_sys_clk_div = 2,
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.min_pix_clk_div = 6,
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.max_pix_clk_div = 10,
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.min_pix_clk_freq_hz = 30000000,
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.max_pix_clk_freq_hz = 120000000,
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},
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.min_line_length_pck_bin = IMX214_PPL_DEFAULT,
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.min_line_length_pck = IMX214_PPL_DEFAULT,
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};
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unsigned int num_lanes = imx214->bus_cfg.bus.mipi_csi2.num_data_lanes;
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/*
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* There are no documented constraints on the sys clock frequency, for
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* either branch. Recover them based on the PLL output clock frequency
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* and sys_clk_div limits on one hand, and the pix clock frequency and
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* the pix_clk_div limits on the other hand.
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*/
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limits.vt_bk.min_sys_clk_freq_hz =
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max(limits.vt_fr.min_pll_op_clk_freq_hz / limits.vt_bk.max_sys_clk_div,
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limits.vt_bk.min_pix_clk_freq_hz * limits.vt_bk.min_pix_clk_div);
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limits.vt_bk.max_sys_clk_freq_hz =
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min(limits.vt_fr.max_pll_op_clk_freq_hz / limits.vt_bk.min_sys_clk_div,
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limits.vt_bk.max_pix_clk_freq_hz * limits.vt_bk.max_pix_clk_div);
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limits.op_bk.min_sys_clk_freq_hz =
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max(limits.vt_fr.min_pll_op_clk_freq_hz / limits.op_bk.max_sys_clk_div,
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limits.op_bk.min_pix_clk_freq_hz * limits.op_bk.min_pix_clk_div);
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limits.op_bk.max_sys_clk_freq_hz =
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min(limits.vt_fr.max_pll_op_clk_freq_hz / limits.op_bk.min_sys_clk_div,
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limits.op_bk.max_pix_clk_freq_hz * limits.op_bk.max_pix_clk_div);
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memset(pll, 0, sizeof(*pll));
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pll->bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY;
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pll->op_lanes = num_lanes;
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pll->vt_lanes = num_lanes;
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pll->csi2.lanes = num_lanes;
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pll->binning_horizontal = 1;
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pll->binning_vertical = 1;
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pll->scale_m = 1;
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pll->scale_n = 1;
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pll->bits_per_pixel =
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IMX214_CSI_DATA_FORMAT_RAW10 & IMX214_BITS_PER_PIXEL_MASK;
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pll->flags = CCS_PLL_FLAG_LANE_SPEED_MODEL;
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pll->link_freq = link_freq;
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pll->ext_clk_freq_hz = clk_get_rate(imx214->xclk);
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return ccs_pll_calculate(imx214->dev, &limits, pll);
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}
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static int imx214_pll_update(struct imx214 *imx214)
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{
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u64 link_freq;
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int ret;
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link_freq = imx214->bus_cfg.link_frequencies[imx214->link_freq->val];
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ret = imx214_pll_calculate(imx214, &imx214->pll, link_freq);
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if (ret) {
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dev_err(imx214->dev, "PLL calculations failed: %d\n", ret);
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return ret;
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}
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ret = v4l2_ctrl_s_ctrl_int64(imx214->pixel_rate,
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imx214->pll.pixel_rate_pixel_array);
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if (ret) {
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dev_err(imx214->dev, "failed to set pixel rate\n");
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return ret;
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}
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return 0;
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}
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static int imx214_get_frame_interval(struct v4l2_subdev *subdev,
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struct v4l2_subdev_state *sd_state,
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struct v4l2_subdev_frame_interval *fival)
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@@ -1457,12 +1464,6 @@ static int imx214_probe(struct i2c_client *client)
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pm_runtime_set_active(imx214->dev);
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pm_runtime_enable(imx214->dev);
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ret = imx214_pll_update(imx214);
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if (ret < 0) {
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dev_err_probe(dev, ret, "failed to update PLL\n");
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goto error_subdev_cleanup;
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}
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ret = v4l2_async_register_subdev_sensor(&imx214->sd);
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if (ret < 0) {
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dev_err_probe(dev, ret,
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