x86/cacheinfo: Validate CPUID leaf 0x2 EDX output

commit 8177c6bedb upstream.

CPUID leaf 0x2 emits one-byte descriptors in its four output registers
EAX, EBX, ECX, and EDX.  For these descriptors to be valid, the most
significant bit (MSB) of each register must be clear.

The historical Git commit:

  019361a20f016 ("- pre6: Intel: start to add Pentium IV specific stuff (128-byte cacheline etc)...")

introduced leaf 0x2 output parsing.  It only validated the MSBs of EAX,
EBX, and ECX, but left EDX unchecked.

Validate EDX's most-significant bit.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: stable@vger.kernel.org
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/r/20250304085152.51092-2-darwi@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

This commit is contained in:

Ahmed S. Darwish

2025-03-04 09:51:12 +01:00

committed by

Greg Kroah-Hartman

parent 8d1fcb467e

commit db79249be1

1 changed files with 1 additions and 1 deletions

									
										arch/x86/kernel/cpu/cacheinfo.c
									
		+1
		-1
	
												View File
												
				@@ -810,7 +810,7 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c)

							cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);

							/* If bit 31 is set, this is an unknown format */

							for (j = 0 ; j < 3 ; j++)

							for (j = 0 ; j < 4 ; j++)

								if (regs[j] & (1 << 31))

									regs[j] = 0;