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arm64: dts: s32g: add the pinctrl node

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Add the pinctrl node in the device tree in order to enable the
S32G2/S32G3 pinctrl driver to probe.

Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Andrei Stefanescu
2024-07-24 16:24:15 +03:00
committed by Shawn Guo
parent b4167d9757
commit d82a4f5c95
2 changed files with 101 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/freescale/s32g2.dtsi
+50
View File
@@ -114,6 +114,56 @@
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
pinctrl: pinctrl@4009c240 {
compatible = "nxp,s32g2-siul2-pinctrl";
/* MSCR0-MSCR101 registers on siul2_0 */
reg = <0x4009c240 0x198>,
/* MSCR112-MSCR122 registers on siul2_1 */
<0x44010400 0x2c>,
/* MSCR144-MSCR190 registers on siul2_1 */
<0x44010480 0xbc>,
/* IMCR0-IMCR83 registers on siul2_0 */
<0x4009ca40 0x150>,
/* IMCR119-IMCR397 registers on siul2_1 */
<0x44010c1c 0x45c>,
/* IMCR430-IMCR495 registers on siul2_1 */
<0x440110f8 0x108>;
jtag_pins: jtag-pins {
jtag-grp0 {
pinmux = <0x0>;
input-enable;
bias-pull-up;
slew-rate = <166>;
};
jtag-grp1 {
pinmux = <0x11>;
slew-rate = <166>;
};
jtag-grp2 {
pinmux = <0x40>;
input-enable;
bias-pull-down;
slew-rate = <166>;
};
jtag-grp3 {
pinmux = <0x23c0>,
<0x23d0>,
<0x2320>;
};
jtag-grp4 {
pinmux = <0x51>;
input-enable;
bias-pull-up;
slew-rate = <166>;
};
};
};
uart0: serial@401c8000 {
compatible = "nxp,s32g2-linflexuart",
"fsl,s32v234-linflexuart";
arch/arm64/boot/dts/freescale/s32g3.dtsi
+51 -1
View File
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2021-2023 NXP
* Copyright 2021-2024 NXP
*
* Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
* Ciprian Costea <ciprianmarian.costea@nxp.com>
@@ -171,6 +171,56 @@
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
pinctrl: pinctrl@4009c240 {
compatible = "nxp,s32g2-siul2-pinctrl";
/* MSCR0-MSCR101 registers on siul2_0 */
reg = <0x4009c240 0x198>,
/* MSCR112-MSCR122 registers on siul2_1 */
<0x44010400 0x2c>,
/* MSCR144-MSCR190 registers on siul2_1 */
<0x44010480 0xbc>,
/* IMCR0-IMCR83 registers on siul2_0 */
<0x4009ca40 0x150>,
/* IMCR119-IMCR397 registers on siul2_1 */
<0x44010c1c 0x45c>,
/* IMCR430-IMCR495 registers on siul2_1 */
<0x440110f8 0x108>;
jtag_pins: jtag-pins {
jtag-grp0 {
pinmux = <0x0>;
input-enable;
bias-pull-up;
slew-rate = <166>;
};
jtag-grp1 {
pinmux = <0x11>;
slew-rate = <166>;
};
jtag-grp2 {
pinmux = <0x40>;
input-enable;
bias-pull-down;
slew-rate = <166>;
};
jtag-grp3 {
pinmux = <0x23c0>,
<0x23d0>,
<0x2320>;
};
jtag-grp4 {
pinmux = <0x51>;
input-enable;
bias-pull-up;
slew-rate = <166>;
};
};
};
uart0: serial@401c8000 {
compatible = "nxp,s32g3-linflexuart",
"fsl,s32v234-linflexuart";