media: uapi: rk-camera-module: add cmd to get channel info

Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I1a82d1ecce860abd0098404bdee015ced527f5cc
This commit is contained in:
Zefa Chen
2021-09-06 22:12:14 +08:00
committed by Tao Huang
parent 2f002ed1c4
commit d6c2a1cabb
32 changed files with 40 additions and 246 deletions
-5
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@@ -93,11 +93,6 @@ static const char * const gc02m2_supply_names[] = {
#define to_gc02m2(sd) container_of(sd, struct gc02m2, subdev)
enum gc02m2_max_pad {
PAD0,
PAD_MAX,
};
struct regval {
u8 addr;
u8 val;
+7 -9
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@@ -95,11 +95,6 @@ static const char * const gc2053_supply_names[] = {
#define to_gc2053(sd) container_of(sd, struct gc2053, subdev)
enum gc2053_max_pad {
PAD0,
PAD_MAX,
};
struct regval {
u8 addr;
u8 val;
@@ -429,7 +424,7 @@ gc2053_find_best_fit(struct gc2053 *gc2053, struct v4l2_subdev_format *fmt)
return &supported_modes[cur_best_fit];
}
static uint8_t gain_reg_table[29][4] = {
static const uint8_t gain_reg_table[29][4] = {
{0x00, 0x00, 0x01, 0x00},
{0x00, 0x10, 0x01, 0x0c},
{0x00, 0x20, 0x01, 0x1b},
@@ -461,7 +456,7 @@ static uint8_t gain_reg_table[29][4] = {
{0x00, 0xce, 0x3f, 0x3f},
};
static uint32_t gain_level_table[30] = {
static const uint32_t gain_level_table[30] = {
64,
76,
91,
@@ -499,14 +494,17 @@ static int gc2053_set_gain(struct gc2053 *gc2053, u32 gain)
int ret;
uint8_t i = 0;
uint8_t total = 0;
uint8_t temp = 0;
uint32_t temp = 0;
total = sizeof(gain_level_table) / sizeof(u32) - 1;
for (i = 0; i < total; i++) {
for (i = 0; i <= total; i++) {
if ((gain_level_table[i] <= gain) && (gain < gain_level_table[i+1]))
break;
}
if (i > total)
i = total;
ret = gc2053_write_reg(gc2053->client, 0xb4, gain_reg_table[i][0]);
ret |= gc2053_write_reg(gc2053->client, 0xb3, gain_reg_table[i][1]);
ret |= gc2053_write_reg(gc2053->client, 0xb8, gain_reg_table[i][2]);
-8
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@@ -89,14 +89,6 @@ static const char * const gc2093_supply_names[] = {
#define to_gc2093(sd) container_of(sd, struct gc2093, subdev)
enum {
PAD0,
PAD1,
PAD2,
PAD3,
PAD_MAX,
};
enum {
LINK_FREQ_150M_INDEX,
LINK_FREQ_300M_INDEX,
-8
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@@ -99,14 +99,6 @@ static const char * const gc4663_supply_names[] = {
#define GC4663_NUM_SUPPLIES ARRAY_SIZE(gc4663_supply_names)
enum gc4663_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -107,14 +107,6 @@ static const char * const gc4c33_supply_names[] = {
#define GC4C33_NUM_SUPPLIES ARRAY_SIZE(gc4c33_supply_names)
enum gc4c33_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -137,14 +137,6 @@ static const char * const imx334_supply_names[] = {
#define IMX334_NUM_SUPPLIES ARRAY_SIZE(imx334_supply_names)
enum imx334_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -158,14 +158,6 @@ static const char * const imx335_supply_names[] = {
#define IMX335_NUM_SUPPLIES ARRAY_SIZE(imx335_supply_names)
enum imx335_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -149,14 +149,6 @@ static const char * const imx347_supply_names[] = {
#define IMX347_NUM_SUPPLIES ARRAY_SIZE(imx347_supply_names)
enum imx347_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -127,14 +127,6 @@ static const char * const imx378_supply_names[] = {
#define IMX378_NUM_SUPPLIES ARRAY_SIZE(imx378_supply_names)
enum imx378_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -169,14 +169,6 @@ static const char * const imx415_supply_names[] = {
#define IMX415_NUM_SUPPLIES ARRAY_SIZE(imx415_supply_names)
enum imx415_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -93,14 +93,6 @@ struct regval {
u8 val;
};
enum jx_f37_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct jx_f37_mode {
u32 width;
u32 height;
-8
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@@ -84,14 +84,6 @@
#define NVP_RESO_960P_NSTC_VALUE 0xa0
#define NVP_RESO_960P_PAL_VALUE 0xa1
enum nvp6188_max_pad {
PAD0,
PAD1,
PAD2,
PAD3,
PAD_MAX,
};
enum nvp6188_support_reso {
NVP_RESO_UNKOWN = 0,
NVP_RESO_960H_PAL,
-8
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@@ -101,14 +101,6 @@ static const char * const OS02G10_supply_names[] = {
#define OS02G10_NUM_SUPPLIES ARRAY_SIZE(OS02G10_supply_names)
enum os02g10_max_pad {
PAD0,
PAD1,
PAD2,
PAD3,
PAD_MAX,
};
struct regval {
u8 addr;
u8 val;
-8
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@@ -123,14 +123,6 @@ static const char * const os04a10_supply_names[] = {
#define MIRROR_BIT_MASK BIT(1)
#define FLIP_BIT_MASK BIT(2)
enum os04a10_max_pad {
PAD0,
PAD1,
PAD2,
PAD3,
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -106,14 +106,6 @@ static const char * const os05a20_supply_names[] = {
#define MIRROR_BIT_MASK BIT(2)
#define FLIP_BIT_MASK BIT(2)
enum os05a20_max_pad {
PAD0,
PAD1,
PAD2,
PAD3,
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -98,14 +98,6 @@ static const char * const OV02B10_supply_names[] = {
#define OV02B10_NUM_SUPPLIES ARRAY_SIZE(OV02B10_supply_names)
enum ov02b10_max_pad {
PAD0,
PAD1,
PAD2,
PAD3,
PAD_MAX,
};
struct regval {
u8 addr;
u8 val;
-8
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@@ -116,14 +116,6 @@ static const char * const ov02k10_supply_names[] = {
#define OV02K10_NUM_SUPPLIES ARRAY_SIZE(ov02k10_supply_names)
enum ov02k10_max_pad {
PAD0,
PAD1,
PAD2,
PAD3,
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -117,14 +117,6 @@ static const char * const ov12d2q_supply_names[] = {
#define MIRROR_BIT_MASK BIT(2)
#define FLIP_BIT_MASK BIT(2)
enum ov12d2q_max_pad {
PAD0,
PAD1,
PAD2,
PAD3,
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -110,14 +110,6 @@
#define OV2718_NAME "ov2718"
enum ov2718_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct ov2718_gpio {
int pltfrm_gpio;
const char *label;
-8
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@@ -94,14 +94,6 @@
#define OV2775_NAME "ov2775"
enum ov2775_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct ov2775_gpio {
int pltfrm_gpio;
const char *label;
-8
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@@ -104,14 +104,6 @@ static const char * const OV4686_supply_names[] = {
#define OV4686_NUM_SUPPLIES ARRAY_SIZE(OV4686_supply_names)
enum OV4686_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -103,14 +103,6 @@ static const char * const ov4688_supply_names[] = {
#define OV4688_NUM_SUPPLIES ARRAY_SIZE(ov4688_supply_names)
enum ov4688_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -106,14 +106,6 @@ static const char * const ov4689_supply_names[] = {
#define OV4689_NUM_SUPPLIES ARRAY_SIZE(ov4689_supply_names)
enum ov4689_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -125,14 +125,6 @@ static const char * const sc200ai_supply_names[] = {
#define SC200AI_NUM_SUPPLIES ARRAY_SIZE(sc200ai_supply_names)
enum sc200ai_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -88,14 +88,6 @@ static const char * const sc210iot_supply_names[] = {
#define to_sc210iot(sd) container_of(sd, struct sc210iot, subdev)
enum {
PAD0,
PAD1,
PAD2,
PAD3,
PAD_MAX,
};
enum {
LINK_FREQ_INDEX,
};
-8
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@@ -93,14 +93,6 @@ static const char * const sc2232_supply_names[] = {
#define SC2232_NUM_SUPPLIES ARRAY_SIZE(sc2232_supply_names)
enum sc2232_max_pad {
PAD0,
PAD1,
PAD2,
PAD3,
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -121,14 +121,6 @@ static const char * const sc2310_supply_names[] = {
#define SC2310_NUM_SUPPLIES ARRAY_SIZE(sc2310_supply_names)
enum sc2310_max_pad {
PAD0,
PAD1,
PAD2,
PAD3,
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -114,14 +114,6 @@ static const char * const sc4238_supply_names[] = {
#define MIRROR_BIT_MASK (BIT(1) | BIT(2))
#define FLIP_BIT_MASK (BIT(6) | BIT(5))
enum sc4238_max_pad {
PAD0,
PAD1,
PAD2,
PAD3,
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -113,14 +113,6 @@ static const char * const sc430cs_supply_names[] = {
#define SC430CS_NUM_SUPPLIES ARRAY_SIZE(sc430cs_supply_names)
enum sc430cs_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -123,14 +123,6 @@ static const char * const sc500ai_supply_names[] = {
#define sc500ai_NUM_SUPPLIES ARRAY_SIZE(sc500ai_supply_names)
enum sc500ai_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
struct regval {
u16 addr;
u8 val;
-8
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@@ -49,14 +49,6 @@
#define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
#define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
enum tp2855_max_pad {
PAD0,
PAD1,
PAD2,
PAD3,
PAD_MAX,
};
enum{
CH_1=0,
CH_2=1,
+33
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@@ -104,6 +104,9 @@
#define RKMODULE_GET_SONY_BRL \
_IOR('V', BASE_VIDIOC_PRIVATE + 19, __u32)
#define RKMODULE_GET_CHANNEL_INFO \
_IOR('V', BASE_VIDIOC_PRIVATE + 20, struct rkmodule_channel_info)
/**
* struct rkmodule_base_inf - module base information
*
@@ -434,4 +437,34 @@ struct rkmodule_dcg_ratio {
__u32 div_coeff;
};
struct rkmodule_channel_info {
__u32 index;
__u32 vc;
__u32 width;
__u32 height;
__u32 bus_fmt;
} __attribute__ ((packed));
/*
* link to vicap
* linear mode: pad0~pad3 for id0~id3;
*
* HDR_X2: id0 fiexd to vc0 for long frame
* id1 fixed to vc1 for short frame;
* id2~id3 reserved, can config by PAD2~PAD3
*
* HDR_X3: id0 fiexd to vc0 for long frame
* id1 fixed to vc1 for middle frame
* id2 fixed to vc2 for short frame;
* id3 reserved, can config by PAD3
*
* link to isp, the connection relationship is as follows
*/
enum rkmodule_max_pad {
PAD0, /* link to isp */
PAD1, /* link to csi wr0 | hdr x2:L x3:M */
PAD2, /* link to csi wr1 | hdr x3:L */
PAD3, /* link to csi wr2 | hdr x2:M x3:S */
PAD_MAX,
};
#endif /* _UAPI_RKMODULE_CAMERA_H */