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phy: rockchip: mipi csi2 dphy fixes grf write error of val for lane select

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Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: Id56eb83d9a25c15b9d611232e6f82221a55c7e64
This commit is contained in:
Zefa Chen
2023-05-19 09:35:01 +08:00
parent 9dc517e0fd
commit d48ecfc5f7
1 changed files with 1 additions and 1 deletions
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drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c
+1 -1
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@@ -572,7 +572,7 @@ static void csi2_dphy_config_dual_mode(struct csi2_dphy *dphy,
is_cif = false;
if (hw->lane_mode == LANE_MODE_FULL) {
val = ~GRF_CSI2PHY_LANE_SEL_SPLIT;
val = !GRF_CSI2PHY_LANE_SEL_SPLIT;
if (dphy->phy_index < 3) {
write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
GENMASK(sensor->lanes - 1, 0));