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Revert "clk: rockchip: rk3588: export clk_gmac id"

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This reverts commit de8a7dc11e.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I10be8115666498baf872a40fc9c72964744f3243
This commit is contained in:
Elaine Zhang
2021-11-02 10:38:45 +08:00
committed by Tao Huang
parent d6cb203817
commit d3a274cb5e
2 changed files with 0 additions and 8 deletions
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drivers/clk/rockchip/clk-rk3588.c
-6
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@@ -13,7 +13,6 @@
#include <dt-bindings/clock/rk3588-cru.h>
#include "clk.h"
#define RK3588_PHPGRF_CLK_CON1 0x70
#define RK3588_GRF_SOC_STATUS0 0x600
#define RK3588_FRAC_MAX_PRATE 600000000
#define RK3588_UART_FRAC_MAX_PRATE 600000000
@@ -499,7 +498,6 @@ PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
PNAME(clk_ref_pipe_phy0_p) = { "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" };
PNAME(clk_ref_pipe_phy1_p) = { "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" };
PNAME(clk_ref_pipe_phy2_p) = { "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" };
PNAME(mux_clk_gmac_p) = { "clk_gmac_125m", "clk_gmac_50m" };
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
@@ -1459,10 +1457,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(CLK_GMAC_50M, "clk_gmac_50m", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(84), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3588_CLKGATE_CON(35), 6, GFLAGS),
MUXGRF(CLK_GMAC0, "clk_gmac0", mux_clk_gmac_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3588_PHPGRF_CLK_CON1, 0, 1, MFLAGS),
MUXGRF(CLK_GMAC1, "clk_gmac1", mux_clk_gmac_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3588_PHPGRF_CLK_CON1, 5, 1, MFLAGS),
GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", 0,
RK3588_CLKGATE_CON(34), 6, GFLAGS),
include/dt-bindings/clock/rk3588-cru.h
-2
View File
@@ -684,8 +684,6 @@
#define PCLK_PMU1WDT 688
#define TCLK_PMU1WDT 689
#define CLK_CR_PARA 690
#define CLK_GMAC0 691
#define CLK_GMAC1 692
#define CLK_USB2PHY_HDPTXRXPHY_REF 693
#define CLK_USBDPPHY_MIPIDCPPHY_REF 694
#define CLK_REF_PIPE_PHY0_OSC_SRC 695