PM / devfreq: rockchip_bus: remove the autocs keyword.

1、remove the autocs keyword.
2、use cfg-val instead of timer-us in rk1808.dtsi
3、remove bus-soc node in px30.dtsi

Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Change-Id: I0f4563476ad7e08ba8dd9d02097eb4448d024ecd

arch/arm64/boot/dts/rockchip/px30.dtsi

@@ -236,29 +236,6 @@
 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 	};
 
-	bus_soc: bus-soc {
-		compatible = "rockchip,px30-bus";
-		rockchip,busfreq-policy = "autocs";
-		soc-bus0 {
-			bus-id = <0>;
-			timer-us = <20>;
-			enable-msk = <0x40f7>;
-			status = "disabled";
-		};
-		soc-bus1 {
-			bus-id = <1>;
-			timer-us = <200>;
-			enable-msk = <0x40bf>;
-			status = "disabled";
-		};
-		soc-bus2 {
-			bus-id = <2>;
-			timer-us = <200>;
-			enable-msk = <0x4007>;
-			status = "disabled";
-		};
-	};
-
 	bus_apll: bus-apll {
 		compatible = "rockchip,px30-bus";
 		rockchip,busfreq-policy = "clkfreq";

arch/arm64/boot/dts/rockchip/rk1808.dtsi

@@ -207,34 +207,34 @@
 
 	bus_soc: bus-soc {
 		compatible = "rockchip,rk1808-bus";
-		rockchip,busfreq-policy = "autocs";
+		rockchip,busfreq-policy = "smc";
 		soc-bus0 {
 			bus-id = <0>;
-			timer-us = <20>;
+			cfg-val = <0x1e0>;
 			enable-msk = <0x407f>;
 			status = "okay";
 		};
 		soc-bus1 {
 			bus-id = <1>;
-			timer-us = <200>;
+			cfg-val = <0x12c0>;
 			enable-msk = <0x41ff>;
 			status = "okay";
 		};
 		soc-bus2 {
 			bus-id = <2>;
-			timer-us = <200>;
+			cfg-val = <0x12c0>;
 			enable-msk = <0x4005>;
 			status = "okay";
 		};
 		soc-bus3 {
 			bus-id = <3>;
-			timer-us = <200>;
+			cfg-val = <0x12c0>;
 			enable-msk = <0x4001>;
 			status = "okay";
 		};
 		soc-bus4 {
 			bus-id = <4>;
-			timer-us = <200>;
+			cfg-val = <0x12c0>;
 			enable-msk = <0x4001>;
 			status = "disabled";
 		};

drivers/devfreq/rockchip_bus.c

@@ -57,21 +57,22 @@ struct rockchip_bus {
 	unsigned int cpu_freq[MAX_CLUSTERS];
 };
 
-static int rockchip_sip_soc_bus_div(u32 bus_id, u32 timer, u32 enable_msk)
+static int rockchip_sip_bus_smc_config(u32 bus_id, u32 cfg, u32 enable_msk)
 {
 	struct arm_smccc_res res;
 
-	res = sip_smc_soc_bus_div(bus_id, timer, enable_msk);
+	res = sip_smc_bus_config(bus_id, cfg, enable_msk);
 
 	return res.a0;
 }
 
-static int rockchip_bus_autocs(struct rockchip_bus *bus)
+static int rockchip_bus_smc_config(struct rockchip_bus *bus)
 {
 	struct device *dev = bus->dev;
 	struct device_node *np = dev->of_node;
 	struct device_node *child;
-	int ret, enable_msk, bus_id, sip_timer;
+	unsigned int enable_msk, bus_id, cfg;
+	int ret;
 
 	for_each_available_child_of_node(np, child) {
 		ret = of_property_read_u32_index(child, "bus-id", 0,
@@ -79,15 +80,15 @@ static int rockchip_bus_autocs(struct rockchip_bus *bus)
 		if (ret)
 			continue;
 
-		ret = of_property_read_u32_index(child, "timer-us", 0,
-						 &sip_timer);
+		ret = of_property_read_u32_index(child, "cfg-val", 0,
+						 &cfg);
 		if (ret) {
-			dev_info(dev, "get timer_us error\n");
+			dev_info(dev, "get cfg-val error\n");
 			continue;
 		}
 
-		if (!sip_timer) {
-			dev_info(dev, "timer_us invalid\n");
+		if (!cfg) {
+			dev_info(dev, "cfg-val invalid\n");
 			continue;
 		}
 
@@ -98,10 +99,10 @@ static int rockchip_bus_autocs(struct rockchip_bus *bus)
 			continue;
 		}
 
-		ret = rockchip_sip_soc_bus_div(bus_id, sip_timer,
-					       enable_msk);
-		if (ret == -2) {
-			dev_info(dev, "smc sip not support! %x\n", ret);
+		ret = rockchip_sip_bus_smc_config(bus_id, cfg,
+						  enable_msk);
+		if (ret) {
+			dev_info(dev, "bus smc config error: %x!\n", ret);
 			break;
 		}
 	}
@@ -471,8 +472,8 @@ static int rockchip_busfreq_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	if (!strcmp(policy_name, "autocs"))
-		ret = rockchip_bus_autocs(bus);
+	if (!strcmp(policy_name, "smc"))
+		ret = rockchip_bus_smc_config(bus);
 	else if (!strcmp(policy_name, "clkfreq"))
 		ret = rockchip_bus_clkfreq(bus);
 	else if (!strcmp(policy_name, "cpufreq"))

drivers/firmware/rockchip_sip.c

@@ -145,11 +145,11 @@ struct arm_smccc_res sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2)
 }
 EXPORT_SYMBOL_GPL(sip_smc_vpu_reset);
 
-struct arm_smccc_res sip_smc_soc_bus_div(u32 arg0, u32 arg1, u32 arg2)
+struct arm_smccc_res sip_smc_bus_config(u32 arg0, u32 arg1, u32 arg2)
 {
 	struct arm_smccc_res res;
 
-	res = __invoke_sip_fn_smc(RK_SIP_SOC_BUS_DIV, arg0, arg1, arg2);
+	res = __invoke_sip_fn_smc(SIP_BUS_CFG, arg0, arg1, arg2);
 	return res;
 }
 

include/linux/rockchip/rockchip_sip.h

@@ -31,7 +31,7 @@
 #define SIP_SIP_VERSION			0x8200000a
 #define SIP_REMOTECTL_CFG		0x8200000b
 #define PSCI_SIP_VPU_RESET		0x8200000c
-#define RK_SIP_SOC_BUS_DIV		0x8200000d
+#define SIP_BUS_CFG			0x8200000d
 #define SIP_LAST_LOG			0x8200000e
 
 /* Rockchip Sip version */
@@ -129,7 +129,7 @@ int sip_smc_remotectl_config(u32 func, u32 data);
 
 int sip_smc_secure_reg_write(u32 addr_phy, u32 val);
 u32 sip_smc_secure_reg_read(u32 addr_phy);
-struct arm_smccc_res sip_smc_soc_bus_div(u32 arg0, u32 arg1, u32 arg2);
+struct arm_smccc_res sip_smc_bus_config(u32 arg0, u32 arg1, u32 arg2);
 
 /***************************fiq debugger **************************************/
 void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu);