drm/amdkfd: fix cu mask for asics with wgps
GFX10 and up have work group processors (WGP) and WGP mode is the native compile mode. KFD and ROCr have no visibility into whether a dispatch is operating in CU or WGP mode. Enforce CU masking to be pairwise continguous in enablement and round robin distribute CUs across the SEs in a pairwise manner to assume WGP mode at all times. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
committed by
Alex Deucher
parent
6a4a1f6054
commit
cff35798fa
@@ -100,7 +100,9 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
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{
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struct kfd_cu_info cu_info;
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uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0};
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int i, se, sh, cu, cu_bitmap_sh_mul;
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bool wgp_mode_req = KFD_GC_VERSION(mm->dev) >= IP_VERSION(10, 0, 0);
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uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1;
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int i, se, sh, cu, cu_bitmap_sh_mul, inc = wgp_mode_req ? 2 : 1;
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amdgpu_amdkfd_get_cu_info(mm->dev->adev, &cu_info);
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@@ -167,13 +169,13 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
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se_mask[i] = 0;
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i = 0;
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for (cu = 0; cu < 16; cu++) {
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for (cu = 0; cu < 16; cu += inc) {
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for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) {
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for (se = 0; se < cu_info.num_shader_engines; se++) {
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if (cu_per_sh[se][sh] > cu) {
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if (cu_mask[i / 32] & (1 << (i % 32)))
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se_mask[se] |= 1 << (cu + sh * 16);
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i++;
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if (cu_mask[i / 32] & (en_mask << (i % 32)))
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se_mask[se] |= en_mask << (cu + sh * 16);
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i += inc;
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if (i == cu_mask_count)
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return;
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}
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@@ -498,6 +498,21 @@ int pqm_update_mqd(struct process_queue_manager *pqm,
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return -EFAULT;
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}
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/* ASICs that have WGPs must enforce pairwise enabled mask checks. */
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if (minfo && minfo->update_flag == UPDATE_FLAG_CU_MASK && minfo->cu_mask.ptr &&
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KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0)) {
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int i;
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for (i = 0; i < minfo->cu_mask.count; i += 2) {
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uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3;
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if (cu_pair && cu_pair != 0x3) {
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pr_debug("CUs must be adjacent pairwise enabled.\n");
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return -EINVAL;
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}
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}
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}
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retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
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pqn->q, minfo);
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if (retval != 0)
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