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spi: tegra210-quad: modify chip select (CS) deactivation

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[ Upstream commit d8966b6541 ]

Modify the chip select (CS) deactivation and inter-transfer delay
execution only during the DATA_TRANSFER phase when the cs_change
flag is not set. This ensures proper CS handling and timing between
transfers while eliminating redundant operations.

Fixes: 1b8342cc4a ("spi: tegra210-quad: combined sequence mode")
Signed-off-by: Vishwaroop A <va@nvidia.com>
Link: https://patch.msgid.link/20250416110606.2737315-4-va@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Vishwaroop A
2025-04-16 11:06:03 +00:00
committed by Greg Kroah-Hartman
parent 41de2c9e30
commit c6c1422679
1 changed files with 4 additions and 4 deletions
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drivers/spi/spi-tegra210-quad.c
+4 -4
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@@ -1159,16 +1159,16 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
ret = -EIO;
goto exit;
}
if (!xfer->cs_change) {
tegra_qspi_transfer_end(spi);
spi_transfer_delay_exec(xfer);
}
break;
default:
ret = -EINVAL;
goto exit;
}
msg->actual_length += xfer->len;
if (!xfer->cs_change && transfer_phase == DATA_TRANSFER) {
tegra_qspi_transfer_end(spi);
spi_transfer_delay_exec(xfer);
}
transfer_phase++;
}
ret = 0;