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Merge fc80c51fd4 ("Merge tag 'kbuild-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild") into android-mainline

Browse Source 
Steps on the way to 5.9-rc1

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I75b7f1589f230e546c0f2103456fd725c8866460
This commit is contained in:
Greg Kroah-Hartman
2020-08-10 10:48:14 +02:00
parent c630edbf79 fc80c51fd4
commit c592c07327
263 changed files with 12180 additions and 3138 deletions
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Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
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@@ -0,0 +1,252 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings
description: |
The FMC2 functional block makes the interface with: synchronous and
asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
peripherals) and NAND flash memories.
Its main purposes are:
- to translate AXI transactions into the appropriate external device
protocol
- to meet the access time requirements of the external devices
All external devices share the addresses, data and control signals with the
controller. Each external device is accessed by means of a unique Chip
Select. The FMC2 performs only one access at a time to an external device.
maintainers:
- Christophe Kerello <christophe.kerello@st.com>
properties:
compatible:
const: st,stm32mp1-fmc2-ebi
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
"#address-cells":
const: 2
"#size-cells":
const: 1
ranges:
description: |
Reflects the memory layout with four integer values per bank. Format:
<bank-number> 0 <address of the bank> <size>
patternProperties:
"^.*@[0-4],[a-f0-9]+$":
type: object
properties:
reg:
description: Bank number, base address and size of the device.
st,fmc2-ebi-cs-transaction-type:
description: |
Select one of the transactions type supported
0: Asynchronous mode 1 SRAM/FRAM.
1: Asynchronous mode 1 PSRAM.
2: Asynchronous mode A SRAM/FRAM.
3: Asynchronous mode A PSRAM.
4: Asynchronous mode 2 NOR.
5: Asynchronous mode B NOR.
6: Asynchronous mode C NOR.
7: Asynchronous mode D NOR.
8: Synchronous read synchronous write PSRAM.
9: Synchronous read asynchronous write PSRAM.
10: Synchronous read synchronous write NOR.
11: Synchronous read asynchronous write NOR.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 11
st,fmc2-ebi-cs-cclk-enable:
description: Continuous clock enable (first bank must be configured
in synchronous mode). The FMC_CLK is generated continuously
during asynchronous and synchronous access. By default, the
FMC_CLK is only generated during synchronous access.
$ref: /schemas/types.yaml#/definitions/flag
st,fmc2-ebi-cs-mux-enable:
description: Address/Data multiplexed on databus (valid only with
NOR and PSRAM transactions type). By default, Address/Data
are not multiplexed.
$ref: /schemas/types.yaml#/definitions/flag
st,fmc2-ebi-cs-buswidth:
description: Data bus width
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 8, 16 ]
default: 16
st,fmc2-ebi-cs-waitpol-high:
description: Wait signal polarity (NWAIT signal active high).
By default, NWAIT is active low.
$ref: /schemas/types.yaml#/definitions/flag
st,fmc2-ebi-cs-waitcfg-enable:
description: The NWAIT signal indicates wheither the data from the
device are valid or if a wait state must be inserted when accessing
the device in synchronous mode. By default, the NWAIT signal is
active one data cycle before wait state.
$ref: /schemas/types.yaml#/definitions/flag
st,fmc2-ebi-cs-wait-enable:
description: The NWAIT signal is enabled (its level is taken into
account after the programmed latency period to insert wait states
if asserted). By default, the NWAIT signal is disabled.
$ref: /schemas/types.yaml#/definitions/flag
st,fmc2-ebi-cs-asyncwait-enable:
description: The NWAIT signal is taken into account during asynchronous
transactions. By default, the NWAIT signal is not taken into account
during asynchronous transactions.
$ref: /schemas/types.yaml#/definitions/flag
st,fmc2-ebi-cs-cpsize:
description: CRAM page size. The controller splits the burst access
when the memory page is reached. By default, no burst split when
crossing page boundary.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 128, 256, 512, 1024 ]
default: 0
st,fmc2-ebi-cs-byte-lane-setup-ns:
description: This property configures the byte lane setup timing
defined in nanoseconds from NBLx low to Chip Select NEx low.
st,fmc2-ebi-cs-address-setup-ns:
description: This property defines the duration of the address setup
phase in nanoseconds used for asynchronous read/write transactions.
st,fmc2-ebi-cs-address-hold-ns:
description: This property defines the duration of the address hold
phase in nanoseconds used for asynchronous multiplexed read/write
transactions.
st,fmc2-ebi-cs-data-setup-ns:
description: This property defines the duration of the data setup phase
in nanoseconds used for asynchronous read/write transactions.
st,fmc2-ebi-cs-bus-turnaround-ns:
description: This property defines the delay in nanoseconds between the
end of current read/write transaction and the next transaction.
st,fmc2-ebi-cs-data-hold-ns:
description: This property defines the duration of the data hold phase
in nanoseconds used for asynchronous read/write transactions.
st,fmc2-ebi-cs-clk-period-ns:
description: This property defines the FMC_CLK output signal period in
nanoseconds.
st,fmc2-ebi-cs-data-latency-ns:
description: This property defines the data latency before reading or
writing the first data in nanoseconds.
st,fmc2_ebi-cs-write-address-setup-ns:
description: This property defines the duration of the address setup
phase in nanoseconds used for asynchronous write transactions.
st,fmc2-ebi-cs-write-address-hold-ns:
description: This property defines the duration of the address hold
phase in nanoseconds used for asynchronous multiplexed write
transactions.
st,fmc2-ebi-cs-write-data-setup-ns:
description: This property defines the duration of the data setup
phase in nanoseconds used for asynchronous write transactions.
st,fmc2-ebi-cs-write-bus-turnaround-ns:
description: This property defines the delay between the end of current
write transaction and the next transaction in nanoseconds.
st,fmc2-ebi-cs-write-data-hold-ns:
description: This property defines the duration of the data hold phase
in nanoseconds used for asynchronous write transactions.
st,fmc2-ebi-cs-max-low-pulse-ns:
description: This property defines the maximum chip select low pulse
duration in nanoseconds for synchronous transactions. When this timing
reaches 0, the controller splits the current access, toggles NE to
allow device refresh and restarts a new access.
required:
- reg
required:
- "#address-cells"
- "#size-cells"
- compatible
- reg
- clocks
- ranges
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
memory-controller@58002000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "st,stm32mp1-fmc2-ebi";
reg = <0x58002000 0x1000>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
<4 0 0x80000000 0x10000000>; /* NAND */
psram@0,0 {
compatible = "mtd-ram";
reg = <0 0x00000000 0x100000>;
bank-width = <2>;
st,fmc2-ebi-cs-transaction-type = <1>;
st,fmc2-ebi-cs-address-setup-ns = <60>;
st,fmc2-ebi-cs-data-setup-ns = <30>;
st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
};
nand-controller@4,0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp1-fmc2-nfc";
reg = <4 0x00000000 0x1000>,
<4 0x08010000 0x1000>,
<4 0x08020000 0x1000>,
<4 0x01000000 0x1000>,
<4 0x09010000 0x1000>,
<4 0x09020000 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
<&mdma1 20 0x2 0x12000a08 0x0 0x0>,
<&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
dma-names = "tx", "rx", "ecc";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
};
};
};
...
Documentation/devicetree/bindings/mtd/davinci-nand.txt
+2 -2
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@@ -4,8 +4,8 @@ This file provides information, what the device node for the davinci/keystone
NAND interface contains.
Documentation:
Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
Required properties:
Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
+5 -5
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@@ -7,14 +7,16 @@ Required properties:
- fsl,upm-cmd-offset : UPM pattern offset for the command latch.
Optional properties:
- fsl,upm-wait-flags : add chip-dependent short delays after running the
UPM pattern (0x1), after writing a data byte (0x2) or after
writing out a buffer (0x4).
- fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
The corresponding address lines are used to select the chip.
- gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
(R/B#). For multi-chip devices, "n" GPIO definitions are required
according to the number of chips.
Deprecated properties:
- fsl,upm-wait-flags : add chip-dependent short delays after running the
UPM pattern (0x1), after writing a data byte (0x2) or after
writing out a buffer (0x4).
- chip-delay : chip dependent delay for transferring data from array to
read registers (tR). Required if property "gpios" is not used
(R/B# pins not connected).
@@ -52,8 +54,6 @@ upm@3,0 {
fsl,upm-cmd-offset = <0x08>;
/* Multi-chip NAND device */
fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
fsl,upm-wait-flags = <0x5>;
chip-delay = <25>; // in micro-seconds
nand@0 {
#address-cells = <1>;
Documentation/devicetree/bindings/mtd/nand-controller.yaml
+7
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@@ -114,6 +114,13 @@ patternProperties:
description:
Contains the native Ready/Busy IDs.
rb-gpios:
description:
Contains one or more GPIO descriptor (the numper of descriptor
depends on the number of R/B pins exposed by the flash) for the
Ready/Busy pins. Active state refers to the NAND ready state and
should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
required:
- reg
Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
+57 -26
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@@ -9,32 +9,19 @@ title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings
maintainers:
- Christophe Kerello <christophe.kerello@st.com>
allOf:
- $ref: "nand-controller.yaml#"
properties:
compatible:
const: st,stm32mp15-fmc2
enum:
- st,stm32mp15-fmc2
- st,stm32mp1-fmc2-nfc
reg:
items:
- description: Registers
- description: Chip select 0 data
- description: Chip select 0 command
- description: Chip select 0 address space
- description: Chip select 1 data
- description: Chip select 1 command
- description: Chip select 1 address space
minItems: 6
maxItems: 7
interrupts:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
dmas:
items:
- description: tx DMA channel
@@ -57,11 +44,55 @@ patternProperties:
nand-ecc-strength:
enum: [1, 4 ,8 ]
allOf:
- $ref: "nand-controller.yaml#"
- if:
properties:
compatible:
contains:
const: st,stm32mp15-fmc2
then:
properties:
reg:
items:
- description: Registers
- description: Chip select 0 data
- description: Chip select 0 command
- description: Chip select 0 address space
- description: Chip select 1 data
- description: Chip select 1 command
- description: Chip select 1 address space
clocks:
maxItems: 1
resets:
maxItems: 1
required:
- clocks
- if:
properties:
compatible:
contains:
const: st,stm32mp1-fmc2-nfc
then:
properties:
reg:
items:
- description: Chip select 0 data
- description: Chip select 0 command
- description: Chip select 0 address space
- description: Chip select 1 data
- description: Chip select 1 command
- description: Chip select 1 address space
required:
- compatible
- reg
- interrupts
- clocks
examples:
- |
@@ -77,13 +108,13 @@ examples:
<0x81000000 0x1000>,
<0x89010000 0x1000>,
<0x89020000 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
<&mdma1 20 0x10 0x12000a08 0x0 0x0>,
<&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
dma-names = "tx", "rx", "ecc";
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
<&mdma1 20 0x2 0x12000a08 0x0 0x0>,
<&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
dma-names = "tx", "rx", "ecc";
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
#address-cells = <1>;
#size-cells = <0>;
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
-81
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@@ -1,81 +0,0 @@
Ingenic XBurst pin controller
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may
be used as GPIOs, multiplexed device functions are configured within the
GPIO port configuration registers and it is typical to refer to pins using the
naming scheme "PxN" where x is a character identifying the GPIO port with
which the pin is associated and N is an integer from 0 to 31 identifying the
pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
Required properties:
--------------------
- compatible: One of:
- "ingenic,jz4740-pinctrl"
- "ingenic,jz4725b-pinctrl"
- "ingenic,jz4760-pinctrl"
- "ingenic,jz4760b-pinctrl"
- "ingenic,jz4770-pinctrl"
- "ingenic,jz4780-pinctrl"
- "ingenic,x1000-pinctrl"
- "ingenic,x1000e-pinctrl"
- "ingenic,x1500-pinctrl"
- "ingenic,x1830-pinctrl"
- reg: Address range of the pinctrl registers.
Required properties for sub-nodes (GPIO chips):
-----------------------------------------------
- compatible: Must contain one of:
- "ingenic,jz4740-gpio"
- "ingenic,jz4760-gpio"
- "ingenic,jz4770-gpio"
- "ingenic,jz4780-gpio"
- "ingenic,x1000-gpio"
- "ingenic,x1830-gpio"
- reg: The GPIO bank number.
- interrupt-controller: Marks the device node as an interrupt controller.
- interrupts: Interrupt specifier for the controllers interrupt.
- #interrupt-cells: Should be 2. Refer to
../interrupt-controller/interrupts.txt for more details.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the second
cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
- gpio-ranges: Range of pins managed by the GPIO controller. Refer to
../gpio/gpio.txt for more details.
Example:
--------
pinctrl: pin-controller@10010000 {
compatible = "ingenic,jz4740-pinctrl";
reg = <0x10010000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
gpa: gpio@0 {
compatible = "ingenic,jz4740-gpio";
reg = <0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <28>;
};
};
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
+176
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@@ -0,0 +1,176 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ingenic,pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ingenic SoCs pin controller devicetree bindings
description: >
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
For the Ingenic SoCs, pin control is tightly bound with GPIO ports. All pins
may be used as GPIOs, multiplexed device functions are configured within the
GPIO port configuration registers and it is typical to refer to pins using the
naming scheme "PxN" where x is a character identifying the GPIO port with
which the pin is associated and N is an integer from 0 to 31 identifying the
pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
and PB31 is the last pin in GPIO port B. The JZ4740, the X1000 and the X1830
contains 4 GPIO ports, PA to PD, for a total of 128 pins. The JZ4760, the
JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a total of 192
pins.
maintainers:
- Paul Cercueil <paul@crapouillou.net>
properties:
nodename:
pattern: "^pinctrl@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- ingenic,jz4740-pinctrl
- ingenic,jz4725b-pinctrl
- ingenic,jz4760-pinctrl
- ingenic,jz4770-pinctrl
- ingenic,jz4780-pinctrl
- ingenic,x1000-pinctrl
- ingenic,x1500-pinctrl
- ingenic,x1830-pinctrl
- items:
- const: ingenic,jz4760b-pinctrl
- const: ingenic,jz4760-pinctrl
- items:
- const: ingenic,x1000e-pinctrl
- const: ingenic,x1000-pinctrl
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^gpio@[0-9]$":
type: object
properties:
compatible:
enum:
- ingenic,jz4740-gpio
- ingenic,jz4725b-gpio
- ingenic,jz4760-gpio
- ingenic,jz4770-gpio
- ingenic,jz4780-gpio
- ingenic,x1000-gpio
- ingenic,x1500-gpio
- ingenic,x1830-gpio
reg:
items:
- description: The GPIO bank number
gpio-controller: true
"#gpio-cells":
const: 2
gpio-ranges:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 2
description:
Refer to ../interrupt-controller/interrupts.txt for more details.
interrupts:
maxItems: 1
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- interrupts
- interrupt-controller
- "#interrupt-cells"
additionalProperties: false
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
properties:
phandle: true
function: true
groups: true
pins: true
bias-disable: true
bias-pull-up: true
bias-pull-down: true
output-low: true
output-high: true
additionalProperties: false
- type: object
properties:
phandle: true
additionalProperties:
type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
properties:
phandle: true
function: true
groups: true
pins: true
bias-disable: true
bias-pull-up: true
bias-pull-down: true
output-low: true
output-high: true
additionalProperties: false
examples:
- |
pin-controller@10010000 {
compatible = "ingenic,jz4770-pinctrl";
reg = <0x10010000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
gpio@0 {
compatible = "ingenic,jz4770-gpio";
reg = <0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <17>;
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
+202
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@@ -0,0 +1,202 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT6779 Pin Controller Device Tree Bindings
maintainers:
- Andy Teng <andy.teng@mediatek.com>
description: |+
The pin controller node should be the child of a syscon node with the
required property:
- compatible: "syscon"
properties:
compatible:
const: mediatek,mt6779-pinctrl
reg:
minItems: 9
maxItems: 9
reg-names:
items:
- const: "gpio"
- const: "iocfg_rm"
- const: "iocfg_br"
- const: "iocfg_lm"
- const: "iocfg_lb"
- const: "iocfg_rt"
- const: "iocfg_lt"
- const: "iocfg_tl"
- const: "eint"
gpio-controller: true
"#gpio-cells":
const: 2
description: |
Number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
gpio-ranges:
minItems: 1
maxItems: 5
description: |
GPIO valid number range.
interrupt-controller: true
interrupts:
maxItems: 1
description: |
Specifies the summary IRQ.
"#interrupt-cells":
const: 2
required:
- compatible
- reg
- reg-names
- gpio-controller
- "#gpio-cells"
- gpio-ranges
- interrupt-controller
- interrupts
- "#interrupt-cells"
patternProperties:
'-[0-9]*$':
type: object
patternProperties:
'-pins*$':
type: object
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input schmitt.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pinmux:
description:
integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in boot/dts/<soc>-pinfunc.h directly.
bias-disable: true
bias-pull-up: true
bias-pull-down: true
input-enable: true
input-disable: true
output-low: true
output-high: true
input-schmitt-enable: true
input-schmitt-disable: true
mediatek,pull-up-adv:
description: |
Pull up setings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,pull-down-adv:
description: |
Pull down settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
required:
- pinmux
additionalProperties: false
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt6779-pinfunc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pio: pinctrl@10005000 {
compatible = "mediatek,mt6779-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11c20000 0 0x1000>,
<0 0x11d10000 0 0x1000>,
<0 0x11e20000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11ea0000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "gpio", "iocfg_rm",
"iocfg_br", "iocfg_lm",
"iocfg_lb", "iocfg_rt",
"iocfg_lt", "iocfg_tl",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 210>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
mmc0_pins_default: mmc0-0 {
cmd-dat-pins {
pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO167__FUNC_MSDC0_CMD>;
input-enable;
mediatek,pull-up-adv = <1>;
};
clk-pins {
pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
mediatek,pull-down-adv = <2>;
};
rst-pins {
pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
mediatek,pull-up-adv = <0>;
};
};
};
mmc0 {
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-names = "default";
};
};
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
+2 -1
View File
@@ -44,7 +44,8 @@ information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength.
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,
drive-strength.
Non-empty subnodes must specify the 'pins' property.
Note that not all properties are valid for all pins.
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
+2
View File
@@ -23,6 +23,8 @@ PMIC's from Qualcomm.
"qcom,pmi8994-gpio"
"qcom,pmi8998-gpio"
"qcom,pms405-gpio"
"qcom,pm660-gpio"
"qcom,pm660l-gpio"
"qcom,pm8150-gpio"
"qcom,pm8150b-gpio"
"qcom,pm6150-gpio"
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+1
View File
@@ -21,6 +21,7 @@ Required Properties:
- "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller.
- "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller.
- "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller.
- "renesas,pfc-r8a774e1": for R8A774E1 (RZ/G2H) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
-87
View File
@@ -1,87 +0,0 @@
Renesas RZ/A2 combined Pin and GPIO controller
The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO
function (port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
Pin controller node
-------------------
Required properties:
- compatible: shall be:
- "renesas,r7s9210-pinctrl": for RZ/A2M
- reg
Address base and length of the memory area where the pin controller
hardware is mapped to.
- gpio-controller
This pin controller also controls pins as GPIO
- #gpio-cells
Must be 2
- gpio-ranges
Expresses the total number of GPIO ports/pins in this SoC
Example: Pin controller node for RZ/A2M SoC (r7s9210)
pinctrl: pin-controller@fcffe000 {
compatible = "renesas,r7s9210-pinctrl";
reg = <0xfcffe000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 176>;
};
Sub-nodes
---------
The child nodes of the pin controller designate pins to be used for
specific peripheral functions or as GPIO.
- Pin multiplexing sub-nodes:
A pin multiplexing sub-node describes how to configure a set of
(or a single) pin in some desired alternate function mode.
The values for the pinmux properties are a combination of port name, pin
number and the desired function index. Use the RZA2_PINMUX macro located
in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these.
For assigning GPIO pins, use the macro RZA2_PIN also in r7s9210-pinctrl.h
to express the desired port pin.
Required properties:
- pinmux:
integer array representing pin number and pin multiplexing configuration.
When a pin has to be configured in alternate function mode, use this
property to identify the pin by its global index, and provide its
alternate function configuration number along with it.
When multiple pins are required to be configured as part of the same
alternate function they shall be specified as members of the same
argument list of a single "pinmux" property.
Helper macros to ease assembling the pin index from its position
(port where it sits on and pin number) and alternate function identifier
are provided by the pin controller header file at:
<dt-bindings/pinctrl/r7s9210-pinctrl.h>
Integers values in "pinmux" argument list are assembled as:
((PORT * 8 + PIN) | MUX_FUNC << 16)
Example: Board specific pins configuration
&pinctrl {
/* Serial Console */
scif4_pins: serial4 {
pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
<RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
};
};
Example: Assigning a GPIO:
leds {
status = "okay";
compatible = "gpio-leds";
led0 {
/* P6_0 */
gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
};
};
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml
+100
View File
@@ -0,0 +1,100 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/A2 combined Pin and GPIO controller
maintainers:
- Chris Brandt <chris.brandt@renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO function
(port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
properties:
compatible:
const: "renesas,r7s9210-pinctrl" # RZ/A2M
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
description:
The first cell contains the global GPIO port index, constructed using the
RZA2_PIN() helper macro in r7s9210-pinctrl.h.
E.g. "RZA2_PIN(PORT6, 0)" for P6_0.
gpio-ranges:
maxItems: 1
patternProperties:
"^.*$":
if:
type: object
then:
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
The child nodes of the pin controller designate pins to be used for
specific peripheral functions or as GPIO.
A pin multiplexing sub-node describes how to configure a set of
(or a single) pin in some desired alternate function mode.
The values for the pinmux properties are a combination of port name,
pin number and the desired function index. Use the RZA2_PINMUX macro
located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily
define these.
For assigning GPIO pins, use the macro RZA2_PIN also in
to express the desired port pin.
properties:
phandle: true
pinmux:
description:
Values are constructed from GPIO port number, pin number, and
alternate function configuration number using the RZA2_PINMUX()
helper macro in r7s9210-pinctrl.h.
required:
- pinmux
additionalProperties: false
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
pinctrl: pin-controller@fcffe000 {
compatible = "renesas,r7s9210-pinctrl";
reg = <0xfcffe000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 176>;
/* Serial Console */
scif4_pins: serial4 {
pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
<RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
};
};
Documentation/kbuild/Kconfig.recursion-issue-02
+1 -1
View File
@@ -42,7 +42,7 @@
# "select FW_LOADER" [0], in the end the simple alternative solution to this
# problem consisted on matching semantics with newly introduced features.
#
# [0] http://lkml.kernel.org/r/1432241149-8762-1-git-send-email-mcgrof@do-not-panic.com
# [0] https://lkml.kernel.org/r/1432241149-8762-1-git-send-email-mcgrof@do-not-panic.com
mainmenu "Simple example to demo cumulative kconfig recursive dependency implication"
Documentation/kbuild/kconfig-language.rst
+9 -9
View File
@@ -540,8 +540,8 @@ followed by a test macro::
If you need to expose a compiler capability to makefiles and/or C source files,
`CC_HAS_` is the recommended prefix for the config option::
config CC_HAS_STACKPROTECTOR_NONE
def_bool $(cc-option,-fno-stack-protector)
config CC_HAS_ASM_GOTO
def_bool $(success,$(srctree)/scripts/gcc-goto.sh $(CC))
Build as module only
~~~~~~~~~~~~~~~~~~~~
@@ -688,10 +688,10 @@ and real world requirements were not well understood. As it stands though
only reverse engineering techniques have been used to deduce semantics from
variability modeling languages such as Kconfig [3]_.
.. [0] http://www.eng.uwaterloo.ca/~shshe/kconfig_semantics.pdf
.. [1] http://gsd.uwaterloo.ca/sites/default/files/vm-2013-berger.pdf
.. [2] http://gsd.uwaterloo.ca/sites/default/files/ase241-berger_0.pdf
.. [3] http://gsd.uwaterloo.ca/sites/default/files/icse2011.pdf
.. [0] https://www.eng.uwaterloo.ca/~shshe/kconfig_semantics.pdf
.. [1] https://gsd.uwaterloo.ca/sites/default/files/vm-2013-berger.pdf
.. [2] https://gsd.uwaterloo.ca/sites/default/files/ase241-berger_0.pdf
.. [3] https://gsd.uwaterloo.ca/sites/default/files/icse2011.pdf
Full SAT solver for Kconfig
~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -710,10 +710,10 @@ such efforts somehow on Kconfig. There is enough interest from mentors of
existing projects to not only help advise how to integrate this work upstream
but also help maintain it long term. Interested developers should visit:
http://kernelnewbies.org/KernelProjects/kconfig-sat
https://kernelnewbies.org/KernelProjects/kconfig-sat
.. [4] http://www.cs.cornell.edu/~sabhar/chapters/SATSolvers-KR-Handbook.pdf
.. [5] http://gsd.uwaterloo.ca/sites/default/files/vm-2013-berger.pdf
.. [4] https://www.cs.cornell.edu/~sabhar/chapters/SATSolvers-KR-Handbook.pdf
.. [5] https://gsd.uwaterloo.ca/sites/default/files/vm-2013-berger.pdf
.. [6] https://cados.cs.fau.de
.. [7] https://vamos.cs.fau.de
.. [8] https://undertaker.cs.fau.de
Documentation/kbuild/llvm.rst
+1 -1
View File
@@ -76,7 +76,7 @@ Getting Help
Getting LLVM
-------------
- http://releases.llvm.org/download.html
- https://releases.llvm.org/download.html
- https://github.com/llvm/llvm-project
- https://llvm.org/docs/GettingStarted.html
- https://llvm.org/docs/CMake.html
Documentation/kbuild/makefiles.rst
+44 -1
View File
@@ -368,6 +368,14 @@ more details, with real examples.
subdir-ccflags-y := -Werror
ccflags-remove-y, asflags-remove-y
These flags are used to remove particular flags for the compiler,
assembler invocations.
Example::
ccflags-remove-$(CONFIG_MCOUNT) += -pg
CFLAGS_$@, AFLAGS_$@
CFLAGS_$@ and AFLAGS_$@ only apply to commands in current
kbuild makefile.
@@ -375,6 +383,9 @@ more details, with real examples.
$(CFLAGS_$@) specifies per-file options for $(CC). The $@
part has a literal value which specifies the file that it is for.
CFLAGS_$@ has the higher priority than ccflags-remove-y; CFLAGS_$@
can re-add compiler flags that were removed by ccflags-remove-y.
Example::
# drivers/scsi/Makefile
@@ -387,6 +398,9 @@ more details, with real examples.
$(AFLAGS_$@) is a similar feature for source files in assembly
languages.
AFLAGS_$@ has the higher priority than asflags-remove-y; AFLAGS_$@
can re-add assembler flags that were removed by asflags-remove-y.
Example::
# arch/arm/kernel/Makefile
@@ -735,6 +749,10 @@ Both possibilities are described in the following.
hostprogs := lxdialog
always-y := $(hostprogs)
Kbuild provides the following shorthand for this:
hostprogs-always-y := lxdialog
This will tell kbuild to build lxdialog even if not referenced in
any rule.
@@ -817,7 +835,32 @@ The syntax is quite similar. The difference is to use "userprogs" instead of
5.4 When userspace programs are actually built
----------------------------------------------
Same as "When host programs are actually built".
Kbuild builds userspace programs only when told to do so.
There are two ways to do this.
(1) Add it as the prerequisite of another file
Example::
#net/bpfilter/Makefile
userprogs := bpfilter_umh
$(obj)/bpfilter_umh_blob.o: $(obj)/bpfilter_umh
$(obj)/bpfilter_umh is built before $(obj)/bpfilter_umh_blob.o
(2) Use always-y
Example::
userprogs := binderfs_example
always-y := $(userprogs)
Kbuild provides the following shorthand for this:
userprogs-always-y := binderfs_example
This will tell Kbuild to build binderfs_example when it visits this
Makefile.
6 Kbuild clean infrastructure
=============================
Makefile
+15 -11
View File
@@ -508,7 +508,6 @@ KBUILD_CFLAGS_MODULE := -DMODULE
KBUILD_LDFLAGS_MODULE :=
export KBUILD_LDS_MODULE := $(srctree)/scripts/module-common.lds
KBUILD_LDFLAGS :=
GCC_PLUGINS_CFLAGS :=
CLANG_FLAGS :=
export ARCH SRCARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE LD CC
@@ -751,9 +750,6 @@ endif
KBUILD_CFLAGS += $(call cc-option,--param=allow-store-data-races=0)
KBUILD_CFLAGS += $(call cc-option,-fno-allow-store-data-races)
include scripts/Makefile.kcov
include scripts/Makefile.gcc-plugins
ifdef CONFIG_READABLE_ASM
# Disable optimizations that make assembler listings hard to read.
# reorder blocks reorders the control in the function
@@ -768,7 +764,7 @@ ifneq ($(CONFIG_FRAME_WARN),0)
KBUILD_CFLAGS += -Wframe-larger-than=$(CONFIG_FRAME_WARN)
endif
stackp-flags-$(CONFIG_CC_HAS_STACKPROTECTOR_NONE) := -fno-stack-protector
stackp-flags-y := -fno-stack-protector
stackp-flags-$(CONFIG_STACKPROTECTOR) := -fstack-protector
stackp-flags-$(CONFIG_STACKPROTECTOR_STRONG) := -fstack-protector-strong
@@ -963,10 +959,19 @@ ifdef CONFIG_RETPOLINE
KBUILD_CFLAGS += $(call cc-option,-fcf-protection=none)
endif
include scripts/Makefile.kasan
include scripts/Makefile.extrawarn
include scripts/Makefile.ubsan
include scripts/Makefile.kcsan
# include additional Makefiles when needed
include-y := scripts/Makefile.extrawarn
include-$(CONFIG_KASAN) += scripts/Makefile.kasan
include-$(CONFIG_KCSAN) += scripts/Makefile.kcsan
include-$(CONFIG_UBSAN) += scripts/Makefile.ubsan
include-$(CONFIG_KCOV) += scripts/Makefile.kcov
include-$(CONFIG_GCC_PLUGINS) += scripts/Makefile.gcc-plugins
include $(addprefix $(srctree)/, $(include-y))
# scripts/Makefile.gcc-plugins is intentionally included last.
# Do not add $(call cc-option,...) below this line. When you build the kernel
# from the clean source tree, the GCC plugins do not exist at this point.
# Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments
KBUILD_CPPFLAGS += $(KCPPFLAGS)
@@ -1159,7 +1164,6 @@ KBUILD_VMLINUX_OBJS += $(patsubst %/,%/built-in.a, $(drivers-y))
export KBUILD_VMLINUX_OBJS KBUILD_VMLINUX_LIBS
export KBUILD_LDS := arch/$(SRCARCH)/kernel/vmlinux.lds
export LDFLAGS_vmlinux
# used by scripts/Makefile.package
export KBUILD_ALLDIRS := $(sort $(filter-out arch/%,$(vmlinux-alldirs)) LICENSES arch include scripts tools)
@@ -1191,7 +1195,7 @@ ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(SRCARCH)/Makefile.postlink)
# Final link of vmlinux with optional arch pass after final link
cmd_link-vmlinux = \
$(CONFIG_SHELL) $< $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_vmlinux) ; \
$(CONFIG_SHELL) $< "$(LD)" "$(KBUILD_LDFLAGS)" "$(LDFLAGS_vmlinux)"; \
$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
vmlinux: scripts/link-vmlinux.sh autoksyms_recursive $(vmlinux-deps) FORCE
arch/Kconfig
-3
View File
@@ -481,9 +481,6 @@ config HAVE_STACKPROTECTOR
An arch should select this symbol if:
- it has implemented a stack canary (e.g. __stack_chk_guard)
config CC_HAS_STACKPROTECTOR_NONE
def_bool $(cc-option,-fno-stack-protector)
config STACKPROTECTOR
bool "Stack Protector buffer overflow detection"
depends on HAVE_STACKPROTECTOR
arch/arc/kernel/process.c
-5
View File
@@ -296,11 +296,6 @@ void flush_thread(void)
{
}
int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
{
return 0;
}
int elf_check_arch(const struct elf32_hdr *x)
{
unsigned int eflags;
arch/arm/boot/compressed/Makefile
+2 -7
View File
@@ -84,9 +84,8 @@ endif
# -fstack-protector-strong triggers protection checks in this code,
# but it is being used too early to link to meaningful stack_chk logic.
nossp-flags-$(CONFIG_CC_HAS_STACKPROTECTOR_NONE) := -fno-stack-protector
$(foreach o, $(libfdt_objs) atags_to_fdt.o, \
$(eval CFLAGS_$(o) := -I $(srctree)/scripts/dtc/libfdt $(nossp-flags-y)))
$(eval CFLAGS_$(o) := -I $(srctree)/scripts/dtc/libfdt -fno-stack-protector))
# These were previously generated C files. When you are building the kernel
# with O=, make sure to remove the stale files in the output tree. Otherwise,
@@ -103,13 +102,9 @@ clean-files += piggy_data lib1funcs.S ashldi3.S bswapsdi2.S hyp-stub.S
KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING
ifeq ($(CONFIG_FUNCTION_TRACER),y)
ORIG_CFLAGS := $(KBUILD_CFLAGS)
KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
endif
ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin \
-I$(obj) $(DISABLE_ARM_SSP_PER_TASK_PLUGIN)
ccflags-remove-$(CONFIG_FUNCTION_TRACER) += -pg
asflags-y := -DZIMAGE
# Supply kernel BSS size to the decompressor via a linker symbol.
arch/arm/boot/dts/am33xx-l4.dtsi
+1 -1
View File
@@ -290,7 +290,7 @@
am33xx_pinmux: pinmux@800 {
compatible = "pinctrl-single";
reg = <0x800 0x238>;
#pinctrl-cells = <1>;
#pinctrl-cells = <2>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
arch/arm/kernel/process.c
-15
View File
@@ -281,21 +281,6 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs)
return 1;
}
/*
* fill in the fpe structure for a core dump...
*/
int dump_fpu (struct pt_regs *regs, struct user_fp *fp)
{
struct thread_info *thread = current_thread_info();
int used_math = thread->used_cp[1] | thread->used_cp[2];
if (used_math)
memcpy(fp, &thread->fpstate.soft, sizeof (*fp));
return used_math != 0;
}
EXPORT_SYMBOL(dump_fpu);
unsigned long get_wchan(struct task_struct *p)
{
struct stackframe frame;
arch/hexagon/kernel/process.c
-9
View File
@@ -153,15 +153,6 @@ unsigned long get_wchan(struct task_struct *p)
return 0;
}
/*
* Required placeholder.
*/
int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
{
return 0;
}
/*
* Called on the exit path of event entry; see vm_entry.S
*
arch/ia64/kernel/process.c
-34
View File
@@ -530,52 +530,18 @@ do_copy_task_regs (struct task_struct *task, struct unw_frame_info *info, void *
unw_get_ar(info, UNW_AR_SSD, &dst[56]);
}
void
do_dump_task_fpu (struct task_struct *task, struct unw_frame_info *info, void *arg)
{
elf_fpreg_t *dst = arg;
int i;
memset(dst, 0, sizeof(elf_fpregset_t)); /* don't leak any "random" bits */
if (unw_unwind_to_user(info) < 0)
return;
/* f0 is 0.0, f1 is 1.0 */
for (i = 2; i < 32; ++i)
unw_get_fr(info, i, dst + i);
ia64_flush_fph(task);
if ((task->thread.flags & IA64_THREAD_FPH_VALID) != 0)
memcpy(dst + 32, task->thread.fph, 96*16);
}
void
do_copy_regs (struct unw_frame_info *info, void *arg)
{
do_copy_task_regs(current, info, arg);
}
void
do_dump_fpu (struct unw_frame_info *info, void *arg)
{
do_dump_task_fpu(current, info, arg);
}
void
ia64_elf_core_copy_regs (struct pt_regs *pt, elf_gregset_t dst)
{
unw_init_running(do_copy_regs, dst);
}
int
dump_fpu (struct pt_regs *pt, elf_fpregset_t dst)
{
unw_init_running(do_dump_fpu, dst);
return 1; /* f0-f31 are always valid so we always return 1 */
}
/*
* Flush thread state. This is called when a thread does an execve().
*/
arch/mips/vdso/Makefile
+1 -2
View File
@@ -35,8 +35,7 @@ cflags-vdso := $(ccflags-vdso) \
-O3 -g -fPIC -fno-strict-aliasing -fno-common -fno-builtin -G 0 \
-mrelax-pic-calls $(call cc-option, -mexplicit-relocs) \
-fno-stack-protector -fno-jump-tables -DDISABLE_BRANCH_PROFILING \
$(call cc-option, -fno-asynchronous-unwind-tables) \
$(call cc-option, -fno-stack-protector)
$(call cc-option, -fno-asynchronous-unwind-tables)
aflags-vdso := $(ccflags-vdso) \
-D__ASSEMBLY__ -Wa,-gdwarf-2
arch/nios2/kernel/process.c
-8
View File
@@ -252,14 +252,6 @@ void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp)
regs->sp = sp;
}
#include <linux/elfcore.h>
/* Fill in the FPU structure for a core dump. */
int dump_fpu(struct pt_regs *regs, elf_fpregset_t *r)
{
return 0; /* Nios2 has no FPU and thus no FPU registers */
}
asmlinkage int nios2_clone(unsigned long clone_flags, unsigned long newsp,
int __user *parent_tidptr, int __user *child_tidptr,
unsigned long tls)
arch/openrisc/kernel/process.c
-7
View File
@@ -214,13 +214,6 @@ void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp)
regs->sp = sp;
}
/* Fill in the fpu structure for a core dump. */
int dump_fpu(struct pt_regs *regs, elf_fpregset_t * fpu)
{
/* TODO */
return 0;
}
extern struct thread_info *_switch(struct thread_info *old_ti,
struct thread_info *new_ti);
extern int lwa_flag;
arch/parisc/include/asm/elf.h
-3
View File
@@ -305,9 +305,6 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
struct task_struct;
extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *);
#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
struct pt_regs; /* forward declaration... */
arch/parisc/kernel/process.c
-19
View File
@@ -151,25 +151,6 @@ void release_thread(struct task_struct *dead_task)
{
}
/*
* Fill in the FPU structure for a core dump.
*/
int dump_fpu (struct pt_regs * regs, elf_fpregset_t *r)
{
if (regs == NULL)
return 0;
memcpy(r, regs->fr, sizeof *r);
return 1;
}
int dump_task_fpu (struct task_struct *tsk, elf_fpregset_t *r)
{
memcpy(r, tsk->thread.regs.fr, sizeof(*r));
return 1;
}
/*
* Idle thread support
*
arch/powerpc/boot/Makefile
+2
View File
@@ -366,6 +366,8 @@ initrd-y := $(patsubst zImage%, zImage.initrd%, \
$(patsubst treeImage%, treeImage.initrd%, $(image-y)))))
initrd-y := $(filter-out $(image-y), $(initrd-y))
targets += $(image-y) $(initrd-y)
targets += $(foreach x, dtbImage uImage cuImage simpleImage treeImage, \
$(patsubst $(x).%, dts/%.dtb, $(filter $(x).%, $(image-y))))
$(addprefix $(obj)/, $(initrd-y)): $(obj)/ramdisk.image.gz
arch/powerpc/kernel/Makefile
+1 -1
View File
@@ -16,7 +16,7 @@ CFLAGS_prom_init.o += $(DISABLE_LATENT_ENTROPY_PLUGIN)
CFLAGS_btext.o += $(DISABLE_LATENT_ENTROPY_PLUGIN)
CFLAGS_prom.o += $(DISABLE_LATENT_ENTROPY_PLUGIN)
CFLAGS_prom_init.o += $(call cc-option, -fno-stack-protector)
CFLAGS_prom_init.o += -fno-stack-protector
CFLAGS_prom_init.o += -DDISABLE_BRANCH_PROFILING
CFLAGS_prom_init.o += -ffreestanding
arch/powerpc/platforms/powermac/Makefile
+1 -1
View File
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
CFLAGS_bootx_init.o += -fPIC
CFLAGS_bootx_init.o += $(call cc-option, -fno-stack-protector)
CFLAGS_bootx_init.o += -fno-stack-protector
KASAN_SANITIZE_bootx_init.o := n
arch/powerpc/xmon/Makefile
+1 -2
View File
@@ -7,8 +7,7 @@ UBSAN_SANITIZE := n
KASAN_SANITIZE := n
# Disable ftrace for the entire directory
ORIG_CFLAGS := $(KBUILD_CFLAGS)
KBUILD_CFLAGS = $(subst $(CC_FLAGS_FTRACE),,$(ORIG_CFLAGS))
ccflags-remove-$(CONFIG_FUNCTION_TRACER) += $(CC_FLAGS_FTRACE)
ifdef CONFIG_CC_IS_CLANG
# clang stores addresses on the stack causing the frame size to blow
arch/s390/Makefile
+1 -1
View File
@@ -27,7 +27,7 @@ KBUILD_CFLAGS_DECOMPRESSOR := $(CLANG_FLAGS) -m64 -O2
KBUILD_CFLAGS_DECOMPRESSOR += -DDISABLE_BRANCH_PROFILING -D__NO_FORTIFY
KBUILD_CFLAGS_DECOMPRESSOR += -fno-delete-null-pointer-checks -msoft-float
KBUILD_CFLAGS_DECOMPRESSOR += -fno-asynchronous-unwind-tables
KBUILD_CFLAGS_DECOMPRESSOR += $(call cc-option,-ffreestanding)
KBUILD_CFLAGS_DECOMPRESSOR += -ffreestanding
KBUILD_CFLAGS_DECOMPRESSOR += $(call cc-disable-warning, address-of-packed-member)
KBUILD_CFLAGS_DECOMPRESSOR += $(if $(CONFIG_DEBUG_INFO),-g)
KBUILD_CFLAGS_DECOMPRESSOR += $(if $(CONFIG_DEBUG_INFO_DWARF4), $(call cc-option, -gdwarf-4,))
arch/s390/kernel/process.c
-18
View File
@@ -160,24 +160,6 @@ asmlinkage void execve_tail(void)
asm volatile("sfpc %0" : : "d" (0));
}
/*
* fill in the FPU structure for a core dump.
*/
int dump_fpu (struct pt_regs * regs, s390_fp_regs *fpregs)
{
save_fpu_regs();
fpregs->fpc = current->thread.fpu.fpc;
fpregs->pad = 0;
if (MACHINE_HAS_VX)
convert_vx_to_fp((freg_t *)&fpregs->fprs,
current->thread.fpu.vxrs);
else
memcpy(&fpregs->fprs, current->thread.fpu.fprs,
sizeof(fpregs->fprs));
return 1;
}
EXPORT_SYMBOL(dump_fpu);
unsigned long get_wchan(struct task_struct *p)
{
struct unwind_state state;
arch/sh/boot/compressed/Makefile
+1 -4
View File
@@ -28,10 +28,7 @@ IMAGE_OFFSET := $(shell /bin/bash -c 'printf "0x%08x" \
$(CONFIG_BOOT_LINK_OFFSET)]')
endif
ifeq ($(CONFIG_MCOUNT),y)
ORIG_CFLAGS := $(KBUILD_CFLAGS)
KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
endif
ccflags-remove-$(CONFIG_MCOUNT) += -pg
LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext $(IMAGE_OFFSET) -e startup \
-T $(obj)/../../kernel/vmlinux.lds
arch/sh/include/asm/fpu.h
-5
View File
@@ -37,11 +37,6 @@ struct user_regset;
extern int do_fpu_inst(unsigned short, struct pt_regs *);
extern int init_fpu(struct task_struct *);
extern int fpregs_get(struct task_struct *target,
const struct user_regset *regset,
unsigned int pos, unsigned int count,
void *kbuf, void __user *ubuf);
static inline void __unlazy_fpu(struct task_struct *tsk, struct pt_regs *regs)
{
if (task_thread_info(tsk)->status & TS_USEDFPU) {
arch/sh/kernel/process_32.c
-18
View File
@@ -93,24 +93,6 @@ void release_thread(struct task_struct *dead_task)
/* do nothing */
}
/* Fill in the fpu structure for a core dump.. */
int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
{
int fpvalid = 0;
#if defined(CONFIG_SH_FPU)
struct task_struct *tsk = current;
fpvalid = !!tsk_used_math(tsk);
if (fpvalid)
fpvalid = !fpregs_get(tsk, NULL,
(struct membuf){fpu, sizeof(*fpu)});
#endif
return fpvalid;
}
EXPORT_SYMBOL(dump_fpu);
asmlinkage void ret_from_fork(void);
asmlinkage void ret_from_kernel_thread(void);
arch/sh/kernel/ptrace_32.c
+1 -1
View File
@@ -165,7 +165,7 @@ static int genregs_set(struct task_struct *target,
}
#ifdef CONFIG_SH_FPU
int fpregs_get(struct task_struct *target,
static int fpregs_get(struct task_struct *target,
const struct user_regset *regset,
struct membuf to)
{
arch/sparc/kernel/process_32.c
-49
View File
@@ -380,55 +380,6 @@ int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg,
return 0;
}
/*
* fill in the fpu structure for a core dump.
*/
int dump_fpu (struct pt_regs * regs, elf_fpregset_t * fpregs)
{
if (used_math()) {
memset(fpregs, 0, sizeof(*fpregs));
fpregs->pr_q_entrysize = 8;
return 1;
}
#ifdef CONFIG_SMP
if (test_thread_flag(TIF_USEDFPU)) {
put_psr(get_psr() | PSR_EF);
fpsave(&current->thread.float_regs[0], &current->thread.fsr,
&current->thread.fpqueue[0], &current->thread.fpqdepth);
if (regs != NULL) {
regs->psr &= ~(PSR_EF);
clear_thread_flag(TIF_USEDFPU);
}
}
#else
if (current == last_task_used_math) {
put_psr(get_psr() | PSR_EF);
fpsave(&current->thread.float_regs[0], &current->thread.fsr,
&current->thread.fpqueue[0], &current->thread.fpqdepth);
if (regs != NULL) {
regs->psr &= ~(PSR_EF);
last_task_used_math = NULL;
}
}
#endif
memcpy(&fpregs->pr_fr.pr_regs[0],
&current->thread.float_regs[0],
(sizeof(unsigned long) * 32));
fpregs->pr_fsr = current->thread.fsr;
fpregs->pr_qcnt = current->thread.fpqdepth;
fpregs->pr_q_entrysize = 8;
fpregs->pr_en = 1;
if(fpregs->pr_qcnt != 0) {
memcpy(&fpregs->pr_q[0],
&current->thread.fpqueue[0],
sizeof(struct fpq) * fpregs->pr_qcnt);
}
/* Zero out the rest. */
memset(&fpregs->pr_q[fpregs->pr_qcnt], 0,
sizeof(struct fpq) * (32 - fpregs->pr_qcnt));
return 1;
}
unsigned long get_wchan(struct task_struct *task)
{
unsigned long pc, fp, bias = 0;
arch/sparc/kernel/process_64.c
-66
View File
@@ -666,72 +666,6 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
return 0;
}
typedef struct {
union {
unsigned int pr_regs[32];
unsigned long pr_dregs[16];
} pr_fr;
unsigned int __unused;
unsigned int pr_fsr;
unsigned char pr_qcnt;
unsigned char pr_q_entrysize;
unsigned char pr_en;
unsigned int pr_q[64];
} elf_fpregset_t32;
/*
* fill in the fpu structure for a core dump.
*/
int dump_fpu (struct pt_regs * regs, elf_fpregset_t * fpregs)
{
unsigned long *kfpregs = current_thread_info()->fpregs;
unsigned long fprs = current_thread_info()->fpsaved[0];
if (test_thread_flag(TIF_32BIT)) {
elf_fpregset_t32 *fpregs32 = (elf_fpregset_t32 *)fpregs;
if (fprs & FPRS_DL)
memcpy(&fpregs32->pr_fr.pr_regs[0], kfpregs,
sizeof(unsigned int) * 32);
else
memset(&fpregs32->pr_fr.pr_regs[0], 0,
sizeof(unsigned int) * 32);
fpregs32->pr_qcnt = 0;
fpregs32->pr_q_entrysize = 8;
memset(&fpregs32->pr_q[0], 0,
(sizeof(unsigned int) * 64));
if (fprs & FPRS_FEF) {
fpregs32->pr_fsr = (unsigned int) current_thread_info()->xfsr[0];
fpregs32->pr_en = 1;
} else {
fpregs32->pr_fsr = 0;
fpregs32->pr_en = 0;
}
} else {
if(fprs & FPRS_DL)
memcpy(&fpregs->pr_regs[0], kfpregs,
sizeof(unsigned int) * 32);
else
memset(&fpregs->pr_regs[0], 0,
sizeof(unsigned int) * 32);
if(fprs & FPRS_DU)
memcpy(&fpregs->pr_regs[16], kfpregs+16,
sizeof(unsigned int) * 32);
else
memset(&fpregs->pr_regs[16], 0,
sizeof(unsigned int) * 32);
if(fprs & FPRS_FEF) {
fpregs->pr_fsr = current_thread_info()->xfsr[0];
fpregs->pr_gsr = current_thread_info()->gsr[0];
} else {
fpregs->pr_fsr = fpregs->pr_gsr = 0;
}
fpregs->pr_fprs = fprs;
}
return 1;
}
EXPORT_SYMBOL(dump_fpu);
unsigned long get_wchan(struct task_struct *task)
{
unsigned long pc, fp, bias = 0;
arch/sparc/vdso/Makefile
+2 -2
View File
@@ -54,7 +54,7 @@ $(obj)/vdso-image-%.c: $(obj)/vdso%.so.dbg $(obj)/vdso%.so $(obj)/vdso2c FORCE
# optimize sibling calls.
#
CFL := $(PROFILING) -mcmodel=medlow -fPIC -O2 -fasynchronous-unwind-tables -m64 \
$(filter -g%,$(KBUILD_CFLAGS)) $(call cc-option, -fno-stack-protector) \
$(filter -g%,$(KBUILD_CFLAGS)) -fno-stack-protector \
-fno-omit-frame-pointer -foptimize-sibling-calls \
-DDISABLE_BRANCH_PROFILING -DBUILD_VDSO
@@ -93,7 +93,7 @@ KBUILD_CFLAGS_32 := $(filter-out -fno-pic,$(KBUILD_CFLAGS_32))
KBUILD_CFLAGS_32 := $(filter-out $(GCC_PLUGINS_CFLAGS),$(KBUILD_CFLAGS_32))
KBUILD_CFLAGS_32 := $(filter-out $(SPARC_REG_CFLAGS),$(KBUILD_CFLAGS_32))
KBUILD_CFLAGS_32 += -m32 -msoft-float -fpic
KBUILD_CFLAGS_32 += $(call cc-option, -fno-stack-protector)
KBUILD_CFLAGS_32 += -fno-stack-protector
KBUILD_CFLAGS_32 += $(call cc-option, -foptimize-sibling-calls)
KBUILD_CFLAGS_32 += -fno-omit-frame-pointer
KBUILD_CFLAGS_32 += -DDISABLE_BRANCH_PROFILING
arch/um/Makefile
+1 -2
View File
@@ -121,8 +121,7 @@ LINK-$(CONFIG_LD_SCRIPT_STATIC) += -static
LINK-$(CONFIG_LD_SCRIPT_DYN) += -Wl,-rpath,/lib $(call cc-option, -no-pie)
CFLAGS_NO_HARDENING := $(call cc-option, -fno-PIC,) $(call cc-option, -fno-pic,) \
$(call cc-option, -fno-stack-protector,) \
$(call cc-option, -fno-stack-protector-all,)
-fno-stack-protector $(call cc-option, -fno-stack-protector-all)
# Options used by linker script
export LDS_START := $(START)
arch/x86/Makefile
+2 -2
View File
@@ -36,8 +36,8 @@ REALMODE_CFLAGS := $(M16_CFLAGS) -g -Os -DDISABLE_BRANCH_PROFILING \
-fno-strict-aliasing -fomit-frame-pointer -fno-pic \
-mno-mmx -mno-sse
REALMODE_CFLAGS += $(call __cc-option, $(CC), $(REALMODE_CFLAGS), -ffreestanding)
REALMODE_CFLAGS += $(call __cc-option, $(CC), $(REALMODE_CFLAGS), -fno-stack-protector)
REALMODE_CFLAGS += -ffreestanding
REALMODE_CFLAGS += -fno-stack-protector
REALMODE_CFLAGS += $(call __cc-option, $(CC), $(REALMODE_CFLAGS), -Wno-address-of-packed-member)
REALMODE_CFLAGS += $(call __cc-option, $(CC), $(REALMODE_CFLAGS), $(cc_stack_align4))
export REALMODE_CFLAGS
arch/x86/boot/compressed/Makefile
+2 -2
View File
@@ -35,8 +35,8 @@ cflags-$(CONFIG_X86_32) := -march=i386
cflags-$(CONFIG_X86_64) := -mcmodel=small
KBUILD_CFLAGS += $(cflags-y)
KBUILD_CFLAGS += -mno-mmx -mno-sse
KBUILD_CFLAGS += $(call cc-option,-ffreestanding)
KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
KBUILD_CFLAGS += -ffreestanding
KBUILD_CFLAGS += -fno-stack-protector
KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member)
KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
KBUILD_CFLAGS += -Wno-pointer-sign
arch/x86/entry/vdso/Makefile
+2 -2
View File
@@ -82,7 +82,7 @@ $(obj)/vdso-image-%.c: $(obj)/vdso%.so.dbg $(obj)/vdso%.so $(obj)/vdso2c FORCE
# optimize sibling calls.
#
CFL := $(PROFILING) -mcmodel=small -fPIC -O2 -fasynchronous-unwind-tables -m64 \
$(filter -g%,$(KBUILD_CFLAGS)) $(call cc-option, -fno-stack-protector) \
$(filter -g%,$(KBUILD_CFLAGS)) -fno-stack-protector \
-fno-omit-frame-pointer -foptimize-sibling-calls \
-DDISABLE_BRANCH_PROFILING -DBUILD_VDSO
@@ -151,7 +151,7 @@ KBUILD_CFLAGS_32 := $(filter-out -mfentry,$(KBUILD_CFLAGS_32))
KBUILD_CFLAGS_32 := $(filter-out $(GCC_PLUGINS_CFLAGS),$(KBUILD_CFLAGS_32))
KBUILD_CFLAGS_32 := $(filter-out $(RETPOLINE_CFLAGS),$(KBUILD_CFLAGS_32))
KBUILD_CFLAGS_32 += -m32 -msoft-float -mregparm=0 -fpic
KBUILD_CFLAGS_32 += $(call cc-option, -fno-stack-protector)
KBUILD_CFLAGS_32 += -fno-stack-protector
KBUILD_CFLAGS_32 += $(call cc-option, -foptimize-sibling-calls)
KBUILD_CFLAGS_32 += -fno-omit-frame-pointer
KBUILD_CFLAGS_32 += -DDISABLE_BRANCH_PROFILING
arch/x86/kernel/cpu/Makefile
+1 -2
View File
@@ -17,8 +17,7 @@ KCOV_INSTRUMENT_perf_event.o := n
KCSAN_SANITIZE_common.o := n
# Make sure load_percpu_segment has no stackprotector
nostackp := $(call cc-option, -fno-stack-protector)
CFLAGS_common.o := $(nostackp)
CFLAGS_common.o := -fno-stack-protector
obj-y := cacheinfo.o scattered.o topology.o
obj-y += common.o
arch/x86/lib/Makefile
+1 -1
View File
@@ -24,7 +24,7 @@ ifdef CONFIG_FUNCTION_TRACER
CFLAGS_REMOVE_cmdline.o = -pg
endif
CFLAGS_cmdline.o := $(call cc-option, -fno-stack-protector)
CFLAGS_cmdline.o := -fno-stack-protector
endif
inat_tables_script = $(srctree)/arch/x86/tools/gen-insn-attr-x86.awk
arch/x86/mm/Makefile
+3 -4
View File
@@ -22,10 +22,9 @@ obj-y := init.o init_$(BITS).o fault.o ioremap.o extable.o mmap.o \
obj-y += pat/
# Make sure __phys_addr has no stackprotector
nostackp := $(call cc-option, -fno-stack-protector)
CFLAGS_physaddr.o := $(nostackp)
CFLAGS_setup_nx.o := $(nostackp)
CFLAGS_mem_encrypt_identity.o := $(nostackp)
CFLAGS_physaddr.o := -fno-stack-protector
CFLAGS_setup_nx.o := -fno-stack-protector
CFLAGS_mem_encrypt_identity.o := -fno-stack-protector
CFLAGS_fault.o := -I $(srctree)/$(src)/../include/asm/trace
arch/x86/power/Makefile
+1 -2
View File
@@ -3,8 +3,7 @@ OBJECT_FILES_NON_STANDARD_hibernate_asm_$(BITS).o := y
# __restore_processor_state() restores %gs after S3 resume and so should not
# itself be stack-protected
nostackp := $(call cc-option, -fno-stack-protector)
CFLAGS_cpu.o := $(nostackp)
CFLAGS_cpu.o := -fno-stack-protector
obj-$(CONFIG_PM_SLEEP) += cpu.o
obj-$(CONFIG_HIBERNATION) += hibernate_$(BITS).o hibernate_asm_$(BITS).o hibernate.o
arch/x86/purgatory/Makefile
+1 -1
View File
@@ -34,7 +34,7 @@ KCOV_INSTRUMENT := n
PURGATORY_CFLAGS_REMOVE := -mcmodel=kernel
PURGATORY_CFLAGS := -mcmodel=large -ffreestanding -fno-zero-initialized-in-bss
PURGATORY_CFLAGS += $(DISABLE_STACKLEAK_PLUGIN) -DDISABLE_BRANCH_PROFILING
PURGATORY_CFLAGS += $(call cc-option,-fno-stack-protector)
PURGATORY_CFLAGS += -fno-stack-protector
# Default KBUILD_CFLAGS can have -pg option set when FTRACE is enabled. That
# in turn leaves some undefined symbols like __fentry__ in purgatory and not
arch/x86/um/vdso/Makefile
+1 -1
View File
@@ -42,7 +42,7 @@ $(obj)/%.so: $(obj)/%.so.dbg FORCE
# optimize sibling calls.
#
CFL := $(PROFILING) -mcmodel=small -fPIC -O2 -fasynchronous-unwind-tables -m64 \
$(filter -g%,$(KBUILD_CFLAGS)) $(call cc-option, -fno-stack-protector) \
$(filter -g%,$(KBUILD_CFLAGS)) -fno-stack-protector \
-fno-omit-frame-pointer -foptimize-sibling-calls
$(vobjs): KBUILD_CFLAGS += $(CFL)
arch/x86/xen/Makefile
+2 -3
View File
@@ -9,9 +9,8 @@ CFLAGS_REMOVE_irq.o = -pg
endif
# Make sure early boot has no stackprotector
nostackp := $(call cc-option, -fno-stack-protector)
CFLAGS_enlighten_pv.o := $(nostackp)
CFLAGS_mmu_pv.o := $(nostackp)
CFLAGS_enlighten_pv.o := -fno-stack-protector
CFLAGS_mmu_pv.o := -fno-stack-protector
obj-y += enlighten.o
obj-y += mmu.o
arch/xtensa/boot/boot-elf/Makefile
+1 -1
View File
@@ -26,7 +26,7 @@ $(obj)/Image.o: $(obj)/../vmlinux.bin $(OBJS)
$(OBJS) $@
$(obj)/../Image.elf: $(obj)/Image.o $(obj)/boot.lds
$(Q)$(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_vmlinux) \
$(Q)$(LD) $(KBUILD_LDFLAGS) \
-T $(obj)/boot.lds \
--build-id=none \
-o $@ $(obj)/Image.o
drivers/firmware/efi/libstub/Makefile
+2 -2
View File
@@ -28,8 +28,8 @@ cflags-$(CONFIG_EFI_GENERIC_STUB) += -I$(srctree)/scripts/dtc/libfdt
KBUILD_CFLAGS := $(cflags-y) -Os -DDISABLE_BRANCH_PROFILING \
-include $(srctree)/drivers/firmware/efi/libstub/hidden.h \
-D__NO_FORTIFY \
$(call cc-option,-ffreestanding) \
$(call cc-option,-fno-stack-protector) \
-ffreestanding \
-fno-stack-protector \
$(call cc-option,-fno-addrsig) \
-D__DISABLE_EXPORTS
drivers/memory/Kconfig
+10
View File
@@ -188,6 +188,16 @@ config RENESAS_RPCIF
host or HyperFlash. You'll have to select individual components
under the corresponding menu.
config STM32_FMC2_EBI
tristate "Support for FMC2 External Bus Interface on STM32MP SoCs"
depends on MACH_STM32MP157 || COMPILE_TEST
select MFD_SYSCON
help
Select this option to enable the STM32 FMC2 External Bus Interface
controller. This driver configures the transactions with external
devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
SOCs containing the FMC2 External Bus Interface.
source "drivers/memory/samsung/Kconfig"
source "drivers/memory/tegra/Kconfig"
drivers/memory/Makefile
+1
View File
@@ -23,6 +23,7 @@ obj-$(CONFIG_MTK_SMI) += mtk-smi.o
obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o
obj-$(CONFIG_PL353_SMC) += pl353-smc.o
obj-$(CONFIG_RENESAS_RPCIF) += renesas-rpc-if.o
obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o
obj-$(CONFIG_SAMSUNG_MC) += samsung/
obj-$(CONFIG_TEGRA_MC) += tegra/
drivers/memory/stm32-fmc2-ebi.c
+1206
View File
File diff suppressed because it is too large Load Diff
drivers/mtd/chips/Kconfig
+1 -1
View File
@@ -11,7 +11,7 @@ config MTD_CFI
AMD and other flash manufactures that provides a universal method
for probing the capabilities of flash devices. If you wish to
support any device that is CFI-compliant, you need to enable this
option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
option. Visit <https://www.amd.com/products/nvd/overview/cfi.html>
for more information on CFI.
config MTD_JEDECPROBE
drivers/mtd/hyperbus/hbmc-am654.c
+1 -1
View File
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
// Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
// Author: Vignesh Raghavendra <vigneshr@ti.com>
#include <linux/err.h>
drivers/mtd/hyperbus/hyperbus-core.c
+1 -1
View File
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
// Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
// Author: Vignesh Raghavendra <vigneshr@ti.com>
#include <linux/err.h>
drivers/mtd/maps/Kconfig
+1 -1
View File
@@ -310,7 +310,7 @@ config MTD_DC21285
help
This provides a driver for the flash accessed using Intel's
21285 bridge used with Intel's StrongARM processors. More info at
<http://www.intel.com/design/bridge/docs/21285_documentation.htm>.
<https://www.intel.com/design/bridge/docs/21285_documentation.htm>.
config MTD_IXP4XX
tristate "CFI Flash device mapped on Intel IXP4xx based systems"
drivers/mtd/maps/sc520cdp.c
+1 -1
View File
@@ -6,7 +6,7 @@
* The SC520CDP is an evaluation board for the Elan SC520 processor available
* from AMD. It has two banks of 32-bit Flash ROM, each 8 Megabytes in size,
* and up to 512 KiB of 8-bit DIL Flash ROM.
* For details see http://www.amd.com/products/epd/desiging/evalboards/18.elansc520/520_cdp_brief/index.html
* For details see https://www.amd.com/products/epd/desiging/evalboards/18.elansc520/520_cdp_brief/index.html
*/
#include <linux/module.h>
drivers/mtd/nand/Kconfig
+5
View File
@@ -1,7 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-only
menu "NAND"
config MTD_NAND_CORE
tristate
source "drivers/mtd/nand/onenand/Kconfig"
source "drivers/mtd/nand/raw/Kconfig"
source "drivers/mtd/nand/spi/Kconfig"
endmenu
drivers/mtd/nand/onenand/Kconfig
-1
View File
@@ -1,7 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig MTD_ONENAND
tristate "OneNAND Device Support"
depends on MTD
depends on HAS_IOMEM
help
This enables support for accessing all type of OneNAND flash
drivers/mtd/nand/raw/Kconfig
+1 -1
View File
@@ -12,7 +12,6 @@ config MTD_NAND_ECC_SW_HAMMING_SMC
menuconfig MTD_RAW_NAND
tristate "Raw/Parallel NAND Device Support"
depends on MTD
select MTD_NAND_CORE
select MTD_NAND_ECC_SW_HAMMING
help
@@ -415,6 +414,7 @@ config MTD_NAND_TEGRA
config MTD_NAND_STM32_FMC2
tristate "Support for NAND controller on STM32MP SoCs"
depends on MACH_STM32MP157 || COMPILE_TEST
select MFD_SYSCON
help
Enables support for NAND Flash chips on SoCs containing the FMC2
NAND controller. This controller is found on STM32MP SoCs.
drivers/mtd/nand/raw/ams-delta.c
+3 -3
View File
@@ -191,8 +191,8 @@ static int gpio_nand_exec_op(struct nand_chip *this,
return ret;
}
static int gpio_nand_setup_data_interface(struct nand_chip *this, int csline,
const struct nand_data_interface *cf)
static int gpio_nand_setup_interface(struct nand_chip *this, int csline,
const struct nand_interface_config *cf)
{
struct gpio_nand *priv = nand_get_controller_data(this);
const struct nand_sdr_timings *sdr = nand_get_sdr_timings(cf);
@@ -217,7 +217,7 @@ static int gpio_nand_setup_data_interface(struct nand_chip *this, int csline,
static const struct nand_controller_ops gpio_nand_ops = {
.exec_op = gpio_nand_exec_op,
.setup_data_interface = gpio_nand_setup_data_interface,
.setup_interface = gpio_nand_setup_interface,
};
/*
drivers/mtd/nand/raw/arasan-nand-controller.c
+3 -3
View File
@@ -854,8 +854,8 @@ static int anfc_exec_op(struct nand_chip *chip,
return nand_op_parser_exec_op(chip, &anfc_op_parser, op, check_only);
}
static int anfc_setup_data_interface(struct nand_chip *chip, int target,
const struct nand_data_interface *conf)
static int anfc_setup_interface(struct nand_chip *chip, int target,
const struct nand_interface_config *conf)
{
struct anand *anand = to_anand(chip);
struct arasan_nfc *nfc = to_anfc(chip->controller);
@@ -1083,7 +1083,7 @@ static void anfc_detach_chip(struct nand_chip *chip)
static const struct nand_controller_ops anfc_ops = {
.exec_op = anfc_exec_op,
.setup_data_interface = anfc_setup_data_interface,
.setup_interface = anfc_setup_interface,
.attach_chip = anfc_attach_chip,
.detach_chip = anfc_detach_chip,
};
drivers/mtd/nand/raw/atmel/nand-controller.c
+17 -17
View File
@@ -200,8 +200,8 @@ struct atmel_nand_controller_ops {
void (*nand_init)(struct atmel_nand_controller *nc,
struct atmel_nand *nand);
int (*ecc_init)(struct nand_chip *chip);
int (*setup_data_interface)(struct atmel_nand *nand, int csline,
const struct nand_data_interface *conf);
int (*setup_interface)(struct atmel_nand *nand, int csline,
const struct nand_interface_config *conf);
};
struct atmel_nand_controller_caps {
@@ -1168,7 +1168,7 @@ static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
}
static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
const struct nand_data_interface *conf,
const struct nand_interface_config *conf,
struct atmel_smc_cs_conf *smcconf)
{
u32 ncycles, totalcycles, timeps, mckperiodps;
@@ -1397,9 +1397,9 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
return 0;
}
static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
static int atmel_smc_nand_setup_interface(struct atmel_nand *nand,
int csline,
const struct nand_data_interface *conf)
const struct nand_interface_config *conf)
{
struct atmel_nand_controller *nc;
struct atmel_smc_cs_conf smcconf;
@@ -1422,9 +1422,9 @@ static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
return 0;
}
static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
static int atmel_hsmc_nand_setup_interface(struct atmel_nand *nand,
int csline,
const struct nand_data_interface *conf)
const struct nand_interface_config *conf)
{
struct atmel_hsmc_nand_controller *nc;
struct atmel_smc_cs_conf smcconf;
@@ -1452,8 +1452,8 @@ static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
return 0;
}
static int atmel_nand_setup_data_interface(struct nand_chip *chip, int csline,
const struct nand_data_interface *conf)
static int atmel_nand_setup_interface(struct nand_chip *chip, int csline,
const struct nand_interface_config *conf)
{
struct atmel_nand *nand = to_atmel_nand(chip);
struct atmel_nand_controller *nc;
@@ -1464,7 +1464,7 @@ static int atmel_nand_setup_data_interface(struct nand_chip *chip, int csline,
(csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
return -EINVAL;
return nc->caps->ops->setup_data_interface(nand, csline, conf);
return nc->caps->ops->setup_interface(nand, csline, conf);
}
static void atmel_nand_init(struct atmel_nand_controller *nc,
@@ -1483,7 +1483,7 @@ static void atmel_nand_init(struct atmel_nand_controller *nc,
chip->legacy.write_buf = atmel_nand_write_buf;
chip->legacy.select_chip = atmel_nand_select_chip;
if (!nc->mck || !nc->caps->ops->setup_data_interface)
if (!nc->mck || !nc->caps->ops->setup_interface)
chip->options |= NAND_KEEP_TIMINGS;
/* Some NANDs require a longer delay than the default one (20us). */
@@ -1956,7 +1956,7 @@ static int atmel_nand_attach_chip(struct nand_chip *chip)
static const struct nand_controller_ops atmel_nand_controller_ops = {
.attach_chip = atmel_nand_attach_chip,
.setup_data_interface = atmel_nand_setup_data_interface,
.setup_interface = atmel_nand_setup_interface,
};
static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
@@ -2318,7 +2318,7 @@ static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
.remove = atmel_hsmc_nand_controller_remove,
.ecc_init = atmel_hsmc_nand_ecc_init,
.nand_init = atmel_hsmc_nand_init,
.setup_data_interface = atmel_hsmc_nand_setup_data_interface,
.setup_interface = atmel_hsmc_nand_setup_interface,
};
static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
@@ -2375,10 +2375,10 @@ atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
/*
* The SMC reg layout of at91rm9200 is completely different which prevents us
* from re-using atmel_smc_nand_setup_data_interface() for the
* ->setup_data_interface() hook.
* from re-using atmel_smc_nand_setup_interface() for the
* ->setup_interface() hook.
* At this point, there's no support for the at91rm9200 SMC IP, so we leave
* ->setup_data_interface() unassigned.
* ->setup_interface() unassigned.
*/
static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
.probe = atmel_smc_nand_controller_probe,
@@ -2399,7 +2399,7 @@ static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
.remove = atmel_smc_nand_controller_remove,
.ecc_init = atmel_nand_ecc_init,
.nand_init = atmel_smc_nand_init,
.setup_data_interface = atmel_smc_nand_setup_data_interface,
.setup_interface = atmel_smc_nand_setup_interface,
};
static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
drivers/mtd/nand/raw/brcmnand/brcmnand.c
+29 -2
View File
@@ -1918,6 +1918,22 @@ static int brcmnand_edu_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
edu_writel(ctrl, EDU_STOP, 0); /* force stop */
edu_readl(ctrl, EDU_STOP);
if (!ret && edu_cmd == EDU_CMD_READ) {
u64 err_addr = 0;
/*
* check for ECC errors here, subpage ECC errors are
* retained in ECC error address register
*/
err_addr = brcmnand_get_uncorrecc_addr(ctrl);
if (!err_addr) {
err_addr = brcmnand_get_correcc_addr(ctrl);
if (err_addr)
ret = -EUCLEAN;
} else
ret = -EBADMSG;
}
return ret;
}
@@ -2124,6 +2140,7 @@ static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
u64 err_addr = 0;
int err;
bool retry = true;
bool edu_err = false;
dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
@@ -2141,6 +2158,10 @@ try_dmaread:
else
return -EIO;
}
if (has_edu(ctrl) && err_addr)
edu_err = true;
} else {
if (oob)
memset(oob, 0x99, mtd->oobsize);
@@ -2188,6 +2209,11 @@ try_dmaread:
if (mtd_is_bitflip(err)) {
unsigned int corrected = brcmnand_count_corrected(ctrl);
/* in case of EDU correctable error we read again using PIO */
if (edu_err)
err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
oob, &err_addr);
dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
(unsigned long long)err_addr);
mtd->ecc_stats.corrected += corrected;
@@ -3023,8 +3049,9 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
if (ret < 0)
goto err;
/* set edu transfer function to call */
ctrl->dma_trans = brcmnand_edu_trans;
if (has_edu(ctrl))
/* set edu transfer function to call */
ctrl->dma_trans = brcmnand_edu_trans;
}
/* Disable automatic device ID config, direct addressing */
drivers/mtd/nand/raw/cadence-nand-controller.c
+3 -3
View File
@@ -2304,8 +2304,8 @@ static inline u32 calc_tdvw(u32 trp_cnt, u32 clk_period, u32 trhoh_min,
}
static int
cadence_nand_setup_data_interface(struct nand_chip *chip, int chipnr,
const struct nand_data_interface *conf)
cadence_nand_setup_interface(struct nand_chip *chip, int chipnr,
const struct nand_interface_config *conf)
{
const struct nand_sdr_timings *sdr;
struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
@@ -2691,7 +2691,7 @@ static int cadence_nand_attach_chip(struct nand_chip *chip)
static const struct nand_controller_ops cadence_nand_controller_ops = {
.attach_chip = cadence_nand_attach_chip,
.exec_op = cadence_nand_exec_op,
.setup_data_interface = cadence_nand_setup_data_interface,
.setup_interface = cadence_nand_setup_interface,
};
static int cadence_nand_chip_init(struct cdns_nand_ctrl *cdns_ctrl,
drivers/mtd/nand/raw/denali.c
+4 -4
View File
@@ -761,8 +761,8 @@ static int denali_write_page(struct nand_chip *chip, const u8 *buf,
return denali_page_xfer(chip, (void *)buf, mtd->writesize, page, true);
}
static int denali_setup_data_interface(struct nand_chip *chip, int chipnr,
const struct nand_data_interface *conf)
static int denali_setup_interface(struct nand_chip *chip, int chipnr,
const struct nand_interface_config *conf)
{
static const unsigned int data_setup_on_host = 10000;
struct denali_controller *denali = to_denali_controller(chip);
@@ -1173,7 +1173,7 @@ static int denali_exec_op(struct nand_chip *chip,
static const struct nand_controller_ops denali_controller_ops = {
.attach_chip = denali_attach_chip,
.exec_op = denali_exec_op,
.setup_data_interface = denali_setup_data_interface,
.setup_interface = denali_setup_interface,
};
int denali_chip_init(struct denali_controller *denali,
@@ -1230,7 +1230,7 @@ int denali_chip_init(struct denali_controller *denali,
chip->buf_align = 16;
}
/* clk rate info is needed for setup_data_interface */
/* clk rate info is needed for setup_interface */
if (!denali->clk_rate || !denali->clk_x_rate)
chip->options |= NAND_KEEP_TIMINGS;
drivers/mtd/nand/raw/fsl_upm.c
+112 -199
View File
@@ -14,32 +14,23 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/mtd.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <asm/fsl_lbc.h>
#define FSL_UPM_WAIT_RUN_PATTERN 0x1
#define FSL_UPM_WAIT_WRITE_BYTE 0x2
#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
struct fsl_upm_nand {
struct nand_controller base;
struct device *dev;
struct nand_chip chip;
int last_ctrl;
struct mtd_partition *parts;
struct fsl_upm upm;
uint8_t upm_addr_offset;
uint8_t upm_cmd_offset;
void __iomem *io_base;
int rnb_gpio[NAND_MAX_CHIPS];
struct gpio_desc *rnb_gpio[NAND_MAX_CHIPS];
uint32_t mchip_offsets[NAND_MAX_CHIPS];
uint32_t mchip_count;
uint32_t mchip_number;
int chip_delay;
uint32_t wait_flags;
};
static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
@@ -48,106 +39,6 @@ static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
chip);
}
static int fun_chip_ready(struct nand_chip *chip)
{
struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
return 1;
dev_vdbg(fun->dev, "busy\n");
return 0;
}
static void fun_wait_rnb(struct fsl_upm_nand *fun)
{
if (fun->rnb_gpio[fun->mchip_number] >= 0) {
struct mtd_info *mtd = nand_to_mtd(&fun->chip);
int cnt = 1000000;
while (--cnt && !fun_chip_ready(&fun->chip))
cpu_relax();
if (!cnt)
dev_err(fun->dev, "tired waiting for RNB\n");
} else {
ndelay(100);
}
}
static void fun_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl)
{
struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
u32 mar;
if (!(ctrl & fun->last_ctrl)) {
fsl_upm_end_pattern(&fun->upm);
if (cmd == NAND_CMD_NONE)
return;
fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
}
if (ctrl & NAND_CTRL_CHANGE) {
if (ctrl & NAND_ALE)
fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
else if (ctrl & NAND_CLE)
fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
}
mar = (cmd << (32 - fun->upm.width)) |
fun->mchip_offsets[fun->mchip_number];
fsl_upm_run_pattern(&fun->upm, chip->legacy.IO_ADDR_R, mar);
if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
fun_wait_rnb(fun);
}
static void fun_select_chip(struct nand_chip *chip, int mchip_nr)
{
struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
if (mchip_nr == -1) {
chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
} else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
fun->mchip_number = mchip_nr;
chip->legacy.IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
} else {
BUG();
}
}
static uint8_t fun_read_byte(struct nand_chip *chip)
{
struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
return in_8(fun->chip.legacy.IO_ADDR_R);
}
static void fun_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
{
struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
int i;
for (i = 0; i < len; i++)
buf[i] = in_8(fun->chip.legacy.IO_ADDR_R);
}
static void fun_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
{
struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
int i;
for (i = 0; i < len; i++) {
out_8(fun->chip.legacy.IO_ADDR_W, buf[i]);
if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
fun_wait_rnb(fun);
}
if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
fun_wait_rnb(fun);
}
static int fun_chip_init(struct fsl_upm_nand *fun,
const struct device_node *upm_np,
const struct resource *io_res)
@@ -156,21 +47,9 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
int ret;
struct device_node *flash_np;
fun->chip.legacy.IO_ADDR_R = fun->io_base;
fun->chip.legacy.IO_ADDR_W = fun->io_base;
fun->chip.legacy.cmd_ctrl = fun_cmd_ctrl;
fun->chip.legacy.chip_delay = fun->chip_delay;
fun->chip.legacy.read_byte = fun_read_byte;
fun->chip.legacy.read_buf = fun_read_buf;
fun->chip.legacy.write_buf = fun_write_buf;
fun->chip.ecc.mode = NAND_ECC_SOFT;
fun->chip.ecc.algo = NAND_ECC_HAMMING;
if (fun->mchip_count > 1)
fun->chip.legacy.select_chip = fun_select_chip;
if (fun->rnb_gpio[0] >= 0)
fun->chip.legacy.dev_ready = fun_chip_ready;
fun->chip.controller = &fun->base;
mtd->dev.parent = fun->dev;
flash_np = of_get_next_child(upm_np, NULL);
@@ -178,8 +57,9 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
return -ENODEV;
nand_set_flash_node(&fun->chip, flash_np);
mtd->name = kasprintf(GFP_KERNEL, "0x%llx.%pOFn", (u64)io_res->start,
flash_np);
mtd->name = devm_kasprintf(fun->dev, GFP_KERNEL, "0x%llx.%pOFn",
(u64)io_res->start,
flash_np);
if (!mtd->name) {
ret = -ENOMEM;
goto err;
@@ -192,51 +72,130 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
ret = mtd_device_register(mtd, NULL, 0);
err:
of_node_put(flash_np);
if (ret)
kfree(mtd->name);
return ret;
}
static int func_exec_instr(struct nand_chip *chip,
const struct nand_op_instr *instr)
{
struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
u32 mar, reg_offs = fun->mchip_offsets[fun->mchip_number];
unsigned int i;
const u8 *out;
u8 *in;
switch (instr->type) {
case NAND_OP_CMD_INSTR:
fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
mar = (instr->ctx.cmd.opcode << (32 - fun->upm.width)) |
reg_offs;
fsl_upm_run_pattern(&fun->upm, fun->io_base + reg_offs, mar);
fsl_upm_end_pattern(&fun->upm);
return 0;
case NAND_OP_ADDR_INSTR:
fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
for (i = 0; i < instr->ctx.addr.naddrs; i++) {
mar = (instr->ctx.addr.addrs[i] << (32 - fun->upm.width)) |
reg_offs;
fsl_upm_run_pattern(&fun->upm, fun->io_base + reg_offs, mar);
}
fsl_upm_end_pattern(&fun->upm);
return 0;
case NAND_OP_DATA_IN_INSTR:
in = instr->ctx.data.buf.in;
for (i = 0; i < instr->ctx.data.len; i++)
in[i] = in_8(fun->io_base + reg_offs);
return 0;
case NAND_OP_DATA_OUT_INSTR:
out = instr->ctx.data.buf.out;
for (i = 0; i < instr->ctx.data.len; i++)
out_8(fun->io_base + reg_offs, out[i]);
return 0;
case NAND_OP_WAITRDY_INSTR:
if (!fun->rnb_gpio[fun->mchip_number])
return nand_soft_waitrdy(chip, instr->ctx.waitrdy.timeout_ms);
return nand_gpio_waitrdy(chip, fun->rnb_gpio[fun->mchip_number],
instr->ctx.waitrdy.timeout_ms);
default:
return -EINVAL;
}
return 0;
}
static int fun_exec_op(struct nand_chip *chip, const struct nand_operation *op,
bool check_only)
{
struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
unsigned int i;
int ret;
if (op->cs > NAND_MAX_CHIPS)
return -EINVAL;
if (check_only)
return 0;
fun->mchip_number = op->cs;
for (i = 0; i < op->ninstrs; i++) {
ret = func_exec_instr(chip, &op->instrs[i]);
if (ret)
return ret;
if (op->instrs[i].delay_ns)
ndelay(op->instrs[i].delay_ns);
}
return 0;
}
static const struct nand_controller_ops fun_ops = {
.exec_op = fun_exec_op,
};
static int fun_probe(struct platform_device *ofdev)
{
struct fsl_upm_nand *fun;
struct resource io_res;
struct resource *io_res;
const __be32 *prop;
int rnb_gpio;
int ret;
int size;
int i;
fun = kzalloc(sizeof(*fun), GFP_KERNEL);
fun = devm_kzalloc(&ofdev->dev, sizeof(*fun), GFP_KERNEL);
if (!fun)
return -ENOMEM;
ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res);
if (ret) {
dev_err(&ofdev->dev, "can't get IO base\n");
goto err1;
}
io_res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
fun->io_base = devm_ioremap_resource(&ofdev->dev, io_res);
if (IS_ERR(fun->io_base))
return PTR_ERR(fun->io_base);
ret = fsl_upm_find(io_res.start, &fun->upm);
ret = fsl_upm_find(io_res->start, &fun->upm);
if (ret) {
dev_err(&ofdev->dev, "can't find UPM\n");
goto err1;
return ret;
}
prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
&size);
if (!prop || size != sizeof(uint32_t)) {
dev_err(&ofdev->dev, "can't get UPM address offset\n");
ret = -EINVAL;
goto err1;
return -EINVAL;
}
fun->upm_addr_offset = *prop;
prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
if (!prop || size != sizeof(uint32_t)) {
dev_err(&ofdev->dev, "can't get UPM command offset\n");
ret = -EINVAL;
goto err1;
return -EINVAL;
}
fun->upm_cmd_offset = *prop;
@@ -246,7 +205,7 @@ static int fun_probe(struct platform_device *ofdev)
fun->mchip_count = size / sizeof(uint32_t);
if (fun->mchip_count >= NAND_MAX_CHIPS) {
dev_err(&ofdev->dev, "too much multiple chips\n");
goto err1;
return -EINVAL;
}
for (i = 0; i < fun->mchip_count; i++)
fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
@@ -255,63 +214,26 @@ static int fun_probe(struct platform_device *ofdev)
}
for (i = 0; i < fun->mchip_count; i++) {
fun->rnb_gpio[i] = -1;
rnb_gpio = of_get_gpio(ofdev->dev.of_node, i);
if (rnb_gpio >= 0) {
ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
if (ret) {
dev_err(&ofdev->dev,
"can't request RNB gpio #%d\n", i);
goto err2;
}
gpio_direction_input(rnb_gpio);
fun->rnb_gpio[i] = rnb_gpio;
} else if (rnb_gpio == -EINVAL) {
fun->rnb_gpio[i] = devm_gpiod_get_index_optional(&ofdev->dev,
NULL, i,
GPIOD_IN);
if (IS_ERR(fun->rnb_gpio[i])) {
dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
goto err2;
return PTR_ERR(fun->rnb_gpio[i]);
}
}
prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
if (prop)
fun->chip_delay = be32_to_cpup(prop);
else
fun->chip_delay = 50;
prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
if (prop && size == sizeof(uint32_t))
fun->wait_flags = be32_to_cpup(prop);
else
fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN |
FSL_UPM_WAIT_WRITE_BYTE;
fun->io_base = devm_ioremap(&ofdev->dev, io_res.start,
resource_size(&io_res));
if (!fun->io_base) {
ret = -ENOMEM;
goto err2;
}
nand_controller_init(&fun->base);
fun->base.ops = &fun_ops;
fun->dev = &ofdev->dev;
fun->last_ctrl = NAND_CLE;
ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res);
ret = fun_chip_init(fun, ofdev->dev.of_node, io_res);
if (ret)
goto err2;
return ret;
dev_set_drvdata(&ofdev->dev, fun);
return 0;
err2:
for (i = 0; i < fun->mchip_count; i++) {
if (fun->rnb_gpio[i] < 0)
break;
gpio_free(fun->rnb_gpio[i]);
}
err1:
kfree(fun);
return ret;
}
static int fun_remove(struct platform_device *ofdev)
@@ -319,20 +241,11 @@ static int fun_remove(struct platform_device *ofdev)
struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
struct nand_chip *chip = &fun->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
int ret, i;
int ret;
ret = mtd_device_unregister(mtd);
WARN_ON(ret);
nand_cleanup(chip);
kfree(mtd->name);
for (i = 0; i < fun->mchip_count; i++) {
if (fun->rnb_gpio[i] < 0)
break;
gpio_free(fun->rnb_gpio[i]);
}
kfree(fun);
return 0;
}
drivers/mtd/nand/raw/fsmc_nand.c
+3 -3
View File
@@ -327,8 +327,8 @@ static int fsmc_calc_timings(struct fsmc_nand_data *host,
return 0;
}
static int fsmc_setup_data_interface(struct nand_chip *nand, int csline,
const struct nand_data_interface *conf)
static int fsmc_setup_interface(struct nand_chip *nand, int csline,
const struct nand_interface_config *conf)
{
struct fsmc_nand_data *host = nand_to_fsmc(nand);
struct fsmc_nand_timings tims;
@@ -951,7 +951,7 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand)
static const struct nand_controller_ops fsmc_nand_controller_ops = {
.attach_chip = fsmc_nand_attach_chip,
.exec_op = fsmc_exec_op,
.setup_data_interface = fsmc_setup_data_interface,
.setup_interface = fsmc_setup_interface,
};
/**
drivers/mtd/nand/raw/gpio.c
+91 -25
View File
@@ -25,8 +25,11 @@
#include <linux/mtd/nand-gpio.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/delay.h>
struct gpiomtd {
struct nand_controller base;
void __iomem *io;
void __iomem *io_sync;
struct nand_chip nand_chip;
struct gpio_nand_platdata plat;
@@ -69,34 +72,99 @@ static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
#endif
static void gpio_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
unsigned int ctrl)
static int gpio_nand_exec_instr(struct nand_chip *chip,
const struct nand_op_instr *instr)
{
struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip));
unsigned int i;
gpio_nand_dosync(gpiomtd);
if (ctrl & NAND_CTRL_CHANGE) {
if (gpiomtd->nce)
gpiod_set_value(gpiomtd->nce, !(ctrl & NAND_NCE));
gpiod_set_value(gpiomtd->cle, !!(ctrl & NAND_CLE));
gpiod_set_value(gpiomtd->ale, !!(ctrl & NAND_ALE));
switch (instr->type) {
case NAND_OP_CMD_INSTR:
gpio_nand_dosync(gpiomtd);
}
if (cmd == NAND_CMD_NONE)
return;
gpiod_set_value(gpiomtd->cle, 1);
gpio_nand_dosync(gpiomtd);
writeb(instr->ctx.cmd.opcode, gpiomtd->io);
gpio_nand_dosync(gpiomtd);
gpiod_set_value(gpiomtd->cle, 0);
return 0;
writeb(cmd, gpiomtd->nand_chip.legacy.IO_ADDR_W);
gpio_nand_dosync(gpiomtd);
case NAND_OP_ADDR_INSTR:
gpio_nand_dosync(gpiomtd);
gpiod_set_value(gpiomtd->ale, 1);
gpio_nand_dosync(gpiomtd);
for (i = 0; i < instr->ctx.addr.naddrs; i++)
writeb(instr->ctx.addr.addrs[i], gpiomtd->io);
gpio_nand_dosync(gpiomtd);
gpiod_set_value(gpiomtd->ale, 0);
return 0;
case NAND_OP_DATA_IN_INSTR:
gpio_nand_dosync(gpiomtd);
if ((chip->options & NAND_BUSWIDTH_16) &&
!instr->ctx.data.force_8bit)
ioread16_rep(gpiomtd->io, instr->ctx.data.buf.in,
instr->ctx.data.len / 2);
else
ioread8_rep(gpiomtd->io, instr->ctx.data.buf.in,
instr->ctx.data.len);
return 0;
case NAND_OP_DATA_OUT_INSTR:
gpio_nand_dosync(gpiomtd);
if ((chip->options & NAND_BUSWIDTH_16) &&
!instr->ctx.data.force_8bit)
iowrite16_rep(gpiomtd->io, instr->ctx.data.buf.out,
instr->ctx.data.len / 2);
else
iowrite8_rep(gpiomtd->io, instr->ctx.data.buf.out,
instr->ctx.data.len);
return 0;
case NAND_OP_WAITRDY_INSTR:
if (!gpiomtd->rdy)
return nand_soft_waitrdy(chip, instr->ctx.waitrdy.timeout_ms);
return nand_gpio_waitrdy(chip, gpiomtd->rdy,
instr->ctx.waitrdy.timeout_ms);
default:
return -EINVAL;
}
return 0;
}
static int gpio_nand_devready(struct nand_chip *chip)
static int gpio_nand_exec_op(struct nand_chip *chip,
const struct nand_operation *op,
bool check_only)
{
struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip));
unsigned int i;
int ret = 0;
return gpiod_get_value(gpiomtd->rdy);
if (check_only)
return 0;
gpio_nand_dosync(gpiomtd);
gpiod_set_value(gpiomtd->nce, 0);
for (i = 0; i < op->ninstrs; i++) {
ret = gpio_nand_exec_instr(chip, &op->instrs[i]);
if (ret)
break;
if (op->instrs[i].delay_ns)
ndelay(op->instrs[i].delay_ns);
}
gpio_nand_dosync(gpiomtd);
gpiod_set_value(gpiomtd->nce, 1);
return ret;
}
static const struct nand_controller_ops gpio_nand_ops = {
.exec_op = gpio_nand_exec_op,
};
#ifdef CONFIG_OF
static const struct of_device_id gpio_nand_id_table[] = {
{ .compatible = "gpio-control-nand" },
@@ -225,9 +293,9 @@ static int gpio_nand_probe(struct platform_device *pdev)
chip = &gpiomtd->nand_chip;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
chip->legacy.IO_ADDR_R = devm_ioremap_resource(dev, res);
if (IS_ERR(chip->legacy.IO_ADDR_R))
return PTR_ERR(chip->legacy.IO_ADDR_R);
gpiomtd->io = devm_ioremap_resource(dev, res);
if (IS_ERR(gpiomtd->io))
return PTR_ERR(gpiomtd->io);
res = gpio_nand_get_io_sync(pdev);
if (res) {
@@ -269,17 +337,15 @@ static int gpio_nand_probe(struct platform_device *pdev)
ret = PTR_ERR(gpiomtd->rdy);
goto out_ce;
}
/* Using RDY pin */
if (gpiomtd->rdy)
chip->legacy.dev_ready = gpio_nand_devready;
nand_controller_init(&gpiomtd->base);
gpiomtd->base.ops = &gpio_nand_ops;
nand_set_flash_node(chip, pdev->dev.of_node);
chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
chip->ecc.mode = NAND_ECC_SOFT;
chip->ecc.algo = NAND_ECC_HAMMING;
chip->options = gpiomtd->plat.options;
chip->legacy.chip_delay = gpiomtd->plat.chip_delay;
chip->legacy.cmd_ctrl = gpio_nand_cmd_ctrl;
chip->controller = &gpiomtd->base;
mtd = nand_to_mtd(chip);
mtd->dev.parent = dev;
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
+3 -3
View File
@@ -736,8 +736,8 @@ static void gpmi_nfc_apply_timings(struct gpmi_nand_data *this)
udelay(dll_wait_time_us);
}
static int gpmi_setup_data_interface(struct nand_chip *chip, int chipnr,
const struct nand_data_interface *conf)
static int gpmi_setup_interface(struct nand_chip *chip, int chipnr,
const struct nand_interface_config *conf)
{
struct gpmi_nand_data *this = nand_get_controller_data(chip);
const struct nand_sdr_timings *sdr;
@@ -2400,7 +2400,7 @@ unmap:
static const struct nand_controller_ops gpmi_nand_controller_ops = {
.attach_chip = gpmi_nand_attach_chip,
.setup_data_interface = gpmi_setup_data_interface,
.setup_interface = gpmi_setup_interface,
.exec_op = gpmi_nfc_exec_op,
};
drivers/mtd/nand/raw/ingenic/jz4740_ecc.c
+2 -2
View File
@@ -90,8 +90,8 @@ static int jz4740_ecc_calculate(struct ingenic_ecc *ecc,
* If the written data is completely 0xff, we also want to write 0xff as
* ECC, otherwise we will get in trouble when doing subpage writes.
*/
if (memcmp(ecc_code, empty_block_ecc, ARRAY_SIZE(empty_block_ecc)) == 0)
memset(ecc_code, 0xff, ARRAY_SIZE(empty_block_ecc));
if (memcmp(ecc_code, empty_block_ecc, sizeof(empty_block_ecc)) == 0)
memset(ecc_code, 0xff, sizeof(empty_block_ecc));
return 0;
}
drivers/mtd/nand/raw/internals.h
+15 -8
View File
@@ -53,12 +53,12 @@ struct nand_manufacturer_ops {
};
/**
* struct nand_manufacturer - NAND Flash Manufacturer structure
* struct nand_manufacturer_desc - NAND Flash Manufacturer descriptor
* @name: Manufacturer name
* @id: manufacturer ID code of device.
* @ops: manufacturer operations
*/
struct nand_manufacturer {
struct nand_manufacturer_desc {
int id;
char *name;
const struct nand_manufacturer_ops *ops;
@@ -79,14 +79,21 @@ extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops;
extern const struct mtd_pairing_scheme dist3_pairing_scheme;
/* Core functions */
const struct nand_manufacturer *nand_get_manufacturer(u8 id);
const struct nand_manufacturer_desc *nand_get_manufacturer_desc(u8 id);
int nand_bbm_get_next_page(struct nand_chip *chip, int page);
int nand_markbad_bbm(struct nand_chip *chip, loff_t ofs);
int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
int allowbbt);
int onfi_fill_data_interface(struct nand_chip *chip,
enum nand_data_interface_type type,
int timing_mode);
void onfi_fill_interface_config(struct nand_chip *chip,
struct nand_interface_config *iface,
enum nand_interface_type type,
unsigned int timing_mode);
unsigned int
onfi_find_closest_sdr_mode(const struct nand_sdr_timings *spec_timings);
int nand_choose_best_sdr_timings(struct nand_chip *chip,
struct nand_interface_config *iface,
struct nand_sdr_timings *spec_timings);
const struct nand_interface_config *nand_get_reset_interface_config(void);
int nand_get_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
int nand_set_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
int nand_read_page_raw_notsupp(struct nand_chip *chip, u8 *buf,
@@ -130,10 +137,10 @@ static inline int nand_exec_op(struct nand_chip *chip,
return chip->controller->ops->exec_op(chip, op, false);
}
static inline bool nand_has_setup_data_iface(struct nand_chip *chip)
static inline bool nand_controller_can_setup_interface(struct nand_chip *chip)
{
if (!chip->controller || !chip->controller->ops ||
!chip->controller->ops->setup_data_interface)
!chip->controller->ops->setup_interface)
return false;
if (chip->options & NAND_KEEP_TIMINGS)
drivers/mtd/nand/raw/marvell_nand.c
+10 -8
View File
@@ -1096,6 +1096,8 @@ static int marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip *chip,
const u8 *oob_buf, bool raw,
int page)
{
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(nand_get_interface_config(chip));
struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
@@ -1141,7 +1143,7 @@ static int marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip *chip,
return ret;
ret = marvell_nfc_wait_op(chip,
PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max));
PSEC_TO_MSEC(sdr->tPROG_max));
return ret;
}
@@ -1562,6 +1564,8 @@ static int marvell_nfc_hw_ecc_bch_write_page(struct nand_chip *chip,
const u8 *buf,
int oob_required, int page)
{
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(nand_get_interface_config(chip));
struct mtd_info *mtd = nand_to_mtd(chip);
const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
const u8 *data = buf;
@@ -1598,8 +1602,7 @@ static int marvell_nfc_hw_ecc_bch_write_page(struct nand_chip *chip,
marvell_nfc_wait_ndrun(chip);
}
ret = marvell_nfc_wait_op(chip,
PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max));
ret = marvell_nfc_wait_op(chip, PSEC_TO_MSEC(sdr->tPROG_max));
marvell_nfc_disable_hw_ecc(chip);
@@ -2305,9 +2308,8 @@ static struct nand_bbt_descr bbt_mirror_descr = {
.pattern = bbt_mirror_pattern
};
static int marvell_nfc_setup_data_interface(struct nand_chip *chip, int chipnr,
const struct nand_data_interface
*conf)
static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr,
const struct nand_interface_config *conf)
{
struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
@@ -2508,7 +2510,7 @@ static int marvell_nand_attach_chip(struct nand_chip *chip)
static const struct nand_controller_ops marvell_nand_controller_ops = {
.attach_chip = marvell_nand_attach_chip,
.exec_op = marvell_nfc_exec_op,
.setup_data_interface = marvell_nfc_setup_data_interface,
.setup_interface = marvell_nfc_setup_interface,
};
static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
@@ -2644,7 +2646,7 @@ static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
/*
* Save a reference value for timing registers before
* ->setup_data_interface() is called.
* ->setup_interface() is called.
*/
marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0);
marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1);
drivers/mtd/nand/raw/meson_nand.c
+7 -7
View File
@@ -573,10 +573,10 @@ static int meson_nfc_write_buf(struct nand_chip *nand, u8 *buf, int len)
static int meson_nfc_rw_cmd_prepare_and_execute(struct nand_chip *nand,
int page, bool in)
{
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(nand_get_interface_config(nand));
struct mtd_info *mtd = nand_to_mtd(nand);
struct meson_nfc *nfc = nand_get_controller_data(nand);
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&nand->data_interface);
u32 *addrs = nfc->cmdfifo.rw.addrs;
u32 cs = nfc->param.chip_select;
u32 cmd0, cmd_num, row_start;
@@ -626,9 +626,9 @@ static int meson_nfc_rw_cmd_prepare_and_execute(struct nand_chip *nand,
static int meson_nfc_write_page_sub(struct nand_chip *nand,
int page, int raw)
{
struct mtd_info *mtd = nand_to_mtd(nand);
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&nand->data_interface);
nand_get_sdr_timings(nand_get_interface_config(nand));
struct mtd_info *mtd = nand_to_mtd(nand);
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
struct meson_nfc *nfc = nand_get_controller_data(nand);
int data_len, info_len;
@@ -1097,8 +1097,8 @@ static int meson_chip_buffer_init(struct nand_chip *nand)
}
static
int meson_nfc_setup_data_interface(struct nand_chip *nand, int csline,
const struct nand_data_interface *conf)
int meson_nfc_setup_interface(struct nand_chip *nand, int csline,
const struct nand_interface_config *conf)
{
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
const struct nand_sdr_timings *timings;
@@ -1222,7 +1222,7 @@ static int meson_nand_attach_chip(struct nand_chip *nand)
static const struct nand_controller_ops meson_nand_controller_ops = {
.attach_chip = meson_nand_attach_chip,
.detach_chip = meson_nand_detach_chip,
.setup_data_interface = meson_nfc_setup_data_interface,
.setup_interface = meson_nfc_setup_interface,
.exec_op = meson_nfc_exec_op,
};
drivers/mtd/nand/raw/mtk_nand.c
+74 -48
View File
@@ -387,44 +387,6 @@ static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd)
return 0;
}
static void mtk_nfc_select_chip(struct nand_chip *nand, int chip)
{
struct mtk_nfc *nfc = nand_get_controller_data(nand);
struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(nand);
if (chip < 0)
return;
mtk_nfc_hw_runtime_config(nand_to_mtd(nand));
nfi_writel(nfc, mtk_nand->sels[chip], NFI_CSEL);
}
static int mtk_nfc_dev_ready(struct nand_chip *nand)
{
struct mtk_nfc *nfc = nand_get_controller_data(nand);
if (nfi_readl(nfc, NFI_STA) & STA_BUSY)
return 0;
return 1;
}
static void mtk_nfc_cmd_ctrl(struct nand_chip *chip, int dat,
unsigned int ctrl)
{
struct mtk_nfc *nfc = nand_get_controller_data(chip);
if (ctrl & NAND_ALE) {
mtk_nfc_send_address(nfc, dat);
} else if (ctrl & NAND_CLE) {
mtk_nfc_hw_reset(nfc);
nfi_writew(nfc, CNFG_OP_CUST, NFI_CNFG);
mtk_nfc_send_command(nfc, dat);
}
}
static inline void mtk_nfc_wait_ioready(struct mtk_nfc *nfc)
{
int rc;
@@ -501,8 +463,76 @@ static void mtk_nfc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
mtk_nfc_write_byte(chip, buf[i]);
}
static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
const struct nand_data_interface *conf)
static int mtk_nfc_exec_instr(struct nand_chip *chip,
const struct nand_op_instr *instr)
{
struct mtk_nfc *nfc = nand_get_controller_data(chip);
unsigned int i;
u32 status;
switch (instr->type) {
case NAND_OP_CMD_INSTR:
mtk_nfc_send_command(nfc, instr->ctx.cmd.opcode);
return 0;
case NAND_OP_ADDR_INSTR:
for (i = 0; i < instr->ctx.addr.naddrs; i++)
mtk_nfc_send_address(nfc, instr->ctx.addr.addrs[i]);
return 0;
case NAND_OP_DATA_IN_INSTR:
mtk_nfc_read_buf(chip, instr->ctx.data.buf.in,
instr->ctx.data.len);
return 0;
case NAND_OP_DATA_OUT_INSTR:
mtk_nfc_write_buf(chip, instr->ctx.data.buf.out,
instr->ctx.data.len);
return 0;
case NAND_OP_WAITRDY_INSTR:
return readl_poll_timeout(nfc->regs + NFI_STA, status,
status & STA_BUSY, 20,
instr->ctx.waitrdy.timeout_ms);
default:
break;
}
return -EINVAL;
}
static void mtk_nfc_select_target(struct nand_chip *nand, unsigned int cs)
{
struct mtk_nfc *nfc = nand_get_controller_data(nand);
struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(nand);
mtk_nfc_hw_runtime_config(nand_to_mtd(nand));
nfi_writel(nfc, mtk_nand->sels[cs], NFI_CSEL);
}
static int mtk_nfc_exec_op(struct nand_chip *chip,
const struct nand_operation *op,
bool check_only)
{
struct mtk_nfc *nfc = nand_get_controller_data(chip);
unsigned int i;
int ret = 0;
if (check_only)
return 0;
mtk_nfc_hw_reset(nfc);
nfi_writew(nfc, CNFG_OP_CUST, NFI_CNFG);
mtk_nfc_select_target(chip, op->cs);
for (i = 0; i < op->ninstrs; i++) {
ret = mtk_nfc_exec_instr(chip, &op->instrs[i]);
if (ret)
break;
}
return ret;
}
static int mtk_nfc_setup_interface(struct nand_chip *chip, int csline,
const struct nand_interface_config *conf)
{
struct mtk_nfc *nfc = nand_get_controller_data(chip);
const struct nand_sdr_timings *timings;
@@ -803,6 +833,7 @@ static int mtk_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
u32 reg;
int ret;
mtk_nfc_select_target(chip, chip->cur_cs);
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
if (!raw) {
@@ -920,6 +951,7 @@ static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
u8 *buf;
int rc;
mtk_nfc_select_target(chip, chip->cur_cs);
start = data_offs / chip->ecc.size;
end = DIV_ROUND_UP(data_offs + readlen, chip->ecc.size);
@@ -1325,7 +1357,8 @@ static int mtk_nfc_attach_chip(struct nand_chip *chip)
static const struct nand_controller_ops mtk_nfc_controller_ops = {
.attach_chip = mtk_nfc_attach_chip,
.setup_data_interface = mtk_nfc_setup_data_interface,
.setup_interface = mtk_nfc_setup_interface,
.exec_op = mtk_nfc_exec_op,
};
static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
@@ -1381,13 +1414,6 @@ static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
nand_set_controller_data(nand, nfc);
nand->options |= NAND_USES_DMA | NAND_SUBPAGE_READ;
nand->legacy.dev_ready = mtk_nfc_dev_ready;
nand->legacy.select_chip = mtk_nfc_select_chip;
nand->legacy.write_byte = mtk_nfc_write_byte;
nand->legacy.write_buf = mtk_nfc_write_buf;
nand->legacy.read_byte = mtk_nfc_read_byte;
nand->legacy.read_buf = mtk_nfc_read_buf;
nand->legacy.cmd_ctrl = mtk_nfc_cmd_ctrl;
/* set default mode in case dt entry is missing */
nand->ecc.mode = NAND_ECC_HW;
drivers/mtd/nand/raw/mxc_nand.c
+11 -11
View File
@@ -137,8 +137,8 @@ struct mxc_nand_devtype_data {
u32 (*get_ecc_status)(struct mxc_nand_host *);
const struct mtd_ooblayout_ops *ooblayout;
void (*select_chip)(struct nand_chip *chip, int cs);
int (*setup_data_interface)(struct nand_chip *chip, int csline,
const struct nand_data_interface *conf);
int (*setup_interface)(struct nand_chip *chip, int csline,
const struct nand_interface_config *conf);
void (*enable_hwecc)(struct nand_chip *chip, bool enable);
/*
@@ -1139,8 +1139,8 @@ static void preset_v1(struct mtd_info *mtd)
writew(0x4, NFC_V1_V2_WRPROT);
}
static int mxc_nand_v2_setup_data_interface(struct nand_chip *chip, int csline,
const struct nand_data_interface *conf)
static int mxc_nand_v2_setup_interface(struct nand_chip *chip, int csline,
const struct nand_interface_config *conf)
{
struct mxc_nand_host *host = nand_get_controller_data(chip);
int tRC_min_ns, tRC_ps, ret;
@@ -1432,7 +1432,7 @@ static int mxc_nand_get_features(struct nand_chip *chip, int addr,
}
/*
* The generic flash bbt decriptors overlap with our ecc
* The generic flash bbt descriptors overlap with our ecc
* hardware, so define some i.MX specific ones.
*/
static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
@@ -1521,7 +1521,7 @@ static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
.get_ecc_status = get_ecc_status_v2,
.ooblayout = &mxc_v2_ooblayout_ops,
.select_chip = mxc_nand_select_chip_v2,
.setup_data_interface = mxc_nand_v2_setup_data_interface,
.setup_interface = mxc_nand_v2_setup_interface,
.enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
.irqpending_quirk = 0,
.needs_ip = 0,
@@ -1738,17 +1738,17 @@ static int mxcnd_attach_chip(struct nand_chip *chip)
return 0;
}
static int mxcnd_setup_data_interface(struct nand_chip *chip, int chipnr,
const struct nand_data_interface *conf)
static int mxcnd_setup_interface(struct nand_chip *chip, int chipnr,
const struct nand_interface_config *conf)
{
struct mxc_nand_host *host = nand_get_controller_data(chip);
return host->devtype_data->setup_data_interface(chip, chipnr, conf);
return host->devtype_data->setup_interface(chip, chipnr, conf);
}
static const struct nand_controller_ops mxcnd_controller_ops = {
.attach_chip = mxcnd_attach_chip,
.setup_data_interface = mxcnd_setup_data_interface,
.setup_interface = mxcnd_setup_interface,
};
static int mxcnd_probe(struct platform_device *pdev)
@@ -1809,7 +1809,7 @@ static int mxcnd_probe(struct platform_device *pdev)
if (err < 0)
return err;
if (!host->devtype_data->setup_data_interface)
if (!host->devtype_data->setup_interface)
this->options |= NAND_KEEP_TIMINGS;
if (host->devtype_data->needs_ip) {
drivers/mtd/nand/raw/mxic_nand.c
+3 -3
View File
@@ -451,8 +451,8 @@ static int mxic_nfc_exec_op(struct nand_chip *chip,
return ret;
}
static int mxic_nfc_setup_data_interface(struct nand_chip *chip, int chipnr,
const struct nand_data_interface *conf)
static int mxic_nfc_setup_interface(struct nand_chip *chip, int chipnr,
const struct nand_interface_config *conf)
{
struct mxic_nand_ctlr *nfc = nand_get_controller_data(chip);
const struct nand_sdr_timings *sdr;
@@ -480,7 +480,7 @@ static int mxic_nfc_setup_data_interface(struct nand_chip *chip, int chipnr,
static const struct nand_controller_ops mxic_nand_controller_ops = {
.exec_op = mxic_nfc_exec_op,
.setup_data_interface = mxic_nfc_setup_data_interface,
.setup_interface = mxic_nfc_setup_interface,
};
static int mxic_nfc_probe(struct platform_device *pdev)
drivers/mtd/nand/raw/nand_base.c
+154 -121
View File
@@ -773,7 +773,7 @@ int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)
return -ENOTSUPP;
/* Wait tWB before polling the STATUS reg. */
timings = nand_get_sdr_timings(&chip->data_interface);
timings = nand_get_sdr_timings(nand_get_interface_config(chip));
ndelay(PSEC_TO_NSEC(timings->tWB_max));
ret = nand_status_op(chip, NULL);
@@ -898,7 +898,7 @@ static bool nand_supports_set_features(struct nand_chip *chip, int addr)
}
/**
* nand_reset_data_interface - Reset data interface and timings
* nand_reset_interface - Reset data interface and timings
* @chip: The NAND chip
* @chipnr: Internal die id
*
@@ -906,11 +906,12 @@ static bool nand_supports_set_features(struct nand_chip *chip, int addr)
*
* Returns 0 for success or negative error code otherwise.
*/
static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
static int nand_reset_interface(struct nand_chip *chip, int chipnr)
{
const struct nand_controller_ops *ops = chip->controller->ops;
int ret;
if (!nand_has_setup_data_iface(chip))
if (!nand_controller_can_setup_interface(chip))
return 0;
/*
@@ -927,9 +928,9 @@ static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
* timings to timing mode 0.
*/
onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0);
ret = chip->controller->ops->setup_data_interface(chip, chipnr,
&chip->data_interface);
chip->current_interface_config = nand_get_reset_interface_config();
ret = ops->setup_interface(chip, chipnr,
chip->current_interface_config);
if (ret)
pr_err("Failed to configure data interface to SDR timing mode 0\n");
@@ -937,28 +938,36 @@ static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
}
/**
* nand_setup_data_interface - Setup the best data interface and timings
* nand_setup_interface - Setup the best data interface and timings
* @chip: The NAND chip
* @chipnr: Internal die id
*
* Find and configure the best data interface and NAND timings supported by
* the chip and the driver.
* First tries to retrieve supported timing modes from ONFI information,
* and if the NAND chip does not support ONFI, relies on the
* ->onfi_timing_mode_default specified in the nand_ids table.
* Configure what has been reported to be the best data interface and NAND
* timings supported by the chip and the driver.
*
* Returns 0 for success or negative error code otherwise.
*/
static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
static int nand_setup_interface(struct nand_chip *chip, int chipnr)
{
u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
chip->onfi_timing_mode_default,
};
const struct nand_controller_ops *ops = chip->controller->ops;
u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { };
int ret;
if (!nand_has_setup_data_iface(chip))
if (!nand_controller_can_setup_interface(chip))
return 0;
/*
* A nand_reset_interface() put both the NAND chip and the NAND
* controller in timings mode 0. If the default mode for this chip is
* also 0, no need to proceed to the change again. Plus, at probe time,
* nand_setup_interface() uses ->set/get_features() which would
* fail anyway as the parameter page is not available yet.
*/
if (!chip->best_interface_config)
return 0;
tmode_param[0] = chip->best_interface_config->timings.mode;
/* Change the mode on the chip side (if supported by the NAND chip) */
if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) {
nand_select_target(chip, chipnr);
@@ -970,14 +979,13 @@ static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
}
/* Change the mode on the controller side */
ret = chip->controller->ops->setup_data_interface(chip, chipnr,
&chip->data_interface);
ret = ops->setup_interface(chip, chipnr, chip->best_interface_config);
if (ret)
return ret;
/* Check the mode has been accepted by the chip, if supported */
if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE))
return 0;
goto update_interface_config;
memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
nand_select_target(chip, chipnr);
@@ -987,12 +995,15 @@ static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
if (ret)
goto err_reset_chip;
if (tmode_param[0] != chip->onfi_timing_mode_default) {
if (tmode_param[0] != chip->best_interface_config->timings.mode) {
pr_warn("timing mode %d not acknowledged by the NAND chip\n",
chip->onfi_timing_mode_default);
chip->best_interface_config->timings.mode);
goto err_reset_chip;
}
update_interface_config:
chip->current_interface_config = chip->best_interface_config;
return 0;
err_reset_chip:
@@ -1000,7 +1011,7 @@ err_reset_chip:
* Fallback to mode 0 if the chip explicitly did not ack the chosen
* timing mode.
*/
nand_reset_data_interface(chip, chipnr);
nand_reset_interface(chip, chipnr);
nand_select_target(chip, chipnr);
nand_reset_op(chip);
nand_deselect_target(chip);
@@ -1009,59 +1020,90 @@ err_reset_chip:
}
/**
* nand_init_data_interface - find the best data interface and timings
* nand_choose_best_sdr_timings - Pick up the best SDR timings that both the
* NAND controller and the NAND chip support
* @chip: the NAND chip
* @iface: the interface configuration (can eventually be updated)
* @spec_timings: specific timings, when not fitting the ONFI specification
*
* If specific timings are provided, use them. Otherwise, retrieve supported
* timing modes from ONFI information.
*/
int nand_choose_best_sdr_timings(struct nand_chip *chip,
struct nand_interface_config *iface,
struct nand_sdr_timings *spec_timings)
{
const struct nand_controller_ops *ops = chip->controller->ops;
int best_mode = 0, mode, ret;
iface->type = NAND_SDR_IFACE;
if (spec_timings) {
iface->timings.sdr = *spec_timings;
iface->timings.mode = onfi_find_closest_sdr_mode(spec_timings);
/* Verify the controller supports the requested interface */
ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
iface);
if (!ret) {
chip->best_interface_config = iface;
return ret;
}
/* Fallback to slower modes */
best_mode = iface->timings.mode;
} else if (chip->parameters.onfi) {
best_mode = fls(chip->parameters.onfi->async_timing_mode) - 1;
}
for (mode = best_mode; mode >= 0; mode--) {
onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, mode);
ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
iface);
if (!ret)
break;
}
chip->best_interface_config = iface;
return 0;
}
/**
* nand_choose_interface_config - find the best data interface and timings
* @chip: The NAND chip
*
* Find the best data interface and NAND timings supported by the chip
* and the driver.
* First tries to retrieve supported timing modes from ONFI information,
* and if the NAND chip does not support ONFI, relies on the
* ->onfi_timing_mode_default specified in the nand_ids table. After this
* function nand_chip->data_interface is initialized with the best timing mode
* available.
* and the driver. Eventually let the NAND manufacturer driver propose his own
* set of timings.
*
* After this function nand_chip->interface_config is initialized with the best
* timing mode available.
*
* Returns 0 for success or negative error code otherwise.
*/
static int nand_init_data_interface(struct nand_chip *chip)
static int nand_choose_interface_config(struct nand_chip *chip)
{
int modes, mode, ret;
struct nand_interface_config *iface;
int ret;
if (!nand_has_setup_data_iface(chip))
if (!nand_controller_can_setup_interface(chip))
return 0;
/*
* First try to identify the best timings from ONFI parameters and
* if the NAND does not support ONFI, fallback to the default ONFI
* timing mode.
*/
if (chip->parameters.onfi) {
modes = chip->parameters.onfi->async_timing_mode;
} else {
if (!chip->onfi_timing_mode_default)
return 0;
iface = kzalloc(sizeof(*iface), GFP_KERNEL);
if (!iface)
return -ENOMEM;
modes = GENMASK(chip->onfi_timing_mode_default, 0);
}
if (chip->ops.choose_interface_config)
ret = chip->ops.choose_interface_config(chip, iface);
else
ret = nand_choose_best_sdr_timings(chip, iface, NULL);
for (mode = fls(modes) - 1; mode >= 0; mode--) {
ret = onfi_fill_data_interface(chip, NAND_SDR_IFACE, mode);
if (ret)
continue;
if (ret)
kfree(iface);
/*
* Pass NAND_DATA_IFACE_CHECK_ONLY to only check if the
* controller supports the requested timings.
*/
ret = chip->controller->ops->setup_data_interface(chip,
NAND_DATA_IFACE_CHECK_ONLY,
&chip->data_interface);
if (!ret) {
chip->onfi_timing_mode_default = mode;
break;
}
}
return 0;
return ret;
}
/**
@@ -1122,9 +1164,9 @@ static int nand_sp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
unsigned int offset_in_page, void *buf,
unsigned int len)
{
struct mtd_info *mtd = nand_to_mtd(chip);
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
struct mtd_info *mtd = nand_to_mtd(chip);
u8 addrs[4];
struct nand_op_instr instrs[] = {
NAND_OP_CMD(NAND_CMD_READ0, 0),
@@ -1166,7 +1208,7 @@ static int nand_lp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
unsigned int len)
{
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
u8 addrs[5];
struct nand_op_instr instrs[] = {
NAND_OP_CMD(NAND_CMD_READ0, 0),
@@ -1263,7 +1305,7 @@ int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
if (nand_has_exec_op(chip)) {
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
struct nand_op_instr instrs[] = {
NAND_OP_CMD(NAND_CMD_PARAM, 0),
NAND_OP_ADDR(1, &page, PSEC_TO_NSEC(sdr->tWB_max)),
@@ -1318,7 +1360,7 @@ int nand_change_read_column_op(struct nand_chip *chip,
if (nand_has_exec_op(chip)) {
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
u8 addrs[2] = {};
struct nand_op_instr instrs[] = {
NAND_OP_CMD(NAND_CMD_RNDOUT, 0),
@@ -1392,9 +1434,9 @@ static int nand_exec_prog_page_op(struct nand_chip *chip, unsigned int page,
unsigned int offset_in_page, const void *buf,
unsigned int len, bool prog)
{
struct mtd_info *mtd = nand_to_mtd(chip);
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
struct mtd_info *mtd = nand_to_mtd(chip);
u8 addrs[5] = {};
struct nand_op_instr instrs[] = {
/*
@@ -1517,7 +1559,7 @@ int nand_prog_page_end_op(struct nand_chip *chip)
if (nand_has_exec_op(chip)) {
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
struct nand_op_instr instrs[] = {
NAND_OP_CMD(NAND_CMD_PAGEPROG,
PSEC_TO_NSEC(sdr->tWB_max)),
@@ -1624,7 +1666,7 @@ int nand_change_write_column_op(struct nand_chip *chip,
if (nand_has_exec_op(chip)) {
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
u8 addrs[2];
struct nand_op_instr instrs[] = {
NAND_OP_CMD(NAND_CMD_RNDIN, 0),
@@ -1679,7 +1721,7 @@ int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
if (nand_has_exec_op(chip)) {
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
struct nand_op_instr instrs[] = {
NAND_OP_CMD(NAND_CMD_READID, 0),
NAND_OP_ADDR(1, &addr, PSEC_TO_NSEC(sdr->tADL_min)),
@@ -1718,7 +1760,7 @@ int nand_status_op(struct nand_chip *chip, u8 *status)
{
if (nand_has_exec_op(chip)) {
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
struct nand_op_instr instrs[] = {
NAND_OP_CMD(NAND_CMD_STATUS,
PSEC_TO_NSEC(sdr->tADL_min)),
@@ -1787,7 +1829,7 @@ int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
if (nand_has_exec_op(chip)) {
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
u8 addrs[3] = { page, page >> 8, page >> 16 };
struct nand_op_instr instrs[] = {
NAND_OP_CMD(NAND_CMD_ERASE1, 0),
@@ -1846,7 +1888,7 @@ static int nand_set_features_op(struct nand_chip *chip, u8 feature,
if (nand_has_exec_op(chip)) {
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
struct nand_op_instr instrs[] = {
NAND_OP_CMD(NAND_CMD_SET_FEATURES, 0),
NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tADL_min)),
@@ -1893,7 +1935,7 @@ static int nand_get_features_op(struct nand_chip *chip, u8 feature,
if (nand_has_exec_op(chip)) {
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
struct nand_op_instr instrs[] = {
NAND_OP_CMD(NAND_CMD_GET_FEATURES, 0),
NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tWB_max)),
@@ -1950,7 +1992,7 @@ int nand_reset_op(struct nand_chip *chip)
{
if (nand_has_exec_op(chip)) {
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
struct nand_op_instr instrs[] = {
NAND_OP_CMD(NAND_CMD_RESET, PSEC_TO_NSEC(sdr->tWB_max)),
NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tRST_max), 0),
@@ -2480,17 +2522,16 @@ EXPORT_SYMBOL_GPL(nand_subop_get_data_len);
* @chipnr: Internal die id
*
* Save the timings data structure, then apply SDR timings mode 0 (see
* nand_reset_data_interface for details), do the reset operation, and
* apply back the previous timings.
* nand_reset_interface for details), do the reset operation, and apply
* back the previous timings.
*
* Returns 0 on success, a negative error code otherwise.
*/
int nand_reset(struct nand_chip *chip, int chipnr)
{
struct nand_data_interface saved_data_intf = chip->data_interface;
int ret;
ret = nand_reset_data_interface(chip, chipnr);
ret = nand_reset_interface(chip, chipnr);
if (ret)
return ret;
@@ -2505,18 +2546,7 @@ int nand_reset(struct nand_chip *chip, int chipnr)
if (ret)
return ret;
/*
* A nand_reset_data_interface() put both the NAND chip and the NAND
* controller in timings mode 0. If the default mode for this chip is
* also 0, no need to proceed to the change again. Plus, at probe time,
* nand_setup_data_interface() uses ->set/get_features() which would
* fail anyway as the parameter page is not available yet.
*/
if (!chip->onfi_timing_mode_default)
return 0;
chip->data_interface = saved_data_intf;
ret = nand_setup_data_interface(chip, chipnr);
ret = nand_setup_interface(chip, chipnr);
if (ret)
return ret;
@@ -3215,10 +3245,10 @@ static int nand_setup_read_retry(struct nand_chip *chip, int retry_mode)
if (retry_mode >= chip->read_retries)
return -EINVAL;
if (!chip->setup_read_retry)
if (!chip->ops.setup_read_retry)
return -EOPNOTSUPP;
return chip->setup_read_retry(chip, retry_mode);
return chip->ops.setup_read_retry(chip, retry_mode);
}
static void nand_wait_readrdy(struct nand_chip *chip)
@@ -3228,7 +3258,7 @@ static void nand_wait_readrdy(struct nand_chip *chip)
if (!(chip->options & NAND_NEED_READRDY))
return;
sdr = nand_get_sdr_timings(&chip->data_interface);
sdr = nand_get_sdr_timings(nand_get_interface_config(chip));
WARN_ON(nand_wait_rdy_op(chip, PSEC_TO_MSEC(sdr->tR_max), 0));
}
@@ -4462,8 +4492,8 @@ static int nand_suspend(struct mtd_info *mtd)
int ret = 0;
mutex_lock(&chip->lock);
if (chip->suspend)
ret = chip->suspend(chip);
if (chip->ops.suspend)
ret = chip->ops.suspend(chip);
if (!ret)
chip->suspended = 1;
mutex_unlock(&chip->lock);
@@ -4481,8 +4511,8 @@ static void nand_resume(struct mtd_info *mtd)
mutex_lock(&chip->lock);
if (chip->suspended) {
if (chip->resume)
chip->resume(chip);
if (chip->ops.resume)
chip->ops.resume(chip);
chip->suspended = 0;
} else {
pr_err("%s called for a chip which is not in suspended state\n",
@@ -4511,10 +4541,10 @@ static int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
struct nand_chip *chip = mtd_to_nand(mtd);
if (!chip->lock_area)
if (!chip->ops.lock_area)
return -ENOTSUPP;
return chip->lock_area(chip, ofs, len);
return chip->ops.lock_area(chip, ofs, len);
}
/**
@@ -4527,10 +4557,10 @@ static int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
struct nand_chip *chip = mtd_to_nand(mtd);
if (!chip->unlock_area)
if (!chip->ops.unlock_area)
return -ENOTSUPP;
return chip->unlock_area(chip, ofs, len);
return chip->ops.unlock_area(chip, ofs, len);
}
/* Set default functions */
@@ -4743,8 +4773,6 @@ static bool find_full_id_nand(struct nand_chip *chip,
chip->options |= type->options;
chip->base.eccreq.strength = NAND_ECC_STRENGTH(type);
chip->base.eccreq.step_size = NAND_ECC_STEP(type);
chip->onfi_timing_mode_default =
type->onfi_timing_mode_default;
chip->parameters.model = kstrdup(type->name, GFP_KERNEL);
if (!chip->parameters.model)
@@ -4810,9 +4838,9 @@ static void nand_manufacturer_cleanup(struct nand_chip *chip)
}
static const char *
nand_manufacturer_name(const struct nand_manufacturer *manufacturer)
nand_manufacturer_name(const struct nand_manufacturer_desc *manufacturer_desc)
{
return manufacturer ? manufacturer->name : "Unknown";
return manufacturer_desc ? manufacturer_desc->name : "Unknown";
}
/*
@@ -4820,7 +4848,7 @@ nand_manufacturer_name(const struct nand_manufacturer *manufacturer)
*/
static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
{
const struct nand_manufacturer *manufacturer;
const struct nand_manufacturer_desc *manufacturer_desc;
struct mtd_info *mtd = nand_to_mtd(chip);
struct nand_memory_organization *memorg;
int busw, ret;
@@ -4877,8 +4905,8 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));
/* Try to identify manufacturer */
manufacturer = nand_get_manufacturer(maf_id);
chip->manufacturer.desc = manufacturer;
manufacturer_desc = nand_get_manufacturer_desc(maf_id);
chip->manufacturer.desc = manufacturer_desc;
if (!type)
type = nand_flash_ids;
@@ -4957,7 +4985,7 @@ ident_done:
*/
pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
maf_id, dev_id);
pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc),
mtd->name);
pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8,
(chip->options & NAND_BUSWIDTH_16) ? 16 : 8);
@@ -4992,7 +5020,7 @@ ident_done:
pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
maf_id, dev_id);
pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc),
chip->parameters.model);
pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
(int)(targetsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
@@ -5185,7 +5213,7 @@ static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips,
mutex_init(&chip->lock);
/* Enforce the right timings for reset/detection */
onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0);
chip->current_interface_config = nand_get_reset_interface_config();
ret = nand_dt_init(chip);
if (ret)
@@ -5972,16 +6000,16 @@ static int nand_scan_tail(struct nand_chip *chip)
if (!mtd->bitflip_threshold)
mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
/* Initialize the ->data_interface field. */
ret = nand_init_data_interface(chip);
/* Find the fastest data interface for this chip */
ret = nand_choose_interface_config(chip);
if (ret)
goto err_nanddev_cleanup;
/* Enter fastest possible mode on all dies. */
for (i = 0; i < nanddev_ntargets(&chip->base); i++) {
ret = nand_setup_data_interface(chip, i);
ret = nand_setup_interface(chip, i);
if (ret)
goto err_nanddev_cleanup;
goto err_free_interface_config;
}
/* Check, if we should skip the bad block table scan */
@@ -5991,10 +6019,12 @@ static int nand_scan_tail(struct nand_chip *chip)
/* Build bad block table */
ret = nand_create_bbt(chip);
if (ret)
goto err_nanddev_cleanup;
goto err_free_interface_config;
return 0;
err_free_interface_config:
kfree(chip->best_interface_config);
err_nanddev_cleanup:
nanddev_cleanup(&chip->base);
@@ -6088,6 +6118,9 @@ void nand_cleanup(struct nand_chip *chip)
& NAND_BBT_DYNAMICSTRUCT)
kfree(chip->badblock_pattern);
/* Free the data interface */
kfree(chip->best_interface_config);
/* Free manufacturer priv data. */
nand_manufacturer_cleanup(chip);
drivers/mtd/nand/raw/nand_bbt.c
+1 -1
View File
@@ -1226,7 +1226,7 @@ static int nand_scan_bbt(struct nand_chip *this, struct nand_bbt_descr *bd)
return -ENOMEM;
/*
* If no primary table decriptor is given, scan the device to build a
* If no primary table descriptor is given, scan the device to build a
* memory based bad block table.
*/
if (!td) {
drivers/mtd/nand/raw/nand_hynix.c
+15 -1
View File
@@ -337,7 +337,7 @@ static int hynix_mlc_1xnm_rr_init(struct nand_chip *chip,
rr->nregs = nregs;
rr->regs = hynix_1xnm_mlc_read_retry_regs;
hynix->read_retry = rr;
chip->setup_read_retry = hynix_nand_setup_read_retry;
chip->ops.setup_read_retry = hynix_nand_setup_read_retry;
chip->read_retries = nmodes;
out:
@@ -673,6 +673,15 @@ static void hynix_nand_cleanup(struct nand_chip *chip)
nand_set_manufacturer_data(chip, NULL);
}
static int
h27ucg8t2atrbc_choose_interface_config(struct nand_chip *chip,
struct nand_interface_config *iface)
{
onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4);
return nand_choose_best_sdr_timings(chip, iface, NULL);
}
static int hynix_nand_init(struct nand_chip *chip)
{
struct hynix_nand *hynix;
@@ -689,6 +698,11 @@ static int hynix_nand_init(struct nand_chip *chip)
nand_set_manufacturer_data(chip, hynix);
if (!strncmp("H27UCG8T2ATR-BC", chip->parameters.model,
sizeof("H27UCG8T2ATR-BC") - 1))
chip->ops.choose_interface_config =
h27ucg8t2atrbc_choose_interface_config;
ret = hynix_nand_rr_init(chip);
if (ret)
hynix_nand_cleanup(chip);
drivers/mtd/nand/raw/nand_ids.c
+13 -11
View File
@@ -28,8 +28,7 @@ struct nand_flash_dev nand_flash_ids[] = {
*/
{"TC58NVG0S3E 1G 3.3V 8-bit",
{ .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
2 },
SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
{"TC58NVG2S0F 4G 3.3V 8-bit",
{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
@@ -51,7 +50,10 @@ struct nand_flash_dev nand_flash_ids[] = {
{"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
NAND_ECC_INFO(40, SZ_1K), 4 },
NAND_ECC_INFO(40, SZ_1K) },
{"TH58NVG2S3HBAI4 4G 3.3V 8-bit",
{ .id = {0x98, 0xdc, 0x91, 0x15, 0x76} },
SZ_2K, SZ_512, SZ_128K, 0, 5, 128, NAND_ECC_INFO(8, SZ_512) },
LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
@@ -166,7 +168,7 @@ struct nand_flash_dev nand_flash_ids[] = {
};
/* Manufacturer IDs */
static const struct nand_manufacturer nand_manufacturers[] = {
static const struct nand_manufacturer_desc nand_manufacturer_descs[] = {
{NAND_MFR_AMD, "AMD/Spansion", &amd_nand_manuf_ops},
{NAND_MFR_ATO, "ATO"},
{NAND_MFR_EON, "Eon"},
@@ -186,20 +188,20 @@ static const struct nand_manufacturer nand_manufacturers[] = {
};
/**
* nand_get_manufacturer - Get manufacturer information from the manufacturer
* ID
* nand_get_manufacturer_desc - Get manufacturer information from the
* manufacturer ID
* @id: manufacturer ID
*
* Returns a pointer a nand_manufacturer object if the manufacturer is defined
* Returns a nand_manufacturer_desc object if the manufacturer is defined
* in the NAND manufacturers database, NULL otherwise.
*/
const struct nand_manufacturer *nand_get_manufacturer(u8 id)
const struct nand_manufacturer_desc *nand_get_manufacturer_desc(u8 id)
{
int i;
for (i = 0; i < ARRAY_SIZE(nand_manufacturers); i++)
if (nand_manufacturers[i].id == id)
return &nand_manufacturers[i];
for (i = 0; i < ARRAY_SIZE(nand_manufacturer_descs); i++)
if (nand_manufacturer_descs[i].id == id)
return &nand_manufacturer_descs[i];
return NULL;
}
drivers/mtd/nand/raw/nand_legacy.c
+5 -2
View File
@@ -354,6 +354,9 @@ static void nand_command(struct nand_chip *chip, unsigned int command,
static void nand_ccs_delay(struct nand_chip *chip)
{
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(nand_get_interface_config(chip));
/*
* The controller already takes care of waiting for tCCS when the RNDIN
* or RNDOUT command is sent, return directly.
@@ -365,8 +368,8 @@ static void nand_ccs_delay(struct nand_chip *chip)
* Wait tCCS_min if it is correctly defined, otherwise wait 500ns
* (which should be safe for all NANDs).
*/
if (nand_has_setup_data_iface(chip))
ndelay(chip->data_interface.timings.sdr.tCCS_min / 1000);
if (nand_controller_can_setup_interface(chip))
ndelay(sdr->tCCS_min / 1000);
else
ndelay(500);
}
drivers/mtd/nand/raw/nand_macronix.c
+5 -5
View File
@@ -130,7 +130,7 @@ static void macronix_nand_onfi_init(struct nand_chip *chip)
return;
chip->read_retries = MACRONIX_NUM_READ_RETRY_MODES;
chip->setup_read_retry = macronix_nand_setup_read_retry;
chip->ops.setup_read_retry = macronix_nand_setup_read_retry;
if (p->supports_set_get_features) {
bitmap_set(p->set_feature_list,
@@ -242,8 +242,8 @@ static void macronix_nand_block_protection_support(struct nand_chip *chip)
bitmap_set(chip->parameters.set_feature_list,
ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
chip->lock_area = mxic_nand_lock;
chip->unlock_area = mxic_nand_unlock;
chip->ops.lock_area = mxic_nand_lock;
chip->ops.unlock_area = mxic_nand_unlock;
}
static int nand_power_down_op(struct nand_chip *chip)
@@ -312,8 +312,8 @@ static void macronix_nand_deep_power_down_support(struct nand_chip *chip)
if (i < 0)
return;
chip->suspend = mxic_nand_suspend;
chip->resume = mxic_nand_resume;
chip->ops.suspend = mxic_nand_suspend;
chip->ops.resume = mxic_nand_resume;
}
static int macronix_nand_init(struct nand_chip *chip)
drivers/mtd/nand/raw/nand_micron.c
+1 -1
View File
@@ -84,7 +84,7 @@ static int micron_nand_onfi_init(struct nand_chip *chip)
struct nand_onfi_vendor_micron *micron = (void *)p->onfi->vendor;
chip->read_retries = micron->read_retry_options;
chip->setup_read_retry = micron_nand_setup_read_retry;
chip->ops.setup_read_retry = micron_nand_setup_read_retry;
}
if (p->supports_set_get_features) {
drivers/mtd/nand/raw/nand_timings.c
+89 -31
View File
@@ -12,7 +12,14 @@
#define ONFI_DYN_TIMING_MAX U16_MAX
static const struct nand_data_interface onfi_sdr_timings[] = {
/*
* For non-ONFI chips we use the highest possible value for tPROG and tBERS.
* tR and tCCS will take the default values precised in the ONFI specification
* for timing mode 0, respectively 200us and 500ns.
*
* These four values are tweaked to be more accurate in the case of ONFI chips.
*/
static const struct nand_interface_config onfi_sdr_timings[] = {
/* Mode 0 */
{
.type = NAND_SDR_IFACE,
@@ -20,6 +27,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = {
.timings.sdr = {
.tCCS_min = 500000,
.tR_max = 200000000,
.tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
.tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
.tADL_min = 400000,
.tALH_min = 20000,
.tALS_min = 50000,
@@ -63,6 +72,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = {
.timings.sdr = {
.tCCS_min = 500000,
.tR_max = 200000000,
.tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
.tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
.tADL_min = 400000,
.tALH_min = 10000,
.tALS_min = 25000,
@@ -106,6 +117,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = {
.timings.sdr = {
.tCCS_min = 500000,
.tR_max = 200000000,
.tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
.tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
.tADL_min = 400000,
.tALH_min = 10000,
.tALS_min = 15000,
@@ -149,6 +162,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = {
.timings.sdr = {
.tCCS_min = 500000,
.tR_max = 200000000,
.tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
.tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
.tADL_min = 400000,
.tALH_min = 5000,
.tALS_min = 10000,
@@ -192,6 +207,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = {
.timings.sdr = {
.tCCS_min = 500000,
.tR_max = 200000000,
.tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
.tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
.tADL_min = 400000,
.tALH_min = 5000,
.tALS_min = 10000,
@@ -235,6 +252,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = {
.timings.sdr = {
.tCCS_min = 500000,
.tR_max = 200000000,
.tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
.tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX,
.tADL_min = 400000,
.tALH_min = 5000,
.tALS_min = 10000,
@@ -273,23 +292,79 @@ static const struct nand_data_interface onfi_sdr_timings[] = {
},
};
/**
* onfi_fill_data_interface - [NAND Interface] Initialize a data interface from
* given ONFI mode
* @mode: The ONFI timing mode
*/
int onfi_fill_data_interface(struct nand_chip *chip,
enum nand_data_interface_type type,
int timing_mode)
/* All NAND chips share the same reset data interface: SDR mode 0 */
const struct nand_interface_config *nand_get_reset_interface_config(void)
{
return &onfi_sdr_timings[0];
}
/**
* onfi_find_closest_sdr_mode - Derive the closest ONFI SDR timing mode given a
* set of timings
* @spec_timings: the timings to challenge
*/
unsigned int
onfi_find_closest_sdr_mode(const struct nand_sdr_timings *spec_timings)
{
const struct nand_sdr_timings *onfi_timings;
int mode;
for (mode = ARRAY_SIZE(onfi_sdr_timings) - 1; mode > 0; mode--) {
onfi_timings = &onfi_sdr_timings[mode].timings.sdr;
if (spec_timings->tCCS_min <= onfi_timings->tCCS_min &&
spec_timings->tADL_min <= onfi_timings->tADL_min &&
spec_timings->tALH_min <= onfi_timings->tALH_min &&
spec_timings->tALS_min <= onfi_timings->tALS_min &&
spec_timings->tAR_min <= onfi_timings->tAR_min &&
spec_timings->tCEH_min <= onfi_timings->tCEH_min &&
spec_timings->tCH_min <= onfi_timings->tCH_min &&
spec_timings->tCLH_min <= onfi_timings->tCLH_min &&
spec_timings->tCLR_min <= onfi_timings->tCLR_min &&
spec_timings->tCLS_min <= onfi_timings->tCLS_min &&
spec_timings->tCOH_min <= onfi_timings->tCOH_min &&
spec_timings->tCS_min <= onfi_timings->tCS_min &&
spec_timings->tDH_min <= onfi_timings->tDH_min &&
spec_timings->tDS_min <= onfi_timings->tDS_min &&
spec_timings->tIR_min <= onfi_timings->tIR_min &&
spec_timings->tRC_min <= onfi_timings->tRC_min &&
spec_timings->tREH_min <= onfi_timings->tREH_min &&
spec_timings->tRHOH_min <= onfi_timings->tRHOH_min &&
spec_timings->tRHW_min <= onfi_timings->tRHW_min &&
spec_timings->tRLOH_min <= onfi_timings->tRLOH_min &&
spec_timings->tRP_min <= onfi_timings->tRP_min &&
spec_timings->tRR_min <= onfi_timings->tRR_min &&
spec_timings->tWC_min <= onfi_timings->tWC_min &&
spec_timings->tWH_min <= onfi_timings->tWH_min &&
spec_timings->tWHR_min <= onfi_timings->tWHR_min &&
spec_timings->tWP_min <= onfi_timings->tWP_min &&
spec_timings->tWW_min <= onfi_timings->tWW_min)
return mode;
}
return 0;
}
/**
* onfi_fill_interface_config - Initialize an interface config from a given
* ONFI mode
* @chip: The NAND chip
* @iface: The interface configuration to fill
* @type: The interface type
* @timing_mode: The ONFI timing mode
*/
void onfi_fill_interface_config(struct nand_chip *chip,
struct nand_interface_config *iface,
enum nand_interface_type type,
unsigned int timing_mode)
{
struct nand_data_interface *iface = &chip->data_interface;
struct onfi_params *onfi = chip->parameters.onfi;
if (type != NAND_SDR_IFACE)
return -EINVAL;
if (WARN_ON(type != NAND_SDR_IFACE))
return;
if (timing_mode < 0 || timing_mode >= ARRAY_SIZE(onfi_sdr_timings))
return -EINVAL;
if (WARN_ON(timing_mode >= ARRAY_SIZE(onfi_sdr_timings)))
return;
*iface = onfi_sdr_timings[timing_mode];
@@ -308,22 +383,5 @@ int onfi_fill_data_interface(struct nand_chip *chip,
/* nanoseconds -> picoseconds */
timings->tCCS_min = 1000UL * onfi->tCCS;
} else {
struct nand_sdr_timings *timings = &iface->timings.sdr;
/*
* For non-ONFI chips we use the highest possible value for
* tPROG and tBERS. tR and tCCS will take the default values
* precised in the ONFI specification for timing mode 0,
* respectively 200us and 500ns.
*/
/* microseconds -> picoseconds */
timings->tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX;
timings->tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX;
timings->tR_max = 200000000;
timings->tCCS_min = 500000;
}
return 0;
}
drivers/mtd/nand/raw/nand_toshiba.c
+70 -2
View File
@@ -33,7 +33,7 @@ static int toshiba_nand_benand_read_eccstatus_op(struct nand_chip *chip,
if (nand_has_exec_op(chip)) {
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&chip->data_interface);
nand_get_sdr_timings(nand_get_interface_config(chip));
struct nand_op_instr instrs[] = {
NAND_OP_CMD(TOSHIBA_NAND_CMD_ECC_STATUS_READ,
PSEC_TO_NSEC(sdr->tADL_min)),
@@ -194,17 +194,79 @@ static void toshiba_nand_decode_id(struct nand_chip *chip)
}
}
static int
tc58teg5dclta00_choose_interface_config(struct nand_chip *chip,
struct nand_interface_config *iface)
{
onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 5);
return nand_choose_best_sdr_timings(chip, iface, NULL);
}
static int
tc58nvg0s3e_choose_interface_config(struct nand_chip *chip,
struct nand_interface_config *iface)
{
onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 2);
return nand_choose_best_sdr_timings(chip, iface, NULL);
}
static int
th58nvg2s3hbai4_choose_interface_config(struct nand_chip *chip,
struct nand_interface_config *iface)
{
struct nand_sdr_timings *sdr = &iface->timings.sdr;
/* Start with timings from the closest timing mode, mode 4. */
onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4);
/* Patch timings that differ from mode 4. */
sdr->tALS_min = 12000;
sdr->tCHZ_max = 20000;
sdr->tCLS_min = 12000;
sdr->tCOH_min = 0;
sdr->tDS_min = 12000;
sdr->tRHOH_min = 25000;
sdr->tRHW_min = 30000;
sdr->tRHZ_max = 60000;
sdr->tWHR_min = 60000;
/* Patch timings not part of onfi timing mode. */
sdr->tPROG_max = 700000000;
sdr->tBERS_max = 5000000000;
return nand_choose_best_sdr_timings(chip, iface, sdr);
}
static int tc58teg5dclta00_init(struct nand_chip *chip)
{
struct mtd_info *mtd = nand_to_mtd(chip);
chip->onfi_timing_mode_default = 5;
chip->ops.choose_interface_config =
&tc58teg5dclta00_choose_interface_config;
chip->options |= NAND_NEED_SCRAMBLING;
mtd_set_pairing_scheme(mtd, &dist3_pairing_scheme);
return 0;
}
static int tc58nvg0s3e_init(struct nand_chip *chip)
{
chip->ops.choose_interface_config =
&tc58nvg0s3e_choose_interface_config;
return 0;
}
static int th58nvg2s3hbai4_init(struct nand_chip *chip)
{
chip->ops.choose_interface_config =
&th58nvg2s3hbai4_choose_interface_config;
return 0;
}
static int toshiba_nand_init(struct nand_chip *chip)
{
if (nand_is_slc(chip))
@@ -217,6 +279,12 @@ static int toshiba_nand_init(struct nand_chip *chip)
if (!strcmp("TC58TEG5DCLTA00", chip->parameters.model))
tc58teg5dclta00_init(chip);
if (!strncmp("TC58NVG0S3E", chip->parameters.model,
sizeof("TC58NVG0S3E") - 1))
tc58nvg0s3e_init(chip);
if (!strncmp("TH58NVG2S3HBAI4", chip->parameters.model,
sizeof("TH58NVG2S3HBAI4") - 1))
th58nvg2s3hbai4_init(chip);
return 0;
}
drivers/mtd/nand/raw/omap_elm.c
+1 -1
View File
@@ -2,7 +2,7 @@
/*
* Error Location Module
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
#define DRIVER_NAME "omap-elm"
drivers/mtd/nand/raw/qcom_nandc.c
+16 -2
View File
@@ -459,11 +459,13 @@ struct qcom_nand_host {
* among different NAND controllers.
* @ecc_modes - ecc mode for NAND
* @is_bam - whether NAND controller is using BAM
* @is_qpic - whether NAND CTRL is part of qpic IP
* @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
*/
struct qcom_nandc_props {
u32 ecc_modes;
bool is_bam;
bool is_qpic;
u32 dev_cmd_reg_start;
};
@@ -2774,14 +2776,24 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
u32 nand_ctrl;
/* kill onenand */
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
if (!nandc->props->is_qpic)
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
NAND_DEV_CMD_VLD_VAL);
/* enable ADM or BAM DMA */
if (nandc->props->is_bam) {
nand_ctrl = nandc_read(nandc, NAND_CTRL);
nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
/*
*NAND_CTRL is an operational registers, and CPU
* access to operational registers are read only
* in BAM mode. So update the NAND_CTRL register
* only if it is not in BAM mode. In most cases BAM
* mode will be enabled in bootloader
*/
if (!(nand_ctrl & BAM_MODE_EN))
nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
} else {
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
}
@@ -3035,12 +3047,14 @@ static const struct qcom_nandc_props ipq806x_nandc_props = {
static const struct qcom_nandc_props ipq4019_nandc_props = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
.is_qpic = true,
.dev_cmd_reg_start = 0x0,
};
static const struct qcom_nandc_props ipq8074_nandc_props = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
.is_qpic = true,
.dev_cmd_reg_start = 0x7000,
};
drivers/mtd/nand/raw/s3c2410.c
+3 -3
View File
@@ -808,8 +808,8 @@ static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
return -ENODEV;
}
static int s3c2410_nand_setup_data_interface(struct nand_chip *chip, int csline,
const struct nand_data_interface *conf)
static int s3c2410_nand_setup_interface(struct nand_chip *chip, int csline,
const struct nand_interface_config *conf)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
@@ -999,7 +999,7 @@ static int s3c2410_nand_attach_chip(struct nand_chip *chip)
static const struct nand_controller_ops s3c24xx_nand_controller_ops = {
.attach_chip = s3c2410_nand_attach_chip,
.setup_data_interface = s3c2410_nand_setup_data_interface,
.setup_interface = s3c2410_nand_setup_interface,
};
static const struct of_device_id s3c24xx_nand_dt_ids[] = {
drivers/mtd/nand/raw/stm32_fmc2_nand.c
+165 -154
View File
@@ -11,10 +11,13 @@
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/mtd/rawnand.h>
#include <linux/of_address.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
/* Bad block marker length */
@@ -242,7 +245,8 @@ struct stm32_fmc2_nfc {
struct nand_controller base;
struct stm32_fmc2_nand nand;
struct device *dev;
void __iomem *io_base;
struct device *cdev;
struct regmap *regmap;
void __iomem *data_base[FMC2_MAX_CE];
void __iomem *cmd_base[FMC2_MAX_CE];
void __iomem *addr_base[FMC2_MAX_CE];
@@ -277,40 +281,37 @@ static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip)
struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
struct stm32_fmc2_timings *timings = &nand->timings;
u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR);
u32 pmem, patt;
/* Set tclr/tar timings */
pcr &= ~FMC2_PCR_TCLR;
pcr |= FIELD_PREP(FMC2_PCR_TCLR, timings->tclr);
pcr &= ~FMC2_PCR_TAR;
pcr |= FIELD_PREP(FMC2_PCR_TAR, timings->tar);
regmap_update_bits(nfc->regmap, FMC2_PCR,
FMC2_PCR_TCLR | FMC2_PCR_TAR,
FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) |
FIELD_PREP(FMC2_PCR_TAR, timings->tar));
/* Set tset/twait/thold/thiz timings in common bank */
pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
regmap_write(nfc->regmap, FMC2_PMEM, pmem);
/* Set tset/twait/thold/thiz timings in attribut bank */
patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
writel_relaxed(pcr, nfc->io_base + FMC2_PCR);
writel_relaxed(pmem, nfc->io_base + FMC2_PMEM);
writel_relaxed(patt, nfc->io_base + FMC2_PATT);
regmap_write(nfc->regmap, FMC2_PATT, patt);
}
static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
{
struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR);
u32 pcr = 0, pcr_mask;
/* Configure ECC algorithm (default configuration is Hamming) */
pcr &= ~FMC2_PCR_ECCALG;
pcr &= ~FMC2_PCR_BCHECC;
pcr_mask = FMC2_PCR_ECCALG;
pcr_mask |= FMC2_PCR_BCHECC;
if (chip->ecc.strength == FMC2_ECC_BCH8) {
pcr |= FMC2_PCR_ECCALG;
pcr |= FMC2_PCR_BCHECC;
@@ -319,15 +320,15 @@ static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
}
/* Set buswidth */
pcr &= ~FMC2_PCR_PWID;
pcr_mask |= FMC2_PCR_PWID;
if (chip->options & NAND_BUSWIDTH_16)
pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
/* Set ECC sector size */
pcr &= ~FMC2_PCR_ECCSS;
pcr_mask |= FMC2_PCR_ECCSS;
pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
writel_relaxed(pcr, nfc->io_base + FMC2_PCR);
regmap_update_bits(nfc->regmap, FMC2_PCR, pcr_mask, pcr);
}
static int stm32_fmc2_nfc_select_chip(struct nand_chip *chip, int chipnr)
@@ -393,81 +394,63 @@ static int stm32_fmc2_nfc_select_chip(struct nand_chip *chip, int chipnr)
static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc, bool set)
{
u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR);
u32 pcr;
pcr &= ~FMC2_PCR_PWID;
if (set)
pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
writel_relaxed(pcr, nfc->io_base + FMC2_PCR);
pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) :
FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8);
regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_PWID, pcr);
}
static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
{
u32 pcr = readl(nfc->io_base + FMC2_PCR);
pcr &= ~FMC2_PCR_ECCEN;
if (enable)
pcr |= FMC2_PCR_ECCEN;
writel(pcr, nfc->io_base + FMC2_PCR);
regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_ECCEN,
enable ? FMC2_PCR_ECCEN : 0);
}
static inline void stm32_fmc2_nfc_enable_seq_irq(struct stm32_fmc2_nfc *nfc)
static void stm32_fmc2_nfc_enable_seq_irq(struct stm32_fmc2_nfc *nfc)
{
u32 csqier = readl_relaxed(nfc->io_base + FMC2_CSQIER);
csqier |= FMC2_CSQIER_TCIE;
nfc->irq_state = FMC2_IRQ_SEQ;
writel_relaxed(csqier, nfc->io_base + FMC2_CSQIER);
regmap_update_bits(nfc->regmap, FMC2_CSQIER,
FMC2_CSQIER_TCIE, FMC2_CSQIER_TCIE);
}
static inline void stm32_fmc2_nfc_disable_seq_irq(struct stm32_fmc2_nfc *nfc)
static void stm32_fmc2_nfc_disable_seq_irq(struct stm32_fmc2_nfc *nfc)
{
u32 csqier = readl_relaxed(nfc->io_base + FMC2_CSQIER);
csqier &= ~FMC2_CSQIER_TCIE;
writel_relaxed(csqier, nfc->io_base + FMC2_CSQIER);
regmap_update_bits(nfc->regmap, FMC2_CSQIER, FMC2_CSQIER_TCIE, 0);
nfc->irq_state = FMC2_IRQ_UNKNOWN;
}
static inline void stm32_fmc2_nfc_clear_seq_irq(struct stm32_fmc2_nfc *nfc)
static void stm32_fmc2_nfc_clear_seq_irq(struct stm32_fmc2_nfc *nfc)
{
writel_relaxed(FMC2_CSQICR_CLEAR_IRQ, nfc->io_base + FMC2_CSQICR);
regmap_write(nfc->regmap, FMC2_CSQICR, FMC2_CSQICR_CLEAR_IRQ);
}
static inline void stm32_fmc2_nfc_enable_bch_irq(struct stm32_fmc2_nfc *nfc,
int mode)
static void stm32_fmc2_nfc_enable_bch_irq(struct stm32_fmc2_nfc *nfc, int mode)
{
u32 bchier = readl_relaxed(nfc->io_base + FMC2_BCHIER);
if (mode == NAND_ECC_WRITE)
bchier |= FMC2_BCHIER_EPBRIE;
else
bchier |= FMC2_BCHIER_DERIE;
nfc->irq_state = FMC2_IRQ_BCH;
writel_relaxed(bchier, nfc->io_base + FMC2_BCHIER);
if (mode == NAND_ECC_WRITE)
regmap_update_bits(nfc->regmap, FMC2_BCHIER,
FMC2_BCHIER_EPBRIE, FMC2_BCHIER_EPBRIE);
else
regmap_update_bits(nfc->regmap, FMC2_BCHIER,
FMC2_BCHIER_DERIE, FMC2_BCHIER_DERIE);
}
static inline void stm32_fmc2_nfc_disable_bch_irq(struct stm32_fmc2_nfc *nfc)
static void stm32_fmc2_nfc_disable_bch_irq(struct stm32_fmc2_nfc *nfc)
{
u32 bchier = readl_relaxed(nfc->io_base + FMC2_BCHIER);
bchier &= ~FMC2_BCHIER_DERIE;
bchier &= ~FMC2_BCHIER_EPBRIE;
writel_relaxed(bchier, nfc->io_base + FMC2_BCHIER);
regmap_update_bits(nfc->regmap, FMC2_BCHIER,
FMC2_BCHIER_DERIE | FMC2_BCHIER_EPBRIE, 0);
nfc->irq_state = FMC2_IRQ_UNKNOWN;
}
static inline void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
{
writel_relaxed(FMC2_BCHICR_CLEAR_IRQ, nfc->io_base + FMC2_BCHICR);
regmap_write(nfc->regmap, FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ);
}
/*
@@ -481,13 +464,8 @@ static void stm32_fmc2_nfc_hwctl(struct nand_chip *chip, int mode)
stm32_fmc2_nfc_set_ecc(nfc, false);
if (chip->ecc.strength != FMC2_ECC_HAM) {
u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR);
if (mode == NAND_ECC_WRITE)
pcr |= FMC2_PCR_WEN;
else
pcr &= ~FMC2_PCR_WEN;
writel_relaxed(pcr, nfc->io_base + FMC2_PCR);
regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0);
reinit_completion(&nfc->complete);
stm32_fmc2_nfc_clear_bch_irq(nfc);
@@ -502,7 +480,7 @@ static void stm32_fmc2_nfc_hwctl(struct nand_chip *chip, int mode)
* ECC is 3 bytes for 512 bytes of data (supports error correction up to
* max of 1-bit)
*/
static inline void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc)
static void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc)
{
ecc[0] = ecc_sta;
ecc[1] = ecc_sta >> 8;
@@ -516,15 +494,15 @@ static int stm32_fmc2_nfc_ham_calculate(struct nand_chip *chip, const u8 *data,
u32 sr, heccr;
int ret;
ret = readl_relaxed_poll_timeout(nfc->io_base + FMC2_SR,
sr, sr & FMC2_SR_NWRF, 1,
1000 * FMC2_TIMEOUT_MS);
ret = regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
sr & FMC2_SR_NWRF, 1,
1000 * FMC2_TIMEOUT_MS);
if (ret) {
dev_err(nfc->dev, "ham timeout\n");
return ret;
}
heccr = readl_relaxed(nfc->io_base + FMC2_HECCR);
regmap_read(nfc->regmap, FMC2_HECCR, &heccr);
stm32_fmc2_nfc_ham_set_ecc(heccr, ecc);
stm32_fmc2_nfc_set_ecc(nfc, false);
@@ -603,13 +581,13 @@ static int stm32_fmc2_nfc_bch_calculate(struct nand_chip *chip, const u8 *data,
}
/* Read parity bits */
bchpbr = readl_relaxed(nfc->io_base + FMC2_BCHPBR1);
regmap_read(nfc->regmap, FMC2_BCHPBR1, &bchpbr);
ecc[0] = bchpbr;
ecc[1] = bchpbr >> 8;
ecc[2] = bchpbr >> 16;
ecc[3] = bchpbr >> 24;
bchpbr = readl_relaxed(nfc->io_base + FMC2_BCHPBR2);
regmap_read(nfc->regmap, FMC2_BCHPBR2, &bchpbr);
ecc[4] = bchpbr;
ecc[5] = bchpbr >> 8;
ecc[6] = bchpbr >> 16;
@@ -617,13 +595,13 @@ static int stm32_fmc2_nfc_bch_calculate(struct nand_chip *chip, const u8 *data,
if (chip->ecc.strength == FMC2_ECC_BCH8) {
ecc[7] = bchpbr >> 24;
bchpbr = readl_relaxed(nfc->io_base + FMC2_BCHPBR3);
regmap_read(nfc->regmap, FMC2_BCHPBR3, &bchpbr);
ecc[8] = bchpbr;
ecc[9] = bchpbr >> 8;
ecc[10] = bchpbr >> 16;
ecc[11] = bchpbr >> 24;
bchpbr = readl_relaxed(nfc->io_base + FMC2_BCHPBR4);
regmap_read(nfc->regmap, FMC2_BCHPBR4, &bchpbr);
ecc[12] = bchpbr;
}
@@ -685,11 +663,7 @@ static int stm32_fmc2_nfc_bch_correct(struct nand_chip *chip, u8 *dat,
return -ETIMEDOUT;
}
ecc_sta[0] = readl_relaxed(nfc->io_base + FMC2_BCHDSR0);
ecc_sta[1] = readl_relaxed(nfc->io_base + FMC2_BCHDSR1);
ecc_sta[2] = readl_relaxed(nfc->io_base + FMC2_BCHDSR2);
ecc_sta[3] = readl_relaxed(nfc->io_base + FMC2_BCHDSR3);
ecc_sta[4] = readl_relaxed(nfc->io_base + FMC2_BCHDSR4);
regmap_bulk_read(nfc->regmap, FMC2_BCHDSR0, ecc_sta, 5);
stm32_fmc2_nfc_set_ecc(nfc, false);
@@ -764,30 +738,29 @@ static void stm32_fmc2_nfc_rw_page_init(struct nand_chip *chip, int page,
{
struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
struct mtd_info *mtd = nand_to_mtd(chip);
u32 csqcfgr1, csqcfgr2, csqcfgr3;
u32 csqar1, csqar2;
u32 ecc_offset = mtd->writesize + FMC2_BBM_LEN;
u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR);
/*
* cfg[0] => csqcfgr1, cfg[1] => csqcfgr2, cfg[2] => csqcfgr3
* cfg[3] => csqar1, cfg[4] => csqar2
*/
u32 cfg[5];
if (write_data)
pcr |= FMC2_PCR_WEN;
else
pcr &= ~FMC2_PCR_WEN;
writel_relaxed(pcr, nfc->io_base + FMC2_PCR);
regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
write_data ? FMC2_PCR_WEN : 0);
/*
* - Set Program Page/Page Read command
* - Enable DMA request data
* - Set timings
*/
csqcfgr1 = FMC2_CSQCFGR1_DMADEN | FMC2_CSQCFGR1_CMD1T;
cfg[0] = FMC2_CSQCFGR1_DMADEN | FMC2_CSQCFGR1_CMD1T;
if (write_data)
csqcfgr1 |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_SEQIN);
cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_SEQIN);
else
csqcfgr1 |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_READ0) |
FMC2_CSQCFGR1_CMD2EN |
FIELD_PREP(FMC2_CSQCFGR1_CMD2, NAND_CMD_READSTART) |
FMC2_CSQCFGR1_CMD2T;
cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_READ0) |
FMC2_CSQCFGR1_CMD2EN |
FIELD_PREP(FMC2_CSQCFGR1_CMD2, NAND_CMD_READSTART) |
FMC2_CSQCFGR1_CMD2T;
/*
* - Set Random Data Input/Random Data Read command
@@ -796,30 +769,29 @@ static void stm32_fmc2_nfc_rw_page_init(struct nand_chip *chip, int page,
* - Set timings
*/
if (write_data)
csqcfgr2 = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDIN);
cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDIN);
else
csqcfgr2 = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDOUT) |
FMC2_CSQCFGR2_RCMD2EN |
FIELD_PREP(FMC2_CSQCFGR2_RCMD2,
NAND_CMD_RNDOUTSTART) |
FMC2_CSQCFGR2_RCMD1T |
FMC2_CSQCFGR2_RCMD2T;
cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDOUT) |
FMC2_CSQCFGR2_RCMD2EN |
FIELD_PREP(FMC2_CSQCFGR2_RCMD2, NAND_CMD_RNDOUTSTART) |
FMC2_CSQCFGR2_RCMD1T |
FMC2_CSQCFGR2_RCMD2T;
if (!raw) {
csqcfgr2 |= write_data ? 0 : FMC2_CSQCFGR2_DMASEN;
csqcfgr2 |= FMC2_CSQCFGR2_SQSDTEN;
cfg[1] |= write_data ? 0 : FMC2_CSQCFGR2_DMASEN;
cfg[1] |= FMC2_CSQCFGR2_SQSDTEN;
}
/*
* - Set the number of sectors to be written
* - Set timings
*/
csqcfgr3 = FIELD_PREP(FMC2_CSQCFGR3_SNBR, chip->ecc.steps - 1);
cfg[2] = FIELD_PREP(FMC2_CSQCFGR3_SNBR, chip->ecc.steps - 1);
if (write_data) {
csqcfgr3 |= FMC2_CSQCFGR3_RAC2T;
cfg[2] |= FMC2_CSQCFGR3_RAC2T;
if (chip->options & NAND_ROW_ADDR_3)
csqcfgr3 |= FMC2_CSQCFGR3_AC5T;
cfg[2] |= FMC2_CSQCFGR3_AC5T;
else
csqcfgr3 |= FMC2_CSQCFGR3_AC4T;
cfg[2] |= FMC2_CSQCFGR3_AC4T;
}
/*
@@ -827,8 +799,8 @@ static void stm32_fmc2_nfc_rw_page_init(struct nand_chip *chip, int page,
* Byte 1 and byte 2 => column, we start at 0x0
* Byte 3 and byte 4 => page
*/
csqar1 = FIELD_PREP(FMC2_CSQCAR1_ADDC3, page);
csqar1 |= FIELD_PREP(FMC2_CSQCAR1_ADDC4, page >> 8);
cfg[3] = FIELD_PREP(FMC2_CSQCAR1_ADDC3, page);
cfg[3] |= FIELD_PREP(FMC2_CSQCAR1_ADDC4, page >> 8);
/*
* - Set chip enable number
@@ -836,23 +808,19 @@ static void stm32_fmc2_nfc_rw_page_init(struct nand_chip *chip, int page,
* - Calculate the number of address cycles to be issued
* - Set byte 5 of address cycle if needed
*/
csqar2 = FIELD_PREP(FMC2_CSQCAR2_NANDCEN, nfc->cs_sel);
cfg[4] = FIELD_PREP(FMC2_CSQCAR2_NANDCEN, nfc->cs_sel);
if (chip->options & NAND_BUSWIDTH_16)
csqar2 |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset >> 1);
cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset >> 1);
else
csqar2 |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset);
cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset);
if (chip->options & NAND_ROW_ADDR_3) {
csqcfgr1 |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 5);
csqar2 |= FIELD_PREP(FMC2_CSQCAR2_ADDC5, page >> 16);
cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 5);
cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_ADDC5, page >> 16);
} else {
csqcfgr1 |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 4);
cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 4);
}
writel_relaxed(csqcfgr1, nfc->io_base + FMC2_CSQCFGR1);
writel_relaxed(csqcfgr2, nfc->io_base + FMC2_CSQCFGR2);
writel_relaxed(csqcfgr3, nfc->io_base + FMC2_CSQCFGR3);
writel_relaxed(csqar1, nfc->io_base + FMC2_CSQAR1);
writel_relaxed(csqar2, nfc->io_base + FMC2_CSQAR2);
regmap_bulk_write(nfc->regmap, FMC2_CSQCFGR1, cfg, 5);
}
static void stm32_fmc2_nfc_dma_callback(void *arg)
@@ -870,7 +838,6 @@ static int stm32_fmc2_nfc_xfer(struct nand_chip *chip, const u8 *buf,
struct dma_chan *dma_ch = nfc->dma_rx_ch;
enum dma_data_direction dma_data_dir = DMA_FROM_DEVICE;
enum dma_transfer_direction dma_transfer_dir = DMA_DEV_TO_MEM;
u32 csqcr = readl_relaxed(nfc->io_base + FMC2_CSQCR);
int eccsteps = chip->ecc.steps;
int eccsize = chip->ecc.size;
unsigned long timeout = msecs_to_jiffies(FMC2_TIMEOUT_MS);
@@ -948,8 +915,8 @@ static int stm32_fmc2_nfc_xfer(struct nand_chip *chip, const u8 *buf,
stm32_fmc2_nfc_enable_seq_irq(nfc);
/* Start the transfer */
csqcr |= FMC2_CSQCR_CSQSTART;
writel_relaxed(csqcr, nfc->io_base + FMC2_CSQCR);
regmap_update_bits(nfc->regmap, FMC2_CSQCR,
FMC2_CSQCR_CSQSTART, FMC2_CSQCR_CSQSTART);
/* Wait end of sequencer transfer */
if (!wait_for_completion_timeout(&nfc->complete, timeout)) {
@@ -1042,11 +1009,13 @@ static int stm32_fmc2_nfc_seq_write_page_raw(struct nand_chip *chip,
}
/* Get a status indicating which sectors have errors */
static inline u16 stm32_fmc2_nfc_get_mapping_status(struct stm32_fmc2_nfc *nfc)
static u16 stm32_fmc2_nfc_get_mapping_status(struct stm32_fmc2_nfc *nfc)
{
u32 csqemsr = readl_relaxed(nfc->io_base + FMC2_CSQEMSR);
u32 csqemsr;
return csqemsr & FMC2_CSQEMSR_SEM;
regmap_read(nfc->regmap, FMC2_CSQEMSR, &csqemsr);
return FIELD_GET(FMC2_CSQEMSR_SEM, csqemsr);
}
static int stm32_fmc2_nfc_seq_correct(struct nand_chip *chip, u8 *dat,
@@ -1302,22 +1271,22 @@ static int stm32_fmc2_nfc_waitrdy(struct nand_chip *chip,
u32 isr, sr;
/* Check if there is no pending requests to the NAND flash */
if (readl_relaxed_poll_timeout_atomic(nfc->io_base + FMC2_SR, sr,
sr & FMC2_SR_NWRF, 1,
1000 * FMC2_TIMEOUT_MS))
if (regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
sr & FMC2_SR_NWRF, 1,
1000 * FMC2_TIMEOUT_MS))
dev_warn(nfc->dev, "Waitrdy timeout\n");
/* Wait tWB before R/B# signal is low */
timings = nand_get_sdr_timings(&chip->data_interface);
timings = nand_get_sdr_timings(nand_get_interface_config(chip));
ndelay(PSEC_TO_NSEC(timings->tWB_max));
/* R/B# signal is low, clear high level flag */
writel_relaxed(FMC2_ICR_CIHLF, nfc->io_base + FMC2_ICR);
regmap_write(nfc->regmap, FMC2_ICR, FMC2_ICR_CIHLF);
/* Wait R/B# signal is high */
return readl_relaxed_poll_timeout_atomic(nfc->io_base + FMC2_ISR,
isr, isr & FMC2_ISR_IHLF,
5, 1000 * timeout_ms);
return regmap_read_poll_timeout(nfc->regmap, FMC2_ISR, isr,
isr & FMC2_ISR_IHLF, 5,
1000 * FMC2_TIMEOUT_MS);
}
static int stm32_fmc2_nfc_exec_op(struct nand_chip *chip,
@@ -1375,8 +1344,9 @@ static int stm32_fmc2_nfc_exec_op(struct nand_chip *chip,
static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc)
{
u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR);
u32 bcr1 = readl_relaxed(nfc->io_base + FMC2_BCR1);
u32 pcr;
regmap_read(nfc->regmap, FMC2_PCR, &pcr);
/* Set CS used to undefined */
nfc->cs_sel = -1;
@@ -1407,12 +1377,13 @@ static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc)
pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
/* Enable FMC2 controller */
bcr1 |= FMC2_BCR1_FMC2EN;
if (nfc->dev == nfc->cdev)
regmap_update_bits(nfc->regmap, FMC2_BCR1,
FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
writel_relaxed(bcr1, nfc->io_base + FMC2_BCR1);
writel_relaxed(pcr, nfc->io_base + FMC2_PCR);
writel_relaxed(FMC2_PMEM_DEFAULT, nfc->io_base + FMC2_PMEM);
writel_relaxed(FMC2_PATT_DEFAULT, nfc->io_base + FMC2_PATT);
regmap_write(nfc->regmap, FMC2_PCR, pcr);
regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT);
regmap_write(nfc->regmap, FMC2_PATT, FMC2_PATT_DEFAULT);
}
static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
@@ -1546,7 +1517,7 @@ static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
}
static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr,
const struct nand_data_interface *conf)
const struct nand_interface_config *conf)
{
const struct nand_sdr_timings *sdrt;
@@ -1570,7 +1541,7 @@ static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc)
nfc->dma_tx_ch = dma_request_chan(nfc->dev, "tx");
if (IS_ERR(nfc->dma_tx_ch)) {
ret = PTR_ERR(nfc->dma_tx_ch);
if (ret != -ENODEV)
if (ret != -ENODEV && ret != -EPROBE_DEFER)
dev_err(nfc->dev,
"failed to request tx DMA channel: %d\n", ret);
nfc->dma_tx_ch = NULL;
@@ -1580,7 +1551,7 @@ static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc)
nfc->dma_rx_ch = dma_request_chan(nfc->dev, "rx");
if (IS_ERR(nfc->dma_rx_ch)) {
ret = PTR_ERR(nfc->dma_rx_ch);
if (ret != -ENODEV)
if (ret != -ENODEV && ret != -EPROBE_DEFER)
dev_err(nfc->dev,
"failed to request rx DMA channel: %d\n", ret);
nfc->dma_rx_ch = NULL;
@@ -1590,7 +1561,7 @@ static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc)
nfc->dma_ecc_ch = dma_request_chan(nfc->dev, "ecc");
if (IS_ERR(nfc->dma_ecc_ch)) {
ret = PTR_ERR(nfc->dma_ecc_ch);
if (ret != -ENODEV)
if (ret != -ENODEV && ret != -EPROBE_DEFER)
dev_err(nfc->dev,
"failed to request ecc DMA channel: %d\n", ret);
nfc->dma_ecc_ch = NULL;
@@ -1764,7 +1735,7 @@ static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip)
static const struct nand_controller_ops stm32_fmc2_nfc_controller_ops = {
.attach_chip = stm32_fmc2_nfc_attach_chip,
.exec_op = stm32_fmc2_nfc_exec_op,
.setup_data_interface = stm32_fmc2_nfc_setup_interface,
.setup_interface = stm32_fmc2_nfc_setup_interface,
};
static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc,
@@ -1838,6 +1809,33 @@ static int stm32_fmc2_nfc_parse_dt(struct stm32_fmc2_nfc *nfc)
return ret;
}
static int stm32_fmc2_nfc_set_cdev(struct stm32_fmc2_nfc *nfc)
{
struct device *dev = nfc->dev;
bool ebi_found = false;
if (dev->parent && of_device_is_compatible(dev->parent->of_node,
"st,stm32mp1-fmc2-ebi"))
ebi_found = true;
if (of_device_is_compatible(dev->of_node, "st,stm32mp1-fmc2-nfc")) {
if (ebi_found) {
nfc->cdev = dev->parent;
return 0;
}
return -EINVAL;
}
if (ebi_found)
return -EINVAL;
nfc->cdev = dev;
return 0;
}
static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1847,7 +1845,9 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
struct resource *res;
struct mtd_info *mtd;
struct nand_chip *chip;
struct resource cres;
int chip_cs, mem_region, ret, irq;
int start_region = 0;
nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
if (!nfc)
@@ -1857,18 +1857,28 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
nand_controller_init(&nfc->base);
nfc->base.ops = &stm32_fmc2_nfc_controller_ops;
ret = stm32_fmc2_nfc_set_cdev(nfc);
if (ret)
return ret;
ret = stm32_fmc2_nfc_parse_dt(nfc);
if (ret)
return ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
nfc->io_base = devm_ioremap_resource(dev, res);
if (IS_ERR(nfc->io_base))
return PTR_ERR(nfc->io_base);
ret = of_address_to_resource(nfc->cdev->of_node, 0, &cres);
if (ret)
return ret;
nfc->io_phys_addr = res->start;
nfc->io_phys_addr = cres.start;
for (chip_cs = 0, mem_region = 1; chip_cs < FMC2_MAX_CE;
nfc->regmap = device_node_to_regmap(nfc->cdev->of_node);
if (IS_ERR(nfc->regmap))
return PTR_ERR(nfc->regmap);
if (nfc->dev == nfc->cdev)
start_region = 1;
for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE;
chip_cs++, mem_region += 3) {
if (!(nfc->cs_assigned & BIT(chip_cs)))
continue;
@@ -1906,7 +1916,7 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
init_completion(&nfc->complete);
nfc->clk = devm_clk_get(dev, NULL);
nfc->clk = devm_clk_get(nfc->cdev, NULL);
if (IS_ERR(nfc->clk))
return PTR_ERR(nfc->clk);
@@ -2047,6 +2057,7 @@ static SIMPLE_DEV_PM_OPS(stm32_fmc2_nfc_pm_ops, stm32_fmc2_nfc_suspend,
static const struct of_device_id stm32_fmc2_nfc_match[] = {
{.compatible = "st,stm32mp15-fmc2"},
{.compatible = "st,stm32mp1-fmc2-nfc"},
{}
};
MODULE_DEVICE_TABLE(of, stm32_fmc2_nfc_match);
drivers/mtd/nand/raw/sunxi_nand.c
+3 -3
View File
@@ -1376,8 +1376,8 @@ static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
#define sunxi_nand_lookup_timing(l, p, c) \
_sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
static int sunxi_nfc_setup_data_interface(struct nand_chip *nand, int csline,
const struct nand_data_interface *conf)
static int sunxi_nfc_setup_interface(struct nand_chip *nand, int csline,
const struct nand_interface_config *conf)
{
struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
@@ -1920,7 +1920,7 @@ static int sunxi_nfc_exec_op(struct nand_chip *nand,
static const struct nand_controller_ops sunxi_nand_controller_ops = {
.attach_chip = sunxi_nand_attach_chip,
.setup_data_interface = sunxi_nfc_setup_data_interface,
.setup_interface = sunxi_nfc_setup_interface,
.exec_op = sunxi_nfc_exec_op,
};
drivers/mtd/nand/raw/tango_nand.c
+91 -58
View File
@@ -113,53 +113,11 @@ struct tango_chip {
#define TIMING(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3))
static void tango_cmd_ctrl(struct nand_chip *chip, int dat, unsigned int ctrl)
{
struct tango_chip *tchip = to_tango_chip(chip);
if (ctrl & NAND_CLE)
writeb_relaxed(dat, tchip->base + PBUS_CMD);
if (ctrl & NAND_ALE)
writeb_relaxed(dat, tchip->base + PBUS_ADDR);
}
static int tango_dev_ready(struct nand_chip *chip)
{
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
return readl_relaxed(nfc->pbus_base + PBUS_CS_CTRL) & PBUS_IORDY;
}
static u8 tango_read_byte(struct nand_chip *chip)
{
struct tango_chip *tchip = to_tango_chip(chip);
return readb_relaxed(tchip->base + PBUS_DATA);
}
static void tango_read_buf(struct nand_chip *chip, u8 *buf, int len)
{
struct tango_chip *tchip = to_tango_chip(chip);
ioread8_rep(tchip->base + PBUS_DATA, buf, len);
}
static void tango_write_buf(struct nand_chip *chip, const u8 *buf, int len)
{
struct tango_chip *tchip = to_tango_chip(chip);
iowrite8_rep(tchip->base + PBUS_DATA, buf, len);
}
static void tango_select_chip(struct nand_chip *chip, int idx)
static void tango_select_target(struct nand_chip *chip, unsigned int cs)
{
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
struct tango_chip *tchip = to_tango_chip(chip);
if (idx < 0)
return; /* No "chip unselect" function */
writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1);
writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2);
writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG);
@@ -168,6 +126,69 @@ static void tango_select_chip(struct nand_chip *chip, int idx)
writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG);
}
static int tango_waitrdy(struct nand_chip *chip, unsigned int timeout_ms)
{
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
u32 status;
return readl_relaxed_poll_timeout(nfc->pbus_base + PBUS_CS_CTRL,
status, status & PBUS_IORDY, 20,
timeout_ms);
}
static int tango_exec_instr(struct nand_chip *chip,
const struct nand_op_instr *instr)
{
struct tango_chip *tchip = to_tango_chip(chip);
unsigned int i;
switch (instr->type) {
case NAND_OP_CMD_INSTR:
writeb_relaxed(instr->ctx.cmd.opcode, tchip->base + PBUS_CMD);
return 0;
case NAND_OP_ADDR_INSTR:
for (i = 0; i < instr->ctx.addr.naddrs; i++)
writeb_relaxed(instr->ctx.addr.addrs[i],
tchip->base + PBUS_ADDR);
return 0;
case NAND_OP_DATA_IN_INSTR:
ioread8_rep(tchip->base + PBUS_DATA, instr->ctx.data.buf.in,
instr->ctx.data.len);
return 0;
case NAND_OP_DATA_OUT_INSTR:
iowrite8_rep(tchip->base + PBUS_DATA, instr->ctx.data.buf.out,
instr->ctx.data.len);
return 0;
case NAND_OP_WAITRDY_INSTR:
return tango_waitrdy(chip,
instr->ctx.waitrdy.timeout_ms);
default:
break;
}
return -EINVAL;
}
static int tango_exec_op(struct nand_chip *chip,
const struct nand_operation *op,
bool check_only)
{
unsigned int i;
int ret = 0;
if (check_only)
return 0;
tango_select_target(chip, op->cs);
for (i = 0; i < op->ninstrs; i++) {
ret = tango_exec_instr(chip, &op->instrs[i]);
if (ret)
break;
}
return ret;
}
/*
* The controller does not check for bitflips in erased pages,
* therefore software must check instead.
@@ -279,6 +300,7 @@ static int tango_read_page(struct nand_chip *chip, u8 *buf,
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
int err, res, len = mtd->writesize;
tango_select_target(chip, chip->cur_cs);
if (oob_required)
chip->ecc.read_oob(chip, page);
@@ -300,22 +322,30 @@ static int tango_write_page(struct nand_chip *chip, const u8 *buf,
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
int err, status, len = mtd->writesize;
const struct nand_sdr_timings *timings;
int err, len = mtd->writesize;
u8 status;
/* Calling tango_write_oob() would send PAGEPROG twice */
if (oob_required)
return -ENOTSUPP;
tango_select_target(chip, chip->cur_cs);
writel_relaxed(0xffffffff, nfc->mem_base + METADATA);
err = do_dma(nfc, DMA_TO_DEVICE, NFC_WRITE, buf, len, page);
if (err)
return err;
status = chip->legacy.waitfunc(chip);
if (status & NAND_STATUS_FAIL)
return -EIO;
timings = nand_get_sdr_timings(nand_get_interface_config(chip));
err = tango_waitrdy(chip, PSEC_TO_MSEC(timings->tR_max));
if (err)
return err;
return 0;
err = nand_status_op(chip, &status);
if (err)
return err;
return (status & NAND_STATUS_FAIL) ? -EIO : 0;
}
static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos)
@@ -326,7 +356,9 @@ static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos)
/* skip over "len" bytes */
nand_change_read_column_op(chip, *pos, NULL, 0, false);
} else {
tango_read_buf(chip, *buf, len);
struct tango_chip *tchip = to_tango_chip(chip);
ioread8_rep(tchip->base + PBUS_DATA, *buf, len);
*buf += len;
}
}
@@ -339,7 +371,9 @@ static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos)
/* skip over "len" bytes */
nand_change_write_column_op(chip, *pos, NULL, 0, false);
} else {
tango_write_buf(chip, *buf, len);
struct tango_chip *tchip = to_tango_chip(chip);
iowrite8_rep(tchip->base + PBUS_DATA, *buf, len);
*buf += len;
}
}
@@ -420,6 +454,7 @@ static void raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob)
static int tango_read_page_raw(struct nand_chip *chip, u8 *buf,
int oob_required, int page)
{
tango_select_target(chip, chip->cur_cs);
nand_read_page_op(chip, page, 0, NULL, 0);
raw_read(chip, buf, chip->oob_poi);
return 0;
@@ -428,6 +463,7 @@ static int tango_read_page_raw(struct nand_chip *chip, u8 *buf,
static int tango_write_page_raw(struct nand_chip *chip, const u8 *buf,
int oob_required, int page)
{
tango_select_target(chip, chip->cur_cs);
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
raw_write(chip, buf, chip->oob_poi);
return nand_prog_page_end_op(chip);
@@ -435,6 +471,7 @@ static int tango_write_page_raw(struct nand_chip *chip, const u8 *buf,
static int tango_read_oob(struct nand_chip *chip, int page)
{
tango_select_target(chip, chip->cur_cs);
nand_read_page_op(chip, page, 0, NULL, 0);
raw_read(chip, NULL, chip->oob_poi);
return 0;
@@ -442,6 +479,7 @@ static int tango_read_oob(struct nand_chip *chip, int page)
static int tango_write_oob(struct nand_chip *chip, int page)
{
tango_select_target(chip, chip->cur_cs);
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
raw_write(chip, NULL, chip->oob_poi);
return nand_prog_page_end_op(chip);
@@ -477,7 +515,7 @@ static u32 to_ticks(int kHz, int ps)
}
static int tango_set_timings(struct nand_chip *chip, int csline,
const struct nand_data_interface *conf)
const struct nand_interface_config *conf)
{
const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf);
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
@@ -527,7 +565,8 @@ static int tango_attach_chip(struct nand_chip *chip)
static const struct nand_controller_ops tango_controller_ops = {
.attach_chip = tango_attach_chip,
.setup_data_interface = tango_set_timings,
.setup_interface = tango_set_timings,
.exec_op = tango_exec_op,
};
static int chip_init(struct device *dev, struct device_node *np)
@@ -562,12 +601,6 @@ static int chip_init(struct device *dev, struct device_node *np)
ecc = &chip->ecc;
mtd = nand_to_mtd(chip);
chip->legacy.read_byte = tango_read_byte;
chip->legacy.write_buf = tango_write_buf;
chip->legacy.read_buf = tango_read_buf;
chip->legacy.select_chip = tango_select_chip;
chip->legacy.cmd_ctrl = tango_cmd_ctrl;
chip->legacy.dev_ready = tango_dev_ready;
chip->options = NAND_USES_DMA |
NAND_NO_SUBPAGE_WRITE |
NAND_WAIT_TCCS;
drivers/mtd/nand/raw/tegra_nand.c
+3 -3
View File
@@ -813,8 +813,8 @@ static void tegra_nand_setup_timing(struct tegra_nand_controller *ctrl,
writel_relaxed(reg, ctrl->regs + TIMING_2);
}
static int tegra_nand_setup_data_interface(struct nand_chip *chip, int csline,
const struct nand_data_interface *conf)
static int tegra_nand_setup_interface(struct nand_chip *chip, int csline,
const struct nand_interface_config *conf)
{
struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
const struct nand_sdr_timings *timings;
@@ -1053,7 +1053,7 @@ static int tegra_nand_attach_chip(struct nand_chip *chip)
static const struct nand_controller_ops tegra_nand_controller_ops = {
.attach_chip = &tegra_nand_attach_chip,
.exec_op = tegra_nand_exec_op,
.setup_data_interface = tegra_nand_setup_data_interface,
.setup_interface = tegra_nand_setup_interface,
};
static int tegra_nand_chips_init(struct device *dev,

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