Merge tag 'renesas-clk-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add GPU and USB2 clocks and resets on Renesas RZ/V2H(P) - Add support for the Renesas RZ/V2N (R9A09G056) SoC - Add GPU clocks and resets on Renesas RZ/G3E * tag 'renesas-clk-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (22 commits) clk: renesas: r9a09g057: Add clock and reset entries for USB2 dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable() clk: renesas: rzv2h: Support static dividers without RMW clk: renesas: rzv2h: Add macro for defining static dividers clk: renesas: rzv2h: Add support for static mux clocks clk: renesas: r9a09g047: Add clock and reset entries for GE3D clk: renesas: rzv2h: Fix a typo clk: renesas: rzv2h: Add support for RZ/V2N SoC clk: renesas: rzv2h: Sort compatible list based on SoC part number dt-bindings: pinctrl: renesas: Document RZ/V2N SoC dt-bindings: clock: renesas: Document RZ/V2N SoC CPG dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert() clk: renesas: rzv2h: Improve rzv2h_ddiv_set_rate() clk: renesas: r9a09g057: Add clock and reset entries for GE3D clk: renesas: rzv2h: Rename PLL field macros for consistency clk: renesas: rzv2h: Add support for enabling PLLs ...
This commit is contained in:
Stephen Boyd
@@ -4,13 +4,13 @@
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$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
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title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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description:
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On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
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On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
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generation and control of clock signals for the IP modules, generation and
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control of resets, and control over booting, low power consumption and power
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supply domains.
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@@ -19,6 +19,7 @@ properties:
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compatible:
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enum:
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- renesas,r9a09g047-cpg # RZ/G3E
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- renesas,r9a09g056-cpg # RZ/V2N
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- renesas,r9a09g057-cpg # RZ/V2H
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reg:
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@@ -27,6 +27,7 @@ properties:
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- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
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- renesas,r9a08g045-pinctrl # RZ/G3S
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- renesas,r9a09g047-pinctrl # RZ/G3E
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- renesas,r9a09g056-pinctrl # RZ/V2N
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- renesas,r9a09g057-pinctrl # RZ/V2H(P)
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- items:
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@@ -145,6 +146,7 @@ allOf:
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contains:
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enum:
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- renesas,r9a09g047-pinctrl
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- renesas,r9a09g056-pinctrl
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- renesas,r9a09g057-pinctrl
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then:
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properties:
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@@ -25,6 +25,7 @@ properties:
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items:
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- enum:
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- renesas,r9a09g047-sys # RZ/G3E
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- renesas,r9a09g056-sys # RZ/V2N
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- renesas,r9a09g057-sys # RZ/V2H
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reg:
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@@ -551,6 +551,21 @@ properties:
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- renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
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- const: renesas,r9a09g047
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- description: RZ/V2N (R9A09G056)
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items:
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- enum:
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- renesas,rzv2n-evk # RZ/V2N EVK (RTK0EF0186C03000BJ)
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- enum:
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- renesas,r9a09g056n41 # RZ/V2N
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- renesas,r9a09g056n42 # RZ/V2N with Mali-G31 support
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- renesas,r9a09g056n43 # RZ/V2N with Mali-C55 support
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- renesas,r9a09g056n44 # RZ/V2N with Mali-G31 + Mali-C55 support
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- renesas,r9a09g056n45 # RZ/V2N with cryptographic extension support
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- renesas,r9a09g056n46 # RZ/V2N with Mali-G31 + cryptographic extension support
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- renesas,r9a09g056n47 # RZ/V2N with Mali-C55 + cryptographic extension support
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- renesas,r9a09g056n48 # RZ/V2N with Mali-G31 + Mali-C55 + cryptographic extension support
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- const: renesas,r9a09g056
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- description: RZ/V2H(P) (R9A09G057)
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items:
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- enum:
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@@ -41,6 +41,7 @@ config CLK_RENESAS
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select CLK_R9A08G045 if ARCH_R9A08G045
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select CLK_R9A09G011 if ARCH_R9A09G011
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select CLK_R9A09G047 if ARCH_R9A09G047
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select CLK_R9A09G056 if ARCH_R9A09G056
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select CLK_R9A09G057 if ARCH_R9A09G057
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select CLK_SH73A0 if ARCH_SH73A0
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@@ -199,6 +200,10 @@ config CLK_R9A09G047
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bool "RZ/G3E clock support" if COMPILE_TEST
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select CLK_RZV2H
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config CLK_R9A09G056
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bool "RZ/V2N clock support" if COMPILE_TEST
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select CLK_RZV2H
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config CLK_R9A09G057
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bool "RZ/V2H(P) clock support" if COMPILE_TEST
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select CLK_RZV2H
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@@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
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obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
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obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
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obj-$(CONFIG_CLK_R9A09G056) += r9a09g056-cpg.o
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obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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@@ -41,6 +41,7 @@ enum clk_ids {
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CLK_PLLDTY_ACPU_DIV4,
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CLK_PLLDTY_DIV16,
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CLK_PLLVDO_CRU0,
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CLK_PLLVDO_GPU,
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/* Module Clocks */
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MOD_CLK_BASE,
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@@ -79,7 +80,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
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DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
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DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
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/* Internal Core Clocks */
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@@ -96,6 +97,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
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DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
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DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
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DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
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/* Core Clocks */
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DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
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@@ -183,6 +185,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16,
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BUS_MSTOP(3, BIT(4))),
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DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
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BUS_MSTOP(3, BIT(4))),
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DEF_MOD("ge3d_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
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BUS_MSTOP(3, BIT(4))),
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DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
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BUS_MSTOP(2, BIT(15))),
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};
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@@ -213,6 +221,9 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
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DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
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DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
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DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
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DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */
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DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */
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DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */
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DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
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};
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@@ -0,0 +1,152 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/V2N CPG driver
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
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#include "rzv2h-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A09G056_GBETH_1_CLK_PTP_REF_I,
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/* External Input Clocks */
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CLK_AUDIO_EXTAL,
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CLK_RTXIN,
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CLK_QEXTAL,
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/* PLL Clocks */
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CLK_PLLCM33,
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CLK_PLLCLN,
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CLK_PLLDTY,
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CLK_PLLCA55,
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/* Internal Core Clocks */
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CLK_PLLCM33_DIV16,
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CLK_PLLCLN_DIV2,
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CLK_PLLCLN_DIV8,
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CLK_PLLDTY_ACPU,
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CLK_PLLDTY_ACPU_DIV4,
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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static const struct clk_div_table dtable_1_8[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{3, 8},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_64[] = {
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{0, 2},
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{1, 4},
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{2, 8},
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{3, 16},
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{4, 64},
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{0, 0},
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};
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static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
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DEF_INPUT("rtxin", CLK_RTXIN),
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DEF_INPUT("qextal", CLK_QEXTAL),
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/* PLL Clocks */
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DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
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/* Internal Core Clocks */
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DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
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DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
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DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
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DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
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DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
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/* Core Clocks */
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DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
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DEF_DDIV("ca55_0_coreclk0", R9A09G056_CA55_0_CORE_CLK0, CLK_PLLCA55,
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CDDIV1_DIVCTL0, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk1", R9A09G056_CA55_0_CORE_CLK1, CLK_PLLCA55,
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CDDIV1_DIVCTL1, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk2", R9A09G056_CA55_0_CORE_CLK2, CLK_PLLCA55,
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CDDIV1_DIVCTL2, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55,
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CDDIV1_DIVCTL3, dtable_1_8),
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DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
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};
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static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
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DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
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BUS_MSTOP(3, BIT(5))),
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DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
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BUS_MSTOP(3, BIT(14))),
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DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
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BUS_MSTOP(8, BIT(4))),
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};
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static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
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DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
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DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
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DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
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DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
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DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
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DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
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DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
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};
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const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {
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/* Core Clocks */
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.core_clks = r9a09g056_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a09g056_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Module Clocks */
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.mod_clks = r9a09g056_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a09g056_mod_clks),
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.num_hw_mod_clks = 25 * 16,
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/* Resets */
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.resets = r9a09g056_resets,
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.num_resets = ARRAY_SIZE(r9a09g056_resets),
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.num_mstop_bits = 192,
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};
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@@ -16,7 +16,7 @@
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A09G057_IOTOP_0_SHCLK,
|
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LAST_DT_CORE_CLK = R9A09G057_GBETH_1_CLK_PTP_REF_I,
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/* External Input Clocks */
|
||||
CLK_AUDIO_EXTAL,
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@@ -29,6 +29,7 @@ enum clk_ids {
|
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CLK_PLLDTY,
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CLK_PLLCA55,
|
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CLK_PLLVDO,
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CLK_PLLGPU,
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/* Internal Core Clocks */
|
||||
CLK_PLLCM33_DIV4,
|
||||
@@ -40,6 +41,7 @@ enum clk_ids {
|
||||
CLK_PLLDTY_ACPU,
|
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CLK_PLLDTY_ACPU_DIV2,
|
||||
CLK_PLLDTY_ACPU_DIV4,
|
||||
CLK_PLLDTY_DIV8,
|
||||
CLK_PLLDTY_DIV16,
|
||||
CLK_PLLDTY_RCPU,
|
||||
CLK_PLLDTY_RCPU_DIV4,
|
||||
@@ -47,6 +49,7 @@ enum clk_ids {
|
||||
CLK_PLLVDO_CRU1,
|
||||
CLK_PLLVDO_CRU2,
|
||||
CLK_PLLVDO_CRU3,
|
||||
CLK_PLLGPU_GEAR,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE,
|
||||
@@ -85,8 +88,9 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
||||
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
|
||||
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
|
||||
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
|
||||
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
|
||||
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
|
||||
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
|
||||
DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
|
||||
@@ -101,6 +105,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
||||
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
|
||||
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
|
||||
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
|
||||
DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
|
||||
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
|
||||
DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),
|
||||
DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
|
||||
@@ -110,6 +115,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
||||
DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
|
||||
DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
|
||||
|
||||
DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
|
||||
|
||||
/* Core Clocks */
|
||||
DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
|
||||
DEF_DDIV("ca55_0_coreclk0", R9A09G057_CA55_0_CORE_CLK0, CLK_PLLCA55,
|
||||
@@ -121,6 +128,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
||||
DEF_DDIV("ca55_0_coreclk3", R9A09G057_CA55_0_CORE_CLK3, CLK_PLLCA55,
|
||||
CDDIV1_DIVCTL3, dtable_1_8),
|
||||
DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
|
||||
DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
|
||||
DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
|
||||
};
|
||||
|
||||
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
|
||||
@@ -214,6 +223,16 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
|
||||
BUS_MSTOP(7, BIT(7))),
|
||||
DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
|
||||
BUS_MSTOP(7, BIT(8))),
|
||||
DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
|
||||
BUS_MSTOP(7, BIT(9))),
|
||||
DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
|
||||
BUS_MSTOP(7, BIT(10))),
|
||||
DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
|
||||
BUS_MSTOP(7, BIT(11))),
|
||||
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
|
||||
@@ -238,6 +257,12 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
|
||||
BUS_MSTOP(9, BIT(7))),
|
||||
DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
|
||||
BUS_MSTOP(9, BIT(7))),
|
||||
DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
|
||||
BUS_MSTOP(3, BIT(4))),
|
||||
DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
|
||||
BUS_MSTOP(3, BIT(4))),
|
||||
DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
|
||||
BUS_MSTOP(3, BIT(4))),
|
||||
};
|
||||
|
||||
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
|
||||
@@ -275,6 +300,10 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
|
||||
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
|
||||
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
|
||||
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
|
||||
DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
|
||||
DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
|
||||
DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
|
||||
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
|
||||
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
|
||||
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
|
||||
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
|
||||
@@ -287,6 +316,9 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
|
||||
DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */
|
||||
DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */
|
||||
DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */
|
||||
DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
|
||||
DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
|
||||
DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */
|
||||
};
|
||||
|
||||
const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
|
||||
|
||||
+135
-51
@@ -25,6 +25,7 @@
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/refcount.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/string_choices.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
@@ -44,10 +45,18 @@
|
||||
#define CPG_BUS_1_MSTOP (0xd00)
|
||||
#define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4)
|
||||
|
||||
#define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), (val)))
|
||||
#define MDIV(val) FIELD_GET(GENMASK(15, 6), (val))
|
||||
#define PDIV(val) FIELD_GET(GENMASK(5, 0), (val))
|
||||
#define SDIV(val) FIELD_GET(GENMASK(2, 0), (val))
|
||||
#define CPG_PLL_STBY(x) ((x))
|
||||
#define CPG_PLL_STBY_RESETB BIT(0)
|
||||
#define CPG_PLL_STBY_RESETB_WEN BIT(16)
|
||||
#define CPG_PLL_CLK1(x) ((x) + 0x004)
|
||||
#define CPG_PLL_CLK1_KDIV(x) ((s16)FIELD_GET(GENMASK(31, 16), (x)))
|
||||
#define CPG_PLL_CLK1_MDIV(x) FIELD_GET(GENMASK(15, 6), (x))
|
||||
#define CPG_PLL_CLK1_PDIV(x) FIELD_GET(GENMASK(5, 0), (x))
|
||||
#define CPG_PLL_CLK2(x) ((x) + 0x008)
|
||||
#define CPG_PLL_CLK2_SDIV(x) FIELD_GET(GENMASK(2, 0), (x))
|
||||
#define CPG_PLL_MON(x) ((x) + 0x010)
|
||||
#define CPG_PLL_MON_RESETB BIT(0)
|
||||
#define CPG_PLL_MON_LOCK BIT(4)
|
||||
|
||||
#define DDIV_DIVCTL_WEN(shift) BIT((shift) + 16)
|
||||
|
||||
@@ -94,8 +103,7 @@ struct pll_clk {
|
||||
struct rzv2h_cpg_priv *priv;
|
||||
void __iomem *base;
|
||||
struct clk_hw hw;
|
||||
unsigned int conf;
|
||||
unsigned int type;
|
||||
struct pll pll;
|
||||
};
|
||||
|
||||
#define to_pll(_hw) container_of(_hw, struct pll_clk, hw)
|
||||
@@ -110,7 +118,7 @@ struct pll_clk {
|
||||
* @on_index: register offset
|
||||
* @on_bit: ON/MON bit
|
||||
* @mon_index: monitor register offset
|
||||
* @mon_bit: montor bit
|
||||
* @mon_bit: monitor bit
|
||||
*/
|
||||
struct mod_clock {
|
||||
struct rzv2h_cpg_priv *priv;
|
||||
@@ -140,27 +148,78 @@ struct ddiv_clk {
|
||||
|
||||
#define to_ddiv_clock(_div) container_of(_div, struct ddiv_clk, div)
|
||||
|
||||
static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct pll_clk *pll_clk = to_pll(hw);
|
||||
struct rzv2h_cpg_priv *priv = pll_clk->priv;
|
||||
u32 val = readl(priv->base + CPG_PLL_MON(pll_clk->pll.offset));
|
||||
|
||||
/* Ensure both RESETB and LOCK bits are set */
|
||||
return (val & (CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK)) ==
|
||||
(CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK);
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_pll_clk_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct pll_clk *pll_clk = to_pll(hw);
|
||||
struct rzv2h_cpg_priv *priv = pll_clk->priv;
|
||||
struct pll pll = pll_clk->pll;
|
||||
u32 stby_offset;
|
||||
u32 mon_offset;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
if (rzv2h_cpg_pll_clk_is_enabled(hw))
|
||||
return 0;
|
||||
|
||||
stby_offset = CPG_PLL_STBY(pll.offset);
|
||||
mon_offset = CPG_PLL_MON(pll.offset);
|
||||
|
||||
writel(CPG_PLL_STBY_RESETB_WEN | CPG_PLL_STBY_RESETB,
|
||||
priv->base + stby_offset);
|
||||
|
||||
/*
|
||||
* Ensure PLL enters into normal mode
|
||||
*
|
||||
* Note: There is no HW information about the worst case latency.
|
||||
*
|
||||
* Since this latency might depend on external crystal or PLL rate,
|
||||
* use a "super" safe timeout value.
|
||||
*/
|
||||
ret = readl_poll_timeout_atomic(priv->base + mon_offset, val,
|
||||
(val & (CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK)) ==
|
||||
(CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK), 200, 2000);
|
||||
if (ret)
|
||||
dev_err(priv->dev, "Failed to enable PLL 0x%x/%pC\n",
|
||||
stby_offset, hw->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct pll_clk *pll_clk = to_pll(hw);
|
||||
struct rzv2h_cpg_priv *priv = pll_clk->priv;
|
||||
struct pll pll = pll_clk->pll;
|
||||
unsigned int clk1, clk2;
|
||||
u64 rate;
|
||||
|
||||
if (!PLL_CLK_ACCESS(pll_clk->conf))
|
||||
if (!pll.has_clkn)
|
||||
return 0;
|
||||
|
||||
clk1 = readl(priv->base + PLL_CLK1_OFFSET(pll_clk->conf));
|
||||
clk2 = readl(priv->base + PLL_CLK2_OFFSET(pll_clk->conf));
|
||||
clk1 = readl(priv->base + CPG_PLL_CLK1(pll.offset));
|
||||
clk2 = readl(priv->base + CPG_PLL_CLK2(pll.offset));
|
||||
|
||||
rate = mul_u64_u32_shr(parent_rate, (MDIV(clk1) << 16) + KDIV(clk1),
|
||||
16 + SDIV(clk2));
|
||||
rate = mul_u64_u32_shr(parent_rate, (CPG_PLL_CLK1_MDIV(clk1) << 16) +
|
||||
CPG_PLL_CLK1_KDIV(clk1), 16 + CPG_PLL_CLK2_SDIV(clk2));
|
||||
|
||||
return DIV_ROUND_CLOSEST_ULL(rate, PDIV(clk1));
|
||||
return DIV_ROUND_CLOSEST_ULL(rate, CPG_PLL_CLK1_PDIV(clk1));
|
||||
}
|
||||
|
||||
static const struct clk_ops rzv2h_cpg_pll_ops = {
|
||||
.is_enabled = rzv2h_cpg_pll_clk_is_enabled,
|
||||
.enable = rzv2h_cpg_pll_clk_enable,
|
||||
.recalc_rate = rzv2h_cpg_pll_clk_recalc_rate,
|
||||
};
|
||||
|
||||
@@ -193,10 +252,9 @@ rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core,
|
||||
init.num_parents = 1;
|
||||
|
||||
pll_clk->hw.init = &init;
|
||||
pll_clk->conf = core->cfg.conf;
|
||||
pll_clk->pll = core->cfg.pll;
|
||||
pll_clk->base = base;
|
||||
pll_clk->priv = priv;
|
||||
pll_clk->type = core->type;
|
||||
|
||||
ret = devm_clk_hw_register(dev, &pll_clk->hw);
|
||||
if (ret)
|
||||
@@ -241,6 +299,9 @@ static inline int rzv2h_cpg_wait_ddiv_clk_update_done(void __iomem *base, u8 mon
|
||||
u32 bitmask = BIT(mon);
|
||||
u32 val;
|
||||
|
||||
if (mon == CSDIV_NO_MON)
|
||||
return 0;
|
||||
|
||||
return readl_poll_timeout_atomic(base + CPG_CLKSTATUS0, val, !(val & bitmask), 10, 200);
|
||||
}
|
||||
|
||||
@@ -272,12 +333,6 @@ static int rzv2h_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
writel(val, divider->reg);
|
||||
|
||||
ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);
|
||||
if (ret)
|
||||
goto ddiv_timeout;
|
||||
|
||||
spin_unlock_irqrestore(divider->lock, flags);
|
||||
|
||||
return 0;
|
||||
|
||||
ddiv_timeout:
|
||||
spin_unlock_irqrestore(divider->lock, flags);
|
||||
@@ -320,7 +375,10 @@ rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core,
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = core->name;
|
||||
init.ops = &rzv2h_ddiv_clk_divider_ops;
|
||||
if (cfg_ddiv.no_rmw)
|
||||
init.ops = &clk_divider_ops;
|
||||
else
|
||||
init.ops = &rzv2h_ddiv_clk_divider_ops;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
@@ -342,6 +400,24 @@ rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core,
|
||||
return div->hw.clk;
|
||||
}
|
||||
|
||||
static struct clk * __init
|
||||
rzv2h_cpg_mux_clk_register(const struct cpg_core_clk *core,
|
||||
struct rzv2h_cpg_priv *priv)
|
||||
{
|
||||
struct smuxed mux = core->cfg.smux;
|
||||
const struct clk_hw *clk_hw;
|
||||
|
||||
clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
|
||||
core->parent_names, core->num_parents,
|
||||
core->flag, priv->base + mux.offset,
|
||||
mux.shift, mux.width,
|
||||
core->mux_flags, &priv->rmw_lock);
|
||||
if (IS_ERR(clk_hw))
|
||||
return ERR_CAST(clk_hw);
|
||||
|
||||
return clk_hw->clk;
|
||||
}
|
||||
|
||||
static struct clk
|
||||
*rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
|
||||
void *data)
|
||||
@@ -426,6 +502,9 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
|
||||
case CLK_TYPE_DDIV:
|
||||
clk = rzv2h_cpg_ddiv_clk_register(core, priv);
|
||||
break;
|
||||
case CLK_TYPE_SMUX:
|
||||
clk = rzv2h_cpg_mux_clk_register(core, priv);
|
||||
break;
|
||||
default:
|
||||
goto fail;
|
||||
}
|
||||
@@ -494,11 +573,14 @@ static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
|
||||
if (clock->mon_index >= 0) {
|
||||
offset = GET_CLK_MON_OFFSET(clock->mon_index);
|
||||
bitmask = BIT(clock->mon_bit);
|
||||
} else {
|
||||
offset = GET_CLK_ON_OFFSET(clock->on_index);
|
||||
bitmask = BIT(clock->on_bit);
|
||||
|
||||
if (!(readl(priv->base + offset) & bitmask))
|
||||
return 0;
|
||||
}
|
||||
|
||||
offset = GET_CLK_ON_OFFSET(clock->on_index);
|
||||
bitmask = BIT(clock->on_bit);
|
||||
|
||||
return readl(priv->base + offset) & bitmask;
|
||||
}
|
||||
|
||||
@@ -514,7 +596,7 @@ static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
|
||||
int error;
|
||||
|
||||
dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,
|
||||
enable ? "ON" : "OFF");
|
||||
str_on_off(enable));
|
||||
|
||||
if (enabled == enable)
|
||||
return 0;
|
||||
@@ -658,8 +740,8 @@ fail:
|
||||
mod->name, PTR_ERR(clk));
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
static int __rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id, bool assert)
|
||||
{
|
||||
struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
|
||||
@@ -667,35 +749,31 @@ static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
|
||||
u8 monbit = priv->resets[id].mon_bit;
|
||||
u32 value = mask << 16;
|
||||
|
||||
dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, reg);
|
||||
dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n",
|
||||
assert ? "assert" : "deassert", id, reg);
|
||||
|
||||
if (!assert)
|
||||
value |= mask;
|
||||
writel(value, priv->base + reg);
|
||||
|
||||
reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
|
||||
mask = BIT(monbit);
|
||||
|
||||
return readl_poll_timeout_atomic(priv->base + reg, value,
|
||||
value & mask, 10, 200);
|
||||
assert ? (value & mask) : !(value & mask),
|
||||
10, 200);
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return __rzv2h_cpg_assert(rcdev, id, true);
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
|
||||
u32 mask = BIT(priv->resets[id].reset_bit);
|
||||
u8 monbit = priv->resets[id].mon_bit;
|
||||
u32 value = (mask << 16) | mask;
|
||||
|
||||
dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, reg);
|
||||
|
||||
writel(value, priv->base + reg);
|
||||
|
||||
reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
|
||||
mask = BIT(monbit);
|
||||
|
||||
return readl_poll_timeout_atomic(priv->base + reg, value,
|
||||
!(value & mask), 10, 200);
|
||||
return __rzv2h_cpg_assert(rcdev, id, false);
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_reset(struct reset_controller_dev *rcdev,
|
||||
@@ -967,17 +1045,23 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
static const struct of_device_id rzv2h_cpg_match[] = {
|
||||
#ifdef CONFIG_CLK_R9A09G057
|
||||
{
|
||||
.compatible = "renesas,r9a09g057-cpg",
|
||||
.data = &r9a09g057_cpg_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R9A09G047
|
||||
{
|
||||
.compatible = "renesas,r9a09g047-cpg",
|
||||
.data = &r9a09g047_cpg_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R9A09G056
|
||||
{
|
||||
.compatible = "renesas,r9a09g056-cpg",
|
||||
.data = &r9a09g056_cpg_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R9A09G057
|
||||
{
|
||||
.compatible = "renesas,r9a09g057-cpg",
|
||||
.data = &r9a09g057_cpg_info,
|
||||
},
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
@@ -10,6 +10,26 @@
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
/**
|
||||
* struct pll - Structure for PLL configuration
|
||||
*
|
||||
* @offset: STBY register offset
|
||||
* @has_clkn: Flag to indicate if CLK1/2 are accessible or not
|
||||
*/
|
||||
struct pll {
|
||||
unsigned int offset:9;
|
||||
unsigned int has_clkn:1;
|
||||
};
|
||||
|
||||
#define PLL_PACK(_offset, _has_clkn) \
|
||||
((struct pll){ \
|
||||
.offset = _offset, \
|
||||
.has_clkn = _has_clkn \
|
||||
})
|
||||
|
||||
#define PLLCA55 PLL_PACK(0x60, 1)
|
||||
#define PLLGPU PLL_PACK(0x120, 1)
|
||||
|
||||
/**
|
||||
* struct ddiv - Structure for dynamic switching divider
|
||||
*
|
||||
@@ -17,14 +37,25 @@
|
||||
* @shift: position of the divider bit
|
||||
* @width: width of the divider
|
||||
* @monbit: monitor bit in CPG_CLKSTATUS0 register
|
||||
* @no_rmw: flag to indicate if the register is read-modify-write
|
||||
* (1: no RMW, 0: RMW)
|
||||
*/
|
||||
struct ddiv {
|
||||
unsigned int offset:11;
|
||||
unsigned int shift:4;
|
||||
unsigned int width:4;
|
||||
unsigned int monbit:5;
|
||||
unsigned int no_rmw:1;
|
||||
};
|
||||
|
||||
/*
|
||||
* On RZ/V2H(P), the dynamic divider clock supports up to 19 monitor bits,
|
||||
* while on RZ/G3E, it supports up to 16 monitor bits. Use the maximum value
|
||||
* `0x1f` to indicate that monitor bits are not supported for static divider
|
||||
* clocks.
|
||||
*/
|
||||
#define CSDIV_NO_MON (0x1f)
|
||||
|
||||
#define DDIV_PACK(_offset, _shift, _width, _monbit) \
|
||||
((struct ddiv){ \
|
||||
.offset = _offset, \
|
||||
@@ -33,6 +64,35 @@ struct ddiv {
|
||||
.monbit = _monbit \
|
||||
})
|
||||
|
||||
#define DDIV_PACK_NO_RMW(_offset, _shift, _width, _monbit) \
|
||||
((struct ddiv){ \
|
||||
.offset = (_offset), \
|
||||
.shift = (_shift), \
|
||||
.width = (_width), \
|
||||
.monbit = (_monbit), \
|
||||
.no_rmw = 1 \
|
||||
})
|
||||
|
||||
/**
|
||||
* struct smuxed - Structure for static muxed clocks
|
||||
*
|
||||
* @offset: register offset
|
||||
* @shift: position of the divider field
|
||||
* @width: width of the divider field
|
||||
*/
|
||||
struct smuxed {
|
||||
unsigned int offset:11;
|
||||
unsigned int shift:4;
|
||||
unsigned int width:4;
|
||||
};
|
||||
|
||||
#define SMUX_PACK(_offset, _shift, _width) \
|
||||
((struct smuxed){ \
|
||||
.offset = (_offset), \
|
||||
.shift = (_shift), \
|
||||
.width = (_width), \
|
||||
})
|
||||
|
||||
#define CPG_CDDIV0 (0x400)
|
||||
#define CPG_CDDIV1 (0x404)
|
||||
#define CPG_CDDIV3 (0x40C)
|
||||
@@ -44,6 +104,7 @@ struct ddiv {
|
||||
#define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
|
||||
#define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
|
||||
#define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
|
||||
#define CDDIV3_DIVCTL1 DDIV_PACK(CPG_CDDIV3, 4, 3, 13)
|
||||
#define CDDIV3_DIVCTL2 DDIV_PACK(CPG_CDDIV3, 8, 3, 14)
|
||||
#define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15)
|
||||
#define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16)
|
||||
@@ -74,8 +135,13 @@ struct cpg_core_clk {
|
||||
union {
|
||||
unsigned int conf;
|
||||
struct ddiv ddiv;
|
||||
struct pll pll;
|
||||
struct smuxed smux;
|
||||
} cfg;
|
||||
const struct clk_div_table *dtable;
|
||||
const char * const *parent_names;
|
||||
unsigned int num_parents;
|
||||
u8 mux_flags;
|
||||
u32 flag;
|
||||
};
|
||||
|
||||
@@ -85,20 +151,15 @@ enum clk_types {
|
||||
CLK_TYPE_FF, /* Fixed Factor Clock */
|
||||
CLK_TYPE_PLL,
|
||||
CLK_TYPE_DDIV, /* Dynamic Switching Divider */
|
||||
CLK_TYPE_SMUX, /* Static Mux */
|
||||
};
|
||||
|
||||
/* BIT(31) indicates if CLK1/2 are accessible or not */
|
||||
#define PLL_CONF(n) (BIT(31) | ((n) & ~GENMASK(31, 16)))
|
||||
#define PLL_CLK_ACCESS(n) ((n) & BIT(31) ? 1 : 0)
|
||||
#define PLL_CLK1_OFFSET(n) ((n) & ~GENMASK(31, 16))
|
||||
#define PLL_CLK2_OFFSET(n) (((n) & ~GENMASK(31, 16)) + (0x4))
|
||||
|
||||
#define DEF_TYPE(_name, _id, _type...) \
|
||||
{ .name = _name, .id = _id, .type = _type }
|
||||
#define DEF_BASE(_name, _id, _type, _parent...) \
|
||||
DEF_TYPE(_name, _id, _type, .parent = _parent)
|
||||
#define DEF_PLL(_name, _id, _parent, _conf) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.conf = _conf)
|
||||
#define DEF_PLL(_name, _id, _parent, _pll_packed) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.pll = _pll_packed)
|
||||
#define DEF_INPUT(_name, _id) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_IN)
|
||||
#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
|
||||
@@ -109,6 +170,15 @@ enum clk_types {
|
||||
.parent = _parent, \
|
||||
.dtable = _dtable, \
|
||||
.flag = CLK_DIVIDER_HIWORD_MASK)
|
||||
#define DEF_CSDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
|
||||
DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable)
|
||||
#define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \
|
||||
.cfg.smux = _smux_packed, \
|
||||
.parent_names = _parent_names, \
|
||||
.num_parents = ARRAY_SIZE(_parent_names), \
|
||||
.flag = CLK_SET_RATE_PARENT, \
|
||||
.mux_flags = CLK_MUX_HIWORD_MASK)
|
||||
|
||||
/**
|
||||
* struct rzv2h_mod_clk - Module Clocks definitions
|
||||
@@ -221,6 +291,7 @@ struct rzv2h_cpg_info {
|
||||
};
|
||||
|
||||
extern const struct rzv2h_cpg_info r9a09g047_cpg_info;
|
||||
extern const struct rzv2h_cpg_info r9a09g056_cpg_info;
|
||||
extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
|
||||
|
||||
#endif /* __RENESAS_RZV2H_CPG_H__ */
|
||||
|
||||
@@ -0,0 +1,24 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
*
|
||||
* Copyright (C) 2025 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__
|
||||
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* Core Clock list */
|
||||
#define R9A09G056_SYS_0_PCLK 0
|
||||
#define R9A09G056_CA55_0_CORE_CLK0 1
|
||||
#define R9A09G056_CA55_0_CORE_CLK1 2
|
||||
#define R9A09G056_CA55_0_CORE_CLK2 3
|
||||
#define R9A09G056_CA55_0_CORE_CLK3 4
|
||||
#define R9A09G056_CA55_0_PERIPHCLK 5
|
||||
#define R9A09G056_CM33_CLK0 6
|
||||
#define R9A09G056_CST_0_SWCLKTCK 7
|
||||
#define R9A09G056_IOTOP_0_SHCLK 8
|
||||
#define R9A09G056_USB2_0_CLK_CORE0 9
|
||||
#define R9A09G056_GBETH_0_CLK_PTP_REF_I 10
|
||||
#define R9A09G056_GBETH_1_CLK_PTP_REF_I 11
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */
|
||||
@@ -17,5 +17,9 @@
|
||||
#define R9A09G057_CM33_CLK0 6
|
||||
#define R9A09G057_CST_0_SWCLKTCK 7
|
||||
#define R9A09G057_IOTOP_0_SHCLK 8
|
||||
#define R9A09G057_USB2_0_CLK_CORE0 9
|
||||
#define R9A09G057_USB2_0_CLK_CORE1 10
|
||||
#define R9A09G057_GBETH_0_CLK_PTP_REF_I 11
|
||||
#define R9A09G057_GBETH_1_CLK_PTP_REF_I 12
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */
|
||||
|
||||
Reference in New Issue
Block a user