arm64: dts: mediatek: mt6795: Add support for display blocks and DPI/DSI
Introduce all nodes for all of the display blocks in the MediaTek Helio X10 MT6795 SoC, including the DSI PHY and DSI/DPI interfaces: those are left disabled as usage is board specific. Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230721082822.680010-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
AngeloGioacchino Del Regno
committed by
Matthias Brugger
Matthias Brugger
parent
a69e042f6b
commit
bdfae71e52
@@ -1,7 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Mars.C <mars.cheng@mediatek.com>
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* Copyright (C) 2023 Collabora Ltd.
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* Authors: Mars.C <mars.cheng@mediatek.com>
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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@@ -19,6 +21,23 @@
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ovl0 = &ovl0;
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ovl1 = &ovl1;
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rdma0 = &rdma0;
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rdma1 = &rdma1;
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rdma2 = &rdma2;
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wdma0 = &wdma0;
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wdma1 = &wdma1;
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color0 = &color0;
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color1 = &color1;
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split0 = &split0;
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split1 = &split1;
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dpi0 = &dpi0;
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dsi0 = &dsi0;
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dsi1 = &dsi1;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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@@ -434,6 +453,26 @@
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#mbox-cells = <2>;
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};
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mipi_tx0: dsi-phy@10215000 {
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compatible = "mediatek,mt8173-mipi-tx";
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reg = <0 0x10215000 0 0x1000>;
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clocks = <&clk26m>;
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clock-output-names = "mipi_tx0_pll";
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#clock-cells = <0>;
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#phy-cells = <0>;
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status = "disabled";
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};
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mipi_tx1: dsi-phy@10216000 {
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compatible = "mediatek,mt8173-mipi-tx";
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reg = <0 0x10216000 0 0x1000>;
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clocks = <&clk26m>;
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clock-output-names = "mipi_tx1_pll";
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#clock-cells = <0>;
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#phy-cells = <0>;
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status = "disabled";
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};
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gic: interrupt-controller@10221000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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@@ -690,6 +729,211 @@
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
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};
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ovl0: ovl@1400c000 {
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compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl";
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reg = <0 0x1400c000 0 0x1000>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_OVL0>;
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iommus = <&iommu M4U_PORT_DISP_OVL0>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
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};
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ovl1: ovl@1400d000 {
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compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl";
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reg = <0 0x1400d000 0 0x1000>;
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interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_OVL1>;
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iommus = <&iommu M4U_PORT_DISP_OVL1>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
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};
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rdma0: rdma@1400e000 {
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compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma";
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reg = <0 0x1400e000 0 0x1000>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_RDMA0>;
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iommus = <&iommu M4U_PORT_DISP_RDMA0>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
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};
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rdma1: rdma@1400f000 {
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compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma";
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reg = <0 0x1400f000 0 0x1000>;
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interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_RDMA1>;
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iommus = <&iommu M4U_PORT_DISP_RDMA1>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
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};
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rdma2: rdma@14010000 {
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compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma";
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reg = <0 0x14010000 0 0x1000>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_RDMA2>;
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iommus = <&iommu M4U_PORT_DISP_RDMA2>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
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};
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wdma0: wdma@14011000 {
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compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma";
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reg = <0 0x14011000 0 0x1000>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_WDMA0>;
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iommus = <&iommu M4U_PORT_DISP_WDMA0>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
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};
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wdma1: wdma@14012000 {
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compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma";
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reg = <0 0x14012000 0 0x1000>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_WDMA1>;
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iommus = <&iommu M4U_PORT_DISP_WDMA1>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
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};
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color0: color@14013000 {
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compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color";
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reg = <0 0x14013000 0 0x1000>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_COLOR0>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
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};
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color1: color@14014000 {
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compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color";
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reg = <0 0x14014000 0 0x1000>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_COLOR1>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
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};
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aal@14015000 {
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compatible = "mediatek,mt6795-disp-aal", "mediatek,mt8173-disp-aal";
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reg = <0 0x14015000 0 0x1000>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_AAL>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
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};
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gamma@14016000 {
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compatible = "mediatek,mt6795-disp-gamma", "mediatek,mt8173-disp-gamma";
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reg = <0 0x14016000 0 0x1000>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_GAMMA>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
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};
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merge@14017000 {
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compatible = "mediatek,mt6795-disp-merge", "mediatek,mt8173-disp-merge";
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reg = <0 0x14017000 0 0x1000>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_MERGE>;
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};
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split0: split@14018000 {
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compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split";
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reg = <0 0x14018000 0 0x1000>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
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};
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split1: split@14019000 {
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compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split";
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reg = <0 0x14019000 0 0x1000>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
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};
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ufoe@1401a000 {
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compatible = "mediatek,mt6795-disp-ufoe", "mediatek,mt8173-disp-ufoe";
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reg = <0 0x1401a000 0 0x1000>;
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interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_UFOE>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
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};
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dsi0: dsi@1401b000 {
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compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi";
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reg = <0 0x1401b000 0 0x1000>;
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interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
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<&mmsys CLK_MM_DSI0_DIGITAL>,
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<&mipi_tx0>;
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clock-names = "engine", "digital", "hs";
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phys = <&mipi_tx0>;
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phy-names = "dphy";
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status = "disabled";
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};
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dsi1: dsi@1401c000 {
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compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi";
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reg = <0 0x1401c000 0 0x1000>;
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interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
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<&mmsys CLK_MM_DSI1_DIGITAL>,
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<&mipi_tx1>;
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clock-names = "engine", "digital", "hs";
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phys = <&mipi_tx1>;
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phy-names = "dphy";
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status = "disabled";
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};
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dpi0: dpi@1401d000 {
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compatible = "mediatek,mt6795-dpi", "mediatek,mt8183-dpi";
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reg = <0 0x1401d000 0 0x1000>;
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interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DPI_PIXEL>,
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<&mmsys CLK_MM_DPI_ENGINE>,
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<&apmixedsys CLK_APMIXED_TVDPLL>;
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clock-names = "pixel", "engine", "pll";
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status = "disabled";
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};
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pwm0: pwm@1401e000 {
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compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm";
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reg = <0 0x1401e000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_DISP_PWM026M>, <&mmsys CLK_MM_DISP_PWM0MM>;
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clock-names = "main", "mm";
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status = "disabled";
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};
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pwm1: pwm@1401f000 {
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compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm";
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reg = <0 0x1401f000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_DISP_PWM126M>, <&mmsys CLK_MM_DISP_PWM1MM>;
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clock-names = "main", "mm";
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status = "disabled";
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};
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mutex: mutex@14020000 {
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compatible = "mediatek,mt8173-disp-mutex";
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reg = <0 0x14020000 0 0x1000>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_MUTEX_32K>;
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mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
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<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
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mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
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};
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larb0: larb@14021000 {
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compatible = "mediatek,mt6795-smi-larb";
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reg = <0 0x14021000 0 0x1000>;
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@@ -708,6 +952,13 @@
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clock-names = "apb", "smi";
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};
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od@14023000 {
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compatible = "mediatek,mt6795-disp-od", "mediatek,mt8173-disp-od";
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reg = <0 0x14023000 0 0x1000>;
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clocks = <&mmsys CLK_MM_DISP_OD>;
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mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
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};
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larb2: larb@15001000 {
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compatible = "mediatek,mt6795-smi-larb";
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reg = <0 0x15001000 0 0x1000>;
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