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Merge branch 'pci/dt-bindings'

Browse Source 
- Add qcom,pcie-ipq5332 binding (Varadarajan Narayanan)

- Convert fsl,mpc83xx-pcie binding to YAML (J. Neuschäfer)

- Add qcom i.MX8QM and i.MX8QXP/DXP optional DMA interrupt (Alexander
  Stein)

- Drop deprecated layerscape 'num-ib-windows' and 'num-ob-windows' from
  example (Krzysztof Kozlowski)

- Drop unnecessary layerscape 'status' from example (Krzysztof Kozlowski)

- Add common pci-ep-bus.yaml schema for exporting several peripherals of a
  single PCI function via devicetree (Andrea della Porta)

* pci/dt-bindings:
  dt-bindings: PCI: Add common schema for devices accessible through PCI BARs
  dt-bindings: PCI: fsl,layerscape-pcie-ep: Drop unnecessary status from example
  dt-bindings: PCI: fsl,layerscape-pcie-ep: Drop deprecated windows
  dt-bindings: PCI: fsl,imx6q-pcie: Add optional DMA interrupt
  dt-bindings: PCI: Convert fsl,mpc83xx-pcie to YAML
  dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller
This commit is contained in:
Bjorn Helgaas
2025-03-27 13:14:46 -05:00
parent a1aed6b34f 01a1e9d6a0
commit b810fec018
6 changed files with 181 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+4
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@@ -47,12 +47,16 @@ properties:
maxItems: 5
interrupts:
minItems: 1
items:
- description: builtin MSI controller.
- description: builtin DMA controller.
interrupt-names:
minItems: 1
items:
- const: msi
- const: dma
reset-gpio:
description: Should specify the GPIO for controlling the PCI bus device
Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
-3
View File
@@ -94,9 +94,6 @@ examples:
reg-names = "regs", "addr_space";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
status = "disabled";
};
};
...
Documentation/devicetree/bindings/pci/fsl,mpc8xxx-pci.yaml
+113
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@@ -0,0 +1,113 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/fsl,mpc8xxx-pci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale MPC83xx PCI/PCI-X/PCIe controllers
description:
Binding for the PCI/PCI-X/PCIe host bridges on MPC8xxx SoCs
maintainers:
- J. Neuschäfer <j.neuschaefer@gmx.net>
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:
oneOf:
- enum:
- fsl,mpc8314-pcie
- fsl,mpc8349-pci
- fsl,mpc8540-pci
- fsl,mpc8548-pcie
- fsl,mpc8641-pcie
- items:
- enum:
- fsl,mpc8308-pcie
- fsl,mpc8315-pcie
- fsl,mpc8377-pcie
- fsl,mpc8378-pcie
- const: fsl,mpc8314-pcie
- items:
- const: fsl,mpc8360-pci
- const: fsl,mpc8349-pci
- items:
- const: fsl,mpc8540-pcix
- const: fsl,mpc8540-pci
reg:
minItems: 1
items:
- description: internal registers
- description: config space access registers
clock-frequency: true
interrupts:
items:
- description: Consolidated PCI interrupt
fsl,pci-agent-force-enum:
type: boolean
description:
Typically any Freescale PCI-X bridge hardware strapped into Agent mode is
prevented from enumerating the bus. The PrPMC form-factor requires all
mezzanines to be PCI-X Agents, but one per system may still enumerate the
bus.
This property allows a PCI-X bridge to be used for bus enumeration
despite being strapped into Agent mode.
required:
- reg
- compatible
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
pcie@e0009000 {
compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
reg = <0xe0009000 0x00001000>;
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
bus-range = <0 255>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0 0 0 1 &ipic 1 IRQ_TYPE_LEVEL_LOW
0 0 0 2 &ipic 1 IRQ_TYPE_LEVEL_LOW
0 0 0 3 &ipic 1 IRQ_TYPE_LEVEL_LOW
0 0 0 4 &ipic 1 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <0>;
};
- |
pci@ef008000 {
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
reg = <0xef008000 0x1000>;
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
0x01000000 0 0x00000000 0xd0000000 0 0x01000000>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
clock-frequency = <33333333>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = </* IDSEL */
0xe000 0 0 1 &mpic 2 1
0xe000 0 0 2 &mpic 3 1>;
interrupts-extended = <&mpic 24 2>;
bus-range = <0 0>;
fsl,pci-agent-force-enum;
};
...
Documentation/devicetree/bindings/pci/fsl,pci.txt
-27
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@@ -1,27 +0,0 @@
* Bus Enumeration by Freescale PCI-X Agent
Typically any Freescale PCI-X bridge hardware strapped into Agent mode
is prevented from enumerating the bus. The PrPMC form-factor requires
all mezzanines to be PCI-X Agents, but one per system may still
enumerate the bus.
The property defined below will allow a PCI-X bridge to be used for bus
enumeration despite being strapped into Agent mode.
Required properties:
- fsl,pci-agent-force-enum : There is no value associated with this
property. The property itself is treated as a boolean.
Example:
/* PCI-X bridge known to be PrPMC Monarch */
pci0: pci@ef008000 {
fsl,pci-agent-force-enum;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
...
...
};
Documentation/devicetree/bindings/pci/pci-ep-bus.yaml
+58
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@@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/pci-ep-bus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common Properties for PCI MFD EP with Peripherals Addressable from BARs
maintainers:
- A. della Porta <andrea.porta@suse.com>
description:
Define a generic node representing a PCI endpoint which contains several sub-
peripherals. The peripherals can be accessed through one or more BARs.
This common schema is intended to be referenced from device tree bindings and
does not represent a device tree binding by itself.
properties:
'#address-cells':
const: 3
'#size-cells':
const: 2
ranges:
minItems: 1
maxItems: 6
items:
maxItems: 8
additionalItems: true
items:
- maximum: 5 # The BAR number
- const: 0
- const: 0
patternProperties:
'^pci-ep-bus@[0-5]$':
type: object
description:
One node for each BAR used by peripherals contained in the PCI endpoint.
Each node represents a bus on which peripherals are connected.
This allows for some segmentation, e.g., one peripheral is accessible
through BAR0 and another through BAR1, and you don't want the two
peripherals to be able to act on the other BAR. Alternatively, when
different peripherals need to share BARs, you can define only one node
and use a 'ranges' property to map all the used BARs.
additionalProperties: true
properties:
compatible:
const: simple-bus
required:
- compatible
additionalProperties: true
...
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+6 -2
View File
@@ -33,6 +33,7 @@ properties:
- qcom,pcie-sdx55
- items:
- enum:
- qcom,pcie-ipq5332
- qcom,pcie-ipq5424
- const: qcom,pcie-ipq9574
- items:
@@ -49,11 +50,11 @@ properties:
interrupts:
minItems: 1
maxItems: 8
maxItems: 9
interrupt-names:
minItems: 1
maxItems: 8
maxItems: 9
iommu-map:
minItems: 1
@@ -443,6 +444,7 @@ allOf:
interrupts:
minItems: 8
interrupt-names:
minItems: 8
items:
- const: msi0
- const: msi1
@@ -452,6 +454,7 @@ allOf:
- const: msi5
- const: msi6
- const: msi7
- const: global
- if:
properties:
@@ -599,6 +602,7 @@ allOf:
- properties:
interrupts:
minItems: 8
maxItems: 8
interrupt-names:
items:
- const: msi0