dt-bindings: PCI: convert amlogic,meson-pcie.txt to dt-schema
Convert the Amlogic Meson AXG DWC PCIe SoC controller bindings to dt-schema. Link: https://lore.kernel.org/r/20221117-b4-amlogic-bindings-convert-v4-5-34e623dbf789@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Neil Armstrong
committed by
Lorenzo Pieralisi
Lorenzo Pieralisi
parent
fe15c26ee2
commit
b80b848bdf
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic Meson AXG DWC PCIe SoC controller
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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description:
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Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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- $ref: /schemas/pci/snps,dw-pcie-common.yaml#
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# We need a select here so we don't match all nodes with 'snps,dw-pcie'
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select:
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properties:
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compatible:
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enum:
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- amlogic,axg-pcie
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- amlogic,g12a-pcie
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- amlogic,axg-pcie
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- amlogic,g12a-pcie
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- const: snps,dw-pcie
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reg:
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items:
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- description: External local bus interface registers
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- description: Meson designed configuration registers
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- description: PCIe configuration space
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reg-names:
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items:
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- const: elbi
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- const: cfg
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- const: config
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: PCIe GEN 100M PLL clock
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- description: PCIe RC clock gate
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- description: PCIe PHY clock
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clock-names:
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items:
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- const: pclk
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- const: port
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- const: general
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phys:
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maxItems: 1
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phy-names:
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const: pcie
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resets:
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items:
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- description: Port Reset
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- description: Shared APB reset
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reset-names:
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items:
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- const: port
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- const: apb
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num-lanes:
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const: 1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- clock
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- clock-names
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- "#address-cells"
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- "#size-cells"
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- "#interrupt-cells"
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- interrupt-map
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- interrupt-map-mask
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- ranges
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- bus-range
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- device_type
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- num-lanes
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- phys
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- phy-names
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie: pcie@f9800000 {
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compatible = "amlogic,axg-pcie", "snps,dw-pcie";
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reg = <0xf9800000 0x400000>, <0xff646000 0x2000>, <0xf9f00000 0x100000>;
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reg-names = "elbi", "cfg", "config";
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interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
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clocks = <&pclk>, <&clk_port>, <&clk_phy>;
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clock-names = "pclk", "port", "general";
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resets = <&reset_pcie_port>, <&reset_pcie_apb>;
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reset-names = "port", "apb";
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phys = <&pcie_phy>;
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phy-names = "pcie";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
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bus-range = <0x0 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <1>;
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ranges = <0x82000000 0 0 0xf9c00000 0 0x00300000>;
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};
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...
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@@ -1,70 +0,0 @@
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Amlogic Meson AXG DWC PCIE SoC controller
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Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
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It shares common functions with the PCIe DesignWare core driver and
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inherits common properties defined in
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Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
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Additional properties are described here:
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Required properties:
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- compatible:
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should contain :
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- "amlogic,axg-pcie" for AXG SoC Family
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- "amlogic,g12a-pcie" for G12A SoC Family
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to identify the core.
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- reg:
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should contain the configuration address space.
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- reg-names: Must be
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- "elbi" External local bus interface registers
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- "cfg" Meson specific registers
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- "config" PCIe configuration space
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- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Must include the following entries:
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- "pclk" PCIe GEN 100M PLL clock
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- "port" PCIe_x(A or B) RC clock gate
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- "general" PCIe Phy clock
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- resets: phandle to the reset lines.
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- reset-names: must contain "port" and "apb"
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- "port" Port A or B reset
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- "apb" Share APB reset
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- phys: should contain a phandle to the PCIE phy
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- phy-names: must contain "pcie"
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- device_type:
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should be "pci". As specified in snps,dw-pcie.yaml
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Example configuration:
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pcie: pcie@f9800000 {
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compatible = "amlogic,axg-pcie", "snps,dw-pcie";
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reg = <0x0 0xf9800000 0x0 0x400000
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0x0 0xff646000 0x0 0x2000
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0x0 0xf9f00000 0x0 0x100000>;
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reg-names = "elbi", "cfg", "config";
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reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
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bus-range = <0x0 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
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clocks = <&clkc CLKID_USB
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&clkc CLKID_PCIE_A
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&clkc CLKID_PCIE_CML_EN0>;
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clock-names = "general",
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"pclk",
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"port";
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resets = <&reset RESET_PCIE_A>,
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<&reset RESET_PCIE_APB>;
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reset-names = "port",
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"apb";
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phys = <&pcie_phy>;
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phy-names = "pcie";
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};
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