bnxt_en: Remove register mapping to support INTX
In legacy INTX mode, a register is mapped so that the INTX handler can read it to determine if the NIC is the source of the interrupt. This and all the related macros are no longer needed now that INTX is no longer supported. Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com> Reviewed-by: Hongguang Gao <hongguang.gao@broadcom.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: Michael Chan <michael.chan@broadcom.com> Link: https://patch.msgid.link/20240828183235.128948-7-michael.chan@broadcom.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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committed by
Jakub Kicinski
parent
e94d8d97c7
commit
af756aad3d
@@ -302,10 +302,6 @@ static bool bnxt_vf_pciid(enum board_idx idx)
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#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
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#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
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#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
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#define BNXT_CP_DB_IRQ_DIS(db) \
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writel(DB_CP_IRQ_DIS_FLAGS, db)
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#define BNXT_DB_CQ(db, idx) \
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writel(DB_CP_FLAGS | DB_RING_IDX(db, idx), (db)->doorbell)
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@@ -11959,20 +11955,6 @@ static int bnxt_update_phy_setting(struct bnxt *bp)
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return rc;
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}
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/* Common routine to pre-map certain register block to different GRC window.
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* A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
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* in PF and 3 windows in VF that can be customized to map in different
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* register blocks.
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*/
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static void bnxt_preset_reg_win(struct bnxt *bp)
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{
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if (BNXT_PF(bp)) {
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/* CAG registers map to GRC window #4 */
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writel(BNXT_CAG_REG_BASE,
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bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
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}
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}
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static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
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static int bnxt_reinit_after_abort(struct bnxt *bp)
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@@ -12077,7 +12059,6 @@ static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
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{
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int rc = 0;
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bnxt_preset_reg_win(bp);
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netif_carrier_off(bp->dev);
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if (irq_re_init) {
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/* Reserve rings now if none were reserved at driver probe. */
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@@ -1755,8 +1755,6 @@ struct bnxt_test_info {
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#define BNXT_GRCPF_REG_CHIMP_COMM 0x0
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#define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
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#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
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#define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
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#define BNXT_CAG_REG_BASE 0x300000
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#define BNXT_GRC_REG_STATUS_P5 0x520
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