drm/msm/hdmi: simplify code in pll_get_integloop_gain
[ Upstream commitc1beb6f75d] In pll_get_integloop_gain(), digclk_divsel=1 or 2, base=63 or 196ULL, so the base may be 63, 126, 196, 392. The condition base <= 2046 always true. Fixes:caedbf17c4("drm/msm: add msm8998 hdmi phy/pll support") Signed-off-by: Rex Nie <rex.nie@jaguarmicro.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/624153/ Link: https://lore.kernel.org/r/20241112074101.2206-1-rex.nie@jaguarmicro.com Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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committed by
Greg Kroah-Hartman
parent
99a877d607
commit
ae7d487347
@@ -137,7 +137,7 @@ static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk,
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base <<= (digclk_divsel == 2 ? 1 : 0);
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return (base <= 2046 ? base : 2046);
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return base;
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}
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static inline u32 pll_get_pll_cmp(u64 fdata, unsigned long ref_clk)
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