drm/amdgpu: Remove the MES self test
Remove MES self test as this conflicts the userqueue fence interrupts. v2:(Christian) - remove the amdgpu_mes_self_test() function and any now unused code. Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Arunpravin Paneer Selvam
committed by
Alex Deucher
Alex Deucher
parent
70773bef4e
commit
ac4a1f7f13
@@ -5144,9 +5144,6 @@ exit:
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}
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adev->in_suspend = false;
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if (adev->enable_mes)
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amdgpu_mes_self_test(adev);
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if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
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DRM_WARN("smart shift update failed\n");
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@@ -1405,175 +1405,6 @@ out_unlock:
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return r;
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}
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static int amdgpu_mes_test_create_gang_and_queues(struct amdgpu_device *adev,
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int pasid, int *gang_id,
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int queue_type, int num_queue,
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struct amdgpu_ring **added_rings,
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struct amdgpu_mes_ctx_data *ctx_data)
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{
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struct amdgpu_ring *ring;
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struct amdgpu_mes_gang_properties gprops = {0};
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int r, j;
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/* create a gang for the process */
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gprops.priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
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gprops.gang_quantum = adev->mes.default_gang_quantum;
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gprops.inprocess_gang_priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
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gprops.priority_level = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
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gprops.global_priority_level = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
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r = amdgpu_mes_add_gang(adev, pasid, &gprops, gang_id);
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if (r) {
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DRM_ERROR("failed to add gang\n");
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return r;
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}
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/* create queues for the gang */
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for (j = 0; j < num_queue; j++) {
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r = amdgpu_mes_add_ring(adev, *gang_id, queue_type, j,
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ctx_data, &ring);
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if (r) {
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DRM_ERROR("failed to add ring\n");
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break;
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}
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DRM_INFO("ring %s was added\n", ring->name);
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added_rings[j] = ring;
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}
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return 0;
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}
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static int amdgpu_mes_test_queues(struct amdgpu_ring **added_rings)
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{
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struct amdgpu_ring *ring;
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int i, r;
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for (i = 0; i < AMDGPU_MES_CTX_MAX_RINGS; i++) {
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ring = added_rings[i];
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if (!ring)
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continue;
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r = amdgpu_ring_test_helper(ring);
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if (r)
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return r;
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r = amdgpu_ring_test_ib(ring, 1000 * 10);
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if (r) {
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DRM_DEV_ERROR(ring->adev->dev,
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"ring %s ib test failed (%d)\n",
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ring->name, r);
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return r;
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} else
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DRM_INFO("ring %s ib test pass\n", ring->name);
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}
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return 0;
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}
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int amdgpu_mes_self_test(struct amdgpu_device *adev)
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{
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struct amdgpu_vm *vm = NULL;
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struct amdgpu_mes_ctx_data ctx_data = {0};
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struct amdgpu_ring *added_rings[AMDGPU_MES_CTX_MAX_RINGS] = { NULL };
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int gang_ids[3] = {0};
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int queue_types[][2] = { { AMDGPU_RING_TYPE_GFX, 1 },
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{ AMDGPU_RING_TYPE_COMPUTE, 1 },
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{ AMDGPU_RING_TYPE_SDMA, 1} };
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int i, r, pasid, k = 0;
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pasid = amdgpu_pasid_alloc(16);
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if (pasid < 0) {
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dev_warn(adev->dev, "No more PASIDs available!");
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pasid = 0;
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}
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vm = kzalloc(sizeof(*vm), GFP_KERNEL);
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if (!vm) {
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r = -ENOMEM;
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goto error_pasid;
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}
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r = amdgpu_vm_init(adev, vm, -1);
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if (r) {
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DRM_ERROR("failed to initialize vm\n");
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goto error_pasid;
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}
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r = amdgpu_mes_ctx_alloc_meta_data(adev, &ctx_data);
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if (r) {
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DRM_ERROR("failed to alloc ctx meta data\n");
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goto error_fini;
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}
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ctx_data.meta_data_gpu_addr = AMDGPU_VA_RESERVED_BOTTOM;
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r = amdgpu_mes_ctx_map_meta_data(adev, vm, &ctx_data);
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if (r) {
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DRM_ERROR("failed to map ctx meta data\n");
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goto error_vm;
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}
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r = amdgpu_mes_create_process(adev, pasid, vm);
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if (r) {
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DRM_ERROR("failed to create MES process\n");
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goto error_vm;
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}
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for (i = 0; i < ARRAY_SIZE(queue_types); i++) {
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/* On GFX v10.3, fw hasn't supported to map sdma queue. */
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if (amdgpu_ip_version(adev, GC_HWIP, 0) >=
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IP_VERSION(10, 3, 0) &&
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amdgpu_ip_version(adev, GC_HWIP, 0) <
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IP_VERSION(11, 0, 0) &&
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queue_types[i][0] == AMDGPU_RING_TYPE_SDMA)
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continue;
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r = amdgpu_mes_test_create_gang_and_queues(adev, pasid,
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&gang_ids[i],
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queue_types[i][0],
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queue_types[i][1],
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&added_rings[k],
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&ctx_data);
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if (r)
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goto error_queues;
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k += queue_types[i][1];
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}
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/* start ring test and ib test for MES queues */
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amdgpu_mes_test_queues(added_rings);
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error_queues:
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/* remove all queues */
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for (i = 0; i < ARRAY_SIZE(added_rings); i++) {
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if (!added_rings[i])
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continue;
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amdgpu_mes_remove_ring(adev, added_rings[i]);
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}
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for (i = 0; i < ARRAY_SIZE(gang_ids); i++) {
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if (!gang_ids[i])
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continue;
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amdgpu_mes_remove_gang(adev, gang_ids[i]);
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}
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amdgpu_mes_destroy_process(adev, pasid);
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error_vm:
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amdgpu_mes_ctx_unmap_meta_data(adev, &ctx_data);
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error_fini:
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amdgpu_vm_fini(adev, vm);
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error_pasid:
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if (pasid)
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amdgpu_pasid_free(pasid);
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amdgpu_mes_ctx_free_meta_data(&ctx_data);
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kfree(vm);
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return 0;
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}
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int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe)
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{
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const struct mes_firmware_header_v1_0 *mes_hdr;
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@@ -470,8 +470,6 @@ int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,
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int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev,
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struct amdgpu_mes_ctx_data *ctx_data);
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int amdgpu_mes_self_test(struct amdgpu_device *adev);
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int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev);
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/*
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@@ -1712,22 +1712,10 @@ static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block)
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return 0;
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}
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static int mes_v11_0_late_init(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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/* it's only intended for use in mes_self_test case, not for s0ix and reset */
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if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend &&
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(amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3)))
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amdgpu_mes_self_test(adev);
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return 0;
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}
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static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
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.name = "mes_v11_0",
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.early_init = mes_v11_0_early_init,
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.late_init = mes_v11_0_late_init,
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.late_init = NULL,
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.sw_init = mes_v11_0_sw_init,
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.sw_fini = mes_v11_0_sw_fini,
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.hw_init = mes_v11_0_hw_init,
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@@ -1820,21 +1820,10 @@ static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block)
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return 0;
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}
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static int mes_v12_0_late_init(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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/* it's only intended for use in mes_self_test case, not for s0ix and reset */
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if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend)
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amdgpu_mes_self_test(adev);
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return 0;
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}
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static const struct amd_ip_funcs mes_v12_0_ip_funcs = {
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.name = "mes_v12_0",
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.early_init = mes_v12_0_early_init,
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.late_init = mes_v12_0_late_init,
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.late_init = NULL,
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.sw_init = mes_v12_0_sw_init,
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.sw_fini = mes_v12_0_sw_fini,
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.hw_init = mes_v12_0_hw_init,
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