irqchip: Add driver for the RPMI system MSI service group
The RPMI specification defines a system MSI service group which allows application processors to receive MSIs upon system events such as graceful shutdown/reboot request, CPU hotplug event, memory hotplug event, etc. Add an irqchip driver for the RISC-V RPMI system MSI service group to directly receive system MSIs in Linux kernel. Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-14-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
This commit is contained in:
Anup Patel
committed by
Paul Walmsley
Paul Walmsley
parent
3e6cf38486
commit
aa43953e86
@@ -634,6 +634,13 @@ config RISCV_IMSIC
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select GENERIC_MSI_IRQ
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select IRQ_MSI_LIB
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config RISCV_RPMI_SYSMSI
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bool
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depends on MAILBOX
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_MSI_IRQ
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default RISCV
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config SIFIVE_PLIC
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bool
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depends on RISCV
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@@ -106,6 +106,7 @@ obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o
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obj-$(CONFIG_RISCV_APLIC) += irq-riscv-aplic-main.o irq-riscv-aplic-direct.o
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obj-$(CONFIG_RISCV_APLIC_MSI) += irq-riscv-aplic-msi.o
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obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o irq-riscv-imsic-platform.o
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obj-$(CONFIG_RISCV_RPMI_SYSMSI) += irq-riscv-rpmi-sysmsi.o
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obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
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obj-$(CONFIG_STARFIVE_JH8100_INTC) += irq-starfive-jh8100-intc.o
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obj-$(CONFIG_ACLINT_SSWI) += irq-aclint-sswi.o
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@@ -0,0 +1,287 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2025 Ventana Micro Systems Inc. */
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#include <linux/bits.h>
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#include <linux/bug.h>
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#include <linux/device.h>
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#include <linux/device/devres.h>
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#include <linux/dev_printk.h>
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#include <linux/errno.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/mailbox_client.h>
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#include <linux/mailbox/riscv-rpmi-message.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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struct rpmi_sysmsi_get_attrs_rx {
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__le32 status;
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__le32 sys_num_msi;
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__le32 flag0;
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__le32 flag1;
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};
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#define RPMI_SYSMSI_MSI_ATTRIBUTES_FLAG0_PREF_PRIV BIT(0)
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struct rpmi_sysmsi_set_msi_state_tx {
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__le32 sys_msi_index;
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__le32 sys_msi_state;
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};
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struct rpmi_sysmsi_set_msi_state_rx {
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__le32 status;
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};
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#define RPMI_SYSMSI_MSI_STATE_ENABLE BIT(0)
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#define RPMI_SYSMSI_MSI_STATE_PENDING BIT(1)
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struct rpmi_sysmsi_set_msi_target_tx {
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__le32 sys_msi_index;
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__le32 sys_msi_address_low;
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__le32 sys_msi_address_high;
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__le32 sys_msi_data;
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};
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struct rpmi_sysmsi_set_msi_target_rx {
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__le32 status;
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};
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struct rpmi_sysmsi_priv {
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struct device *dev;
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struct mbox_client client;
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struct mbox_chan *chan;
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u32 nr_irqs;
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u32 gsi_base;
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};
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static int rpmi_sysmsi_get_num_msi(struct rpmi_sysmsi_priv *priv)
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{
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struct rpmi_sysmsi_get_attrs_rx rx;
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struct rpmi_mbox_message msg;
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int ret;
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rpmi_mbox_init_send_with_response(&msg, RPMI_SYSMSI_SRV_GET_ATTRIBUTES,
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NULL, 0, &rx, sizeof(rx));
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ret = rpmi_mbox_send_message(priv->chan, &msg);
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if (ret)
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return ret;
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if (rx.status)
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return rpmi_to_linux_error(le32_to_cpu(rx.status));
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return le32_to_cpu(rx.sys_num_msi);
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}
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static int rpmi_sysmsi_set_msi_state(struct rpmi_sysmsi_priv *priv,
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u32 sys_msi_index, u32 sys_msi_state)
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{
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struct rpmi_sysmsi_set_msi_state_tx tx;
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struct rpmi_sysmsi_set_msi_state_rx rx;
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struct rpmi_mbox_message msg;
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int ret;
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tx.sys_msi_index = cpu_to_le32(sys_msi_index);
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tx.sys_msi_state = cpu_to_le32(sys_msi_state);
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rpmi_mbox_init_send_with_response(&msg, RPMI_SYSMSI_SRV_SET_MSI_STATE,
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&tx, sizeof(tx), &rx, sizeof(rx));
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ret = rpmi_mbox_send_message(priv->chan, &msg);
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if (ret)
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return ret;
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if (rx.status)
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return rpmi_to_linux_error(le32_to_cpu(rx.status));
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return 0;
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}
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static int rpmi_sysmsi_set_msi_target(struct rpmi_sysmsi_priv *priv,
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u32 sys_msi_index, struct msi_msg *m)
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{
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struct rpmi_sysmsi_set_msi_target_tx tx;
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struct rpmi_sysmsi_set_msi_target_rx rx;
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struct rpmi_mbox_message msg;
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int ret;
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tx.sys_msi_index = cpu_to_le32(sys_msi_index);
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tx.sys_msi_address_low = cpu_to_le32(m->address_lo);
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tx.sys_msi_address_high = cpu_to_le32(m->address_hi);
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tx.sys_msi_data = cpu_to_le32(m->data);
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rpmi_mbox_init_send_with_response(&msg, RPMI_SYSMSI_SRV_SET_MSI_TARGET,
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&tx, sizeof(tx), &rx, sizeof(rx));
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ret = rpmi_mbox_send_message(priv->chan, &msg);
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if (ret)
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return ret;
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if (rx.status)
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return rpmi_to_linux_error(le32_to_cpu(rx.status));
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return 0;
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}
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static void rpmi_sysmsi_irq_mask(struct irq_data *d)
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{
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struct rpmi_sysmsi_priv *priv = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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int ret;
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ret = rpmi_sysmsi_set_msi_state(priv, hwirq, 0);
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if (ret)
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dev_warn(priv->dev, "Failed to mask hwirq %lu (error %d)\n", hwirq, ret);
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irq_chip_mask_parent(d);
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}
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static void rpmi_sysmsi_irq_unmask(struct irq_data *d)
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{
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struct rpmi_sysmsi_priv *priv = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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int ret;
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irq_chip_unmask_parent(d);
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ret = rpmi_sysmsi_set_msi_state(priv, hwirq, RPMI_SYSMSI_MSI_STATE_ENABLE);
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if (ret)
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dev_warn(priv->dev, "Failed to unmask hwirq %lu (error %d)\n", hwirq, ret);
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}
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static void rpmi_sysmsi_write_msg(struct irq_data *d, struct msi_msg *msg)
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{
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struct rpmi_sysmsi_priv *priv = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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int ret;
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/* For zeroed MSI, do nothing as of now */
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if (!msg->address_hi && !msg->address_lo && !msg->data)
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return;
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ret = rpmi_sysmsi_set_msi_target(priv, hwirq, msg);
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if (ret)
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dev_warn(priv->dev, "Failed to set target for hwirq %lu (error %d)\n", hwirq, ret);
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}
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static void rpmi_sysmsi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
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{
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arg->desc = desc;
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arg->hwirq = desc->data.icookie.value;
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}
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static int rpmi_sysmsi_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
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unsigned long *hwirq, unsigned int *type)
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{
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struct msi_domain_info *info = d->host_data;
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struct rpmi_sysmsi_priv *priv = info->data;
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if (WARN_ON(fwspec->param_count < 1))
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return -EINVAL;
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/* For DT, gsi_base is always zero. */
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*hwirq = fwspec->param[0] - priv->gsi_base;
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*type = IRQ_TYPE_NONE;
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return 0;
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}
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static const struct msi_domain_template rpmi_sysmsi_template = {
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.chip = {
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.name = "RPMI-SYSMSI",
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.irq_mask = rpmi_sysmsi_irq_mask,
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.irq_unmask = rpmi_sysmsi_irq_unmask,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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.irq_write_msi_msg = rpmi_sysmsi_write_msg,
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.flags = IRQCHIP_SET_TYPE_MASKED |
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IRQCHIP_SKIP_SET_WAKE |
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IRQCHIP_MASK_ON_SUSPEND,
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},
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.ops = {
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.set_desc = rpmi_sysmsi_set_desc,
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.msi_translate = rpmi_sysmsi_translate,
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},
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.info = {
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.bus_token = DOMAIN_BUS_WIRED_TO_MSI,
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.flags = MSI_FLAG_USE_DEV_FWNODE,
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.handler = handle_simple_irq,
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.handler_name = "simple",
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},
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};
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static int rpmi_sysmsi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rpmi_sysmsi_priv *priv;
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int rc;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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/* Setup mailbox client */
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priv->client.dev = priv->dev;
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priv->client.rx_callback = NULL;
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priv->client.tx_block = false;
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priv->client.knows_txdone = true;
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priv->client.tx_tout = 0;
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/* Request mailbox channel */
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priv->chan = mbox_request_channel(&priv->client, 0);
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if (IS_ERR(priv->chan))
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return PTR_ERR(priv->chan);
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/* Get number of system MSIs */
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rc = rpmi_sysmsi_get_num_msi(priv);
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if (rc < 1) {
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mbox_free_channel(priv->chan);
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if (rc)
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return dev_err_probe(dev, rc, "Failed to get number of system MSIs\n");
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else
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return dev_err_probe(dev, -ENODEV, "No system MSIs found\n");
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}
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priv->nr_irqs = rc;
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/*
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* The device MSI domain for platform devices on RISC-V architecture
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* is only available after the MSI controller driver is probed so,
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* explicitly configure here.
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*/
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if (!dev_get_msi_domain(dev)) {
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/*
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* The device MSI domain for OF devices is only set at the
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* time of populating/creating OF device. If the device MSI
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* domain is discovered later after the OF device is created
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* then we need to set it explicitly before using any platform
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* MSI functions.
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*/
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if (dev_of_node(dev))
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of_msi_configure(dev, dev_of_node(dev));
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if (!dev_get_msi_domain(dev)) {
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mbox_free_channel(priv->chan);
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return -EPROBE_DEFER;
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}
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}
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if (!msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN,
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&rpmi_sysmsi_template,
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priv->nr_irqs, priv, priv)) {
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mbox_free_channel(priv->chan);
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return dev_err_probe(dev, -ENOMEM, "failed to create MSI irq domain\n");
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}
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dev_info(dev, "%u system MSIs registered\n", priv->nr_irqs);
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return 0;
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}
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static const struct of_device_id rpmi_sysmsi_match[] = {
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{ .compatible = "riscv,rpmi-system-msi" },
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{}
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};
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static struct platform_driver rpmi_sysmsi_driver = {
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.driver = {
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.name = "rpmi-sysmsi",
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.of_match_table = rpmi_sysmsi_match,
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},
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.probe = rpmi_sysmsi_probe,
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};
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builtin_platform_driver(rpmi_sysmsi_driver);
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@@ -91,6 +91,7 @@ static inline int rpmi_to_linux_error(int rpmi_error)
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}
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/* RPMI service group IDs */
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#define RPMI_SRVGRP_SYSTEM_MSI 0x00002
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#define RPMI_SRVGRP_CLOCK 0x00008
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/* RPMI clock service IDs */
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@@ -106,6 +107,18 @@ enum rpmi_clock_service_id {
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RPMI_CLK_SRV_ID_MAX_COUNT
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};
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/* RPMI system MSI service IDs */
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enum rpmi_sysmsi_service_id {
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RPMI_SYSMSI_SRV_ENABLE_NOTIFICATION = 0x01,
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RPMI_SYSMSI_SRV_GET_ATTRIBUTES = 0x02,
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RPMI_SYSMSI_SRV_GET_MSI_ATTRIBUTES = 0x03,
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RPMI_SYSMSI_SRV_SET_MSI_STATE = 0x04,
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RPMI_SYSMSI_SRV_GET_MSI_STATE = 0x05,
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RPMI_SYSMSI_SRV_SET_MSI_TARGET = 0x06,
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RPMI_SYSMSI_SRV_GET_MSI_TARGET = 0x07,
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RPMI_SYSMSI_SRV_ID_MAX_COUNT
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};
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/* RPMI Linux mailbox attribute IDs */
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enum rpmi_mbox_attribute_id {
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RPMI_MBOX_ATTR_SPEC_VERSION,
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