arm64: dts: add support for A5 based Amlogic AV400
Amlogic A5 is an application processor designed for smart audio and IoT applications. Add basic support for the A5 based Amlogic AV400 board, which describes the following components: CPU, GIC, IRQ, Timer and UART. These are capable of booting up into the serial console. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240401-basic_dt-v3-5-cb29ae1c16da@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Neil Armstrong
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@@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb
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dtb-$(CONFIG_ARCH_MESON) += amlogic-a5-a113x2-av400.dtb
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dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
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dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb
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dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
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@@ -0,0 +1,42 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "amlogic-a5.dtsi"
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/ {
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model = "Amlogic A113X2 av400 Development Board";
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compatible = "amlogic,av400", "amlogic,a5";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart_b;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 10 MiB reserved for ARM Trusted Firmware */
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secmon_reserved: secmon@5000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x05000000 0x0 0xa00000>;
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no-map;
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};
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};
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};
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&uart_b {
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status = "okay";
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};
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@@ -0,0 +1,40 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
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*/
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#include "amlogic-a4-common.dtsi"
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/ {
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "psci";
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "psci";
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};
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};
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};
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