TWxSoftware/twx-linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clk: rockchip: Add clock controller for the RK3562

Browse Source 
Add the clock tree definition for the new RK3562 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ia96ad61555537333a8ac54158360e1d23d971135
This commit is contained in:
Finley Xiao
2022-06-29 20:31:42 +08:00
committed by Tao Huang
parent 14d8aa4a04
commit a621b1189c
4 changed files with 1276 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/clk/rockchip/Kconfig
+7
View File
@@ -114,6 +114,13 @@ config CLK_RK3528
help
Build the driver for RK3528 Clock Driver.
config CLK_RK3562
tristate "Rockchip RK3562 clock controller support"
depends on CPU_RK3562 || COMPILE_TEST
default y
help
Build the driver for RK3562 Clock Driver.
config CLK_RK3568
tristate "Rockchip RK3568 clock controller support"
depends on CPU_RK3568 || COMPILE_TEST
drivers/clk/rockchip/Makefile
+1
View File
@@ -34,5 +34,6 @@ obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o
obj-$(CONFIG_CLK_RK3562) += clk-rk3562.o
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o
drivers/clk/rockchip/clk-rk3562.c
+1229
View File
File diff suppressed because it is too large Load Diff
drivers/clk/rockchip/clk.h
+39
View File
@@ -332,6 +332,45 @@ struct clk;
#define RK3528_GLB_SRST_FST 0xc08
#define RK3528_GLB_SRST_SND 0xc0c
#define RK3562_PMU0_CRU_BASE 0x10000
#define RK3562_PMU1_CRU_BASE 0x18000
#define RK3562_DDR_CRU_BASE 0x20000
#define RK3562_SUBDDR_CRU_BASE 0x28000
#define RK3562_PERI_CRU_BASE 0x30000
#define RK3562_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40)
#define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20)
#define RK3562_MODE_CON 0x600
#define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380)
#define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380)
#define RK3562_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
#define RK3562_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
#define RK3562_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
#define RK3562_DDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100)
#define RK3562_DDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180)
#define RK3562_DDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200)
#define RK3562_SUBDDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100)
#define RK3562_SUBDDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180)
#define RK3562_SUBDDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200)
#define RK3562_PERI_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100)
#define RK3562_PERI_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300)
#define RK3562_PERI_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400)
#define RK3562_PMU0_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100)
#define RK3562_PMU0_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180)
#define RK3562_PMU0_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200)
#define RK3562_PMU1_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100)
#define RK3562_PMU1_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180)
#define RK3562_PMU1_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200)
#define RK3562_GLB_SRST_FST 0x614
#define RK3562_GLB_SRST_SND 0x618
#define RK3562_GLB_RST_CON 0x61c
#define RK3562_GLB_RST_ST 0x620
#define RK3562_SDMMC0_CON0 0x624
#define RK3562_SDMMC0_CON1 0x628
#define RK3562_SDMMC1_CON0 0x62c
#define RK3562_SDMMC1_CON1 0x630
#define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3568_MODE_CON0 0xc0
#define RK3568_MISC_CON0 0xc4