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spi: spi-cadence-quadspi: add more logs

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Signed-off-by: Heinrich Toews <ht@twx-software.de>
This commit is contained in:
Heinrich Toews
2026-02-17 12:48:17 +01:00
parent a84b9e8e12
commit a0085a9cb9
1 changed files with 25 additions and 20 deletions
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drivers/mtd/spi-nor/everspin.c
+25 -20
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@@ -7,19 +7,18 @@
#include <linux/mtd/spi-nor.h>
#include "core.h"
/* Opcodes und Register-Definitionen */
/* Opcodes and Register Definitions */
#define SPINOR_OP_EVERSPIN_WRAR 0x71 /* Write Any Register */
#define SPINOR_OP_EVERSPIN_RDAR 0x65 /* Read Any Register */
#define SPINOR_REG_EVERSPIN_CFR1V 0x00800002 /* Volatile CFR1 Adresse */
#define EVERSPIN_OCTAL_STR_ENABLE 0x01 /* Wert für Octal STR Modus */
#define SPINOR_REG_EVERSPIN_CFR1V 0x00800002 /* Volatile CFR1 Address */
#define EVERSPIN_OCTAL_STR_ENABLE 0x01 /* Value for Octal STR Mode */
/**
* everspin_mram_write_reg - Hilfsfunktion zum Schreiben von Registern
* everspin_mram_write_reg - Helper to write to volatile/non-volatile registers
*/
static int everspin_mram_write_reg(struct spi_nor *nor, u32 addr, u8 val)
{
/* Explizite Definition: CMD(1-wire), ADDR(1-wire, 3 byte), DATA(1-wire, 1 byte) */
struct spi_mem_op op =
struct spi_mem_op op =
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_EVERSPIN_WRAR, 1),
SPI_MEM_OP_ADDR(3, addr, 1),
SPI_MEM_OP_NO_DUMMY,
@@ -31,32 +30,38 @@ static int everspin_mram_write_reg(struct spi_nor *nor, u32 addr, u8 val)
static void everspin_mram_default_init(struct spi_nor *nor)
{
struct spi_mem_op op =
struct spi_mem_op op;
int ret;
dev_info(nor->dev, "Starting Everspin MRAM initialization (STR Octal)...\n");
/* 1. Read Status Register 1 (SR1) to diagnose BP bits */
op = (struct spi_mem_op)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
int ret;
dev_info(nor->dev, "Everspin MRAM Init: Checking Status Register\n");
/* SR1 auslesen mit 1-wire Protokoll */
ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
if (ret) {
dev_err(nor->dev, "SR1 read failed: %d\n", ret);
dev_err(nor->dev, "Error reading SR1 register (%d)\n", ret);
} else {
u8 sr1 = nor->bouncebuf[0];
dev_info(nor->dev, "SR1: 0x%02x (BP-Bits: 0x%0x)\n", sr1, (sr1 & 0x3C) >> 2);
u8 bp_bits = (sr1 & GENMASK(5, 2)) >> 2;
dev_info(nor->dev, "SR1: 0x%02x | BP bits: 0x%x (0 = no protection)\n", sr1, bp_bits);
if (bp_bits)
dev_warn(nor->dev, "Hardware write protection (BP bits) is active!\n");
}
/* CFR1V schreiben: Octal Mode Enable */
/* 2. Switch to Octal Mode via CFR1V */
dev_info(nor->dev, "Setting CFR1V to Octal STR (Addr 0x%x)...\n", SPINOR_REG_EVERSPIN_CFR1V);
ret = everspin_mram_write_reg(nor, SPINOR_REG_EVERSPIN_CFR1V, EVERSPIN_OCTAL_STR_ENABLE);
if (ret)
dev_err(nor->dev, "CFR1V write failed: %d\n", ret);
dev_err(nor->dev, "Error writing CFR1V mode register (%d)\n", ret);
else
dev_info(nor->dev, "CFR1V set to Octal STR\n");
dev_info(nor->dev, "CFR1V successfully set to Octal STR.\n");
/* Kernel Parameter */
/* 3. Synchronize kernel parameters */
nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
nor->params->rdsr_dummy = 8;
nor->params->rdsr_addr_nbytes = 0;
@@ -64,12 +69,12 @@ static void everspin_mram_default_init(struct spi_nor *nor)
nor->flags &= ~SNOR_F_HAS_16BIT_SR;
nor->params->quad_enable = NULL;
dev_info(nor->dev, "Standard-Parameter für OSPI-Controller gesetzt.\n");
dev_info(nor->dev, "Standard parameters for OSPI controller set.\n");
}
static int everspin_mram_late_init(struct spi_nor *nor)
{
dev_info(nor->dev, "Konfiguriere Octal Opcodes für Read/Write...\n");
dev_info(nor->dev, "Configuring Octal opcodes for Read/Write...\n");
/* Read Settings: 1-8-8 STR */
nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8;
@@ -81,7 +86,7 @@ static int everspin_mram_late_init(struct spi_nor *nor)
spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_1_8_8],
SPINOR_OP_PP_1_8_8, SNOR_PROTO_1_8_8);
dev_info(nor->dev, "Everspin MRAM erfolgreich im Octal-Modus initialisiert.\n");
dev_info(nor->dev, "Everspin MRAM successfully initialized in Octal mode.\n");
return 0;
}