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phy: rockchip: usbdp: Only verify link rates/lanes/voltage when the corresponding set flags are set

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According documentation of phy_configure_opts_dp, at the configure
stage, link rates should only be verify/configure when set_rate
flag is set, the same applies to lanes and voltage.

So do it as the documentation says.
Because voltage setting depends on the lanes, link rates set
previously, so record the link rates and lanes at it's verify stage.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20250312080041.524546-1-andyshrk@163.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Andy Yan
2025-03-12 16:00:07 +08:00
committed by Vinod Koul
parent ebf198f17b
commit 969a38be43
1 changed files with 62 additions and 43 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/phy/rockchip/phy-rockchip-usbdp.c
+62 -43
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@@ -187,6 +187,8 @@ struct rk_udphy {
u32 dp_aux_din_sel;
bool dp_sink_hpd_sel;
bool dp_sink_hpd_cfg;
unsigned int link_rate;
unsigned int lanes;
u8 bw;
int id;
@@ -1103,13 +1105,35 @@ static int rk_udphy_dp_phy_power_off(struct phy *phy)
return 0;
}
static int rk_udphy_dp_phy_verify_link_rate(unsigned int link_rate)
/*
* Verify link rate
*/
static int rk_udphy_dp_phy_verify_link_rate(struct rk_udphy *udphy,
struct phy_configure_opts_dp *dp)
{
switch (link_rate) {
switch (dp->link_rate) {
case 1620:
case 2700:
case 5400:
case 8100:
udphy->link_rate = dp->link_rate;
break;
default:
return -EINVAL;
}
return 0;
}
static int rk_udphy_dp_phy_verify_lanes(struct rk_udphy *udphy,
struct phy_configure_opts_dp *dp)
{
switch (dp->lanes) {
case 1:
case 2:
case 4:
/* valid lane count. */
udphy->lanes = dp->lanes;
break;
default:
@@ -1119,45 +1143,26 @@ static int rk_udphy_dp_phy_verify_link_rate(unsigned int link_rate)
return 0;
}
static int rk_udphy_dp_phy_verify_config(struct rk_udphy *udphy,
struct phy_configure_opts_dp *dp)
/*
* If changing voltages is required, check swing and pre-emphasis
* levels, per-lane.
*/
static int rk_udphy_dp_phy_verify_voltages(struct rk_udphy *udphy,
struct phy_configure_opts_dp *dp)
{
int i, ret;
int i;
/* If changing link rate was required, verify it's supported. */
ret = rk_udphy_dp_phy_verify_link_rate(dp->link_rate);
if (ret)
return ret;
/* Lane count verified previously. */
for (i = 0; i < udphy->lanes; i++) {
if (dp->voltage[i] > 3 || dp->pre[i] > 3)
return -EINVAL;
/* Verify lane count. */
switch (dp->lanes) {
case 1:
case 2:
case 4:
/* valid lane count. */
break;
default:
return -EINVAL;
}
/*
* If changing voltages is required, check swing and pre-emphasis
* levels, per-lane.
*/
if (dp->set_voltages) {
/* Lane count verified previously. */
for (i = 0; i < dp->lanes; i++) {
if (dp->voltage[i] > 3 || dp->pre[i] > 3)
return -EINVAL;
/*
* Sum of voltage swing and pre-emphasis levels cannot
* exceed 3.
*/
if (dp->voltage[i] + dp->pre[i] > 3)
return -EINVAL;
}
/*
* Sum of voltage swing and pre-emphasis levels cannot
* exceed 3.
*/
if (dp->voltage[i] + dp->pre[i] > 3)
return -EINVAL;
}
return 0;
@@ -1197,9 +1202,23 @@ static int rk_udphy_dp_phy_configure(struct phy *phy,
u32 i, val, lane;
int ret;
ret = rk_udphy_dp_phy_verify_config(udphy, dp);
if (ret)
return ret;
if (dp->set_rate) {
ret = rk_udphy_dp_phy_verify_link_rate(udphy, dp);
if (ret)
return ret;
}
if (dp->set_lanes) {
ret = rk_udphy_dp_phy_verify_lanes(udphy, dp);
if (ret)
return ret;
}
if (dp->set_voltages) {
ret = rk_udphy_dp_phy_verify_voltages(udphy, dp);
if (ret)
return ret;
}
if (dp->set_rate) {
regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
@@ -1244,9 +1263,9 @@ static int rk_udphy_dp_phy_configure(struct phy *phy,
}
if (dp->set_voltages) {
for (i = 0; i < dp->lanes; i++) {
for (i = 0; i < udphy->lanes; i++) {
lane = udphy->dp_lane_sel[i];
switch (dp->link_rate) {
switch (udphy->link_rate) {
case 1620:
case 2700:
regmap_update_bits(udphy->pma_regmap,