drm/amdgpu/sdma5: split out per instance resume function
Extract the resume sequence from sdma_v5_0_gfx_resume for starting/restarting an individual instance. Signed-off-by: Jiadong Zhu <Jiadong.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jiadong Zhu
committed by
Alex Deucher
Alex Deucher
parent
bc4688aed5
commit
94daae9744
@@ -705,14 +705,16 @@ static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
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}
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/**
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* sdma_v5_0_gfx_resume - setup and start the async dma engines
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* sdma_v5_0_gfx_resume_instance - start/restart a certain sdma engine
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*
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* @adev: amdgpu_device pointer
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* @i: instance
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* @restore: used to restore wptr when restart
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*
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* Set up the gfx DMA ring buffers and enable them (NAVI10).
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* Returns 0 for success, error for failure.
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* Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
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* Return 0 for success.
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*/
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static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
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static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
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{
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struct amdgpu_ring *ring;
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u32 rb_cntl, ib_cntl;
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@@ -722,142 +724,163 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
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u32 temp;
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u32 wptr_poll_cntl;
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u64 wptr_gpu_addr;
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int i, r;
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for (i = 0; i < adev->sdma.num_instances; i++) {
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ring = &adev->sdma.instance[i].ring;
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ring = &adev->sdma.instance[i].ring;
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if (!amdgpu_sriov_vf(adev))
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
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if (!amdgpu_sriov_vf(adev))
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
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/* Set ring buffer size in dwords */
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rb_bufsz = order_base_2(ring->ring_size / 4);
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rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
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/* Set ring buffer size in dwords */
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rb_bufsz = order_base_2(ring->ring_size / 4);
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rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
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#ifdef __BIG_ENDIAN
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
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RPTR_WRITEBACK_SWAP_ENABLE, 1);
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
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RPTR_WRITEBACK_SWAP_ENABLE, 1);
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#endif
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
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/* Initialize the ring buffer's read and write pointers */
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/* Initialize the ring buffer's read and write pointers */
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if (restore) {
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
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} else {
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
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}
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/* setup the wptr shadow polling */
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wptr_gpu_addr = ring->wptr_gpu_addr;
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
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lower_32_bits(wptr_gpu_addr));
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
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upper_32_bits(wptr_gpu_addr));
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wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
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mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
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wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
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SDMA0_GFX_RB_WPTR_POLL_CNTL,
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F32_POLL_ENABLE, 1);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
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wptr_poll_cntl);
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/* setup the wptr shadow polling */
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wptr_gpu_addr = ring->wptr_gpu_addr;
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
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lower_32_bits(wptr_gpu_addr));
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
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upper_32_bits(wptr_gpu_addr));
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wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
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mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
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wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
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SDMA0_GFX_RB_WPTR_POLL_CNTL,
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F32_POLL_ENABLE, 1);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
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wptr_poll_cntl);
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/* set the wb address whether it's enabled or not */
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
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upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
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lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
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/* set the wb address whether it's enabled or not */
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
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upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
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lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
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ring->gpu_addr >> 8);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
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ring->gpu_addr >> 40);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
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ring->gpu_addr >> 8);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
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ring->gpu_addr >> 40);
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if (!restore)
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ring->wptr = 0;
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/* before programing wptr to a less value, need set minor_ptr_update first */
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
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/* before programing wptr to a less value, need set minor_ptr_update first */
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
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if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
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lower_32_bits(ring->wptr << 2));
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
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upper_32_bits(ring->wptr << 2));
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}
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if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
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lower_32_bits(ring->wptr << 2));
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
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upper_32_bits(ring->wptr << 2));
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}
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doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
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doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
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mmSDMA0_GFX_DOORBELL_OFFSET));
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doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
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doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
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mmSDMA0_GFX_DOORBELL_OFFSET));
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if (ring->use_doorbell) {
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doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
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doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
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OFFSET, ring->doorbell_index);
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} else {
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doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
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}
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
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doorbell_offset);
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if (ring->use_doorbell) {
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doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
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doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
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OFFSET, ring->doorbell_index);
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} else {
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doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
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}
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
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doorbell_offset);
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adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
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ring->doorbell_index, 20);
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adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
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ring->doorbell_index, 20);
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if (amdgpu_sriov_vf(adev))
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sdma_v5_0_ring_set_wptr(ring);
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if (amdgpu_sriov_vf(adev))
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sdma_v5_0_ring_set_wptr(ring);
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/* set minor_ptr_update to 0 after wptr programed */
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
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/* set minor_ptr_update to 0 after wptr programed */
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
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if (!amdgpu_sriov_vf(adev)) {
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/* set utc l1 enable flag always to 1 */
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temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
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temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
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if (!amdgpu_sriov_vf(adev)) {
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/* set utc l1 enable flag always to 1 */
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temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
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temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
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/* enable MCBP */
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temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
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/* enable MCBP */
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temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
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/* Set up RESP_MODE to non-copy addresses */
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temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
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temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
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temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
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/* Set up RESP_MODE to non-copy addresses */
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temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
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temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
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temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
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/* program default cache read and write policy */
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temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
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/* clean read policy and write policy bits */
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temp &= 0xFF0FFF;
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temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
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}
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/* program default cache read and write policy */
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temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
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/* clean read policy and write policy bits */
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temp &= 0xFF0FFF;
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temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
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}
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if (!amdgpu_sriov_vf(adev)) {
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/* unhalt engine */
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temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
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temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
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}
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if (!amdgpu_sriov_vf(adev)) {
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/* unhalt engine */
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temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
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temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
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WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
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}
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/* enable DMA RB */
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
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/* enable DMA RB */
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
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ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
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ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
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ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
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ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
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#ifdef __BIG_ENDIAN
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ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
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ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
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#endif
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/* enable DMA IBs */
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
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/* enable DMA IBs */
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WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
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if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
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sdma_v5_0_ctx_switch_enable(adev, true);
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sdma_v5_0_enable(adev, true);
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}
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if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
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sdma_v5_0_ctx_switch_enable(adev, true);
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sdma_v5_0_enable(adev, true);
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}
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|
||||
r = amdgpu_ring_test_helper(ring);
|
||||
return amdgpu_ring_test_helper(ring);
|
||||
}
|
||||
|
||||
/**
|
||||
* sdma_v5_0_gfx_resume - setup and start the async dma engines
|
||||
*
|
||||
* @adev: amdgpu_device pointer
|
||||
*
|
||||
* Set up the gfx DMA ring buffers and enable them (NAVI10).
|
||||
* Returns 0 for success, error for failure.
|
||||
*/
|
||||
static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
|
||||
{
|
||||
int i, r;
|
||||
|
||||
for (i = 0; i < adev->sdma.num_instances; i++) {
|
||||
r = sdma_v5_0_gfx_resume_instance(adev, i, false);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user