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x86/gsseg: Use the LKGS instruction if available for load_gs_index()

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The LKGS instruction atomically loads a segment descriptor into the
%gs descriptor registers, *except* that %gs.base is unchanged, and the
base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly
what we want this function to do.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20230112072032.35626-6-xin3.li@intel.com
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
H. Peter Anvin (Intel)
2023-01-11 23:20:32 -08:00
committed by Ingo Molnar
parent ae53fa1870
commit 92cbbadf73
3 changed files with 31 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/x86/include/asm/gsseg.h
+29 -4
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@@ -14,17 +14,42 @@
extern asmlinkage void asm_load_gs_index(u16 selector);
/* Replace with "lkgs %di" once binutils support LKGS instruction */
#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7)
static inline void native_lkgs(unsigned int selector)
{
u16 sel = selector;
asm_inline volatile("1: " LKGS_DI
_ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel])
: [sel] "+D" (sel));
}
static inline void native_load_gs_index(unsigned int selector)
{
unsigned long flags;
if (cpu_feature_enabled(X86_FEATURE_LKGS)) {
native_lkgs(selector);
} else {
unsigned long flags;
local_irq_save(flags);
asm_load_gs_index(selector);
local_irq_restore(flags);
local_irq_save(flags);
asm_load_gs_index(selector);
local_irq_restore(flags);
}
}
#endif /* CONFIG_X86_64 */
static inline void __init lkgs_init(void)
{
#ifdef CONFIG_PARAVIRT_XXL
#ifdef CONFIG_X86_64
if (cpu_feature_enabled(X86_FEATURE_LKGS))
pv_ops.cpu.load_gs_index = native_lkgs;
#endif
#endif
}
#ifndef CONFIG_PARAVIRT_XXL
static inline void load_gs_index(unsigned int selector)
arch/x86/kernel/cpu/common.c
+1
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@@ -1960,6 +1960,7 @@ void __init identify_boot_cpu(void)
setup_cr_pinning();
tsx_init();
lkgs_init();
}
void identify_secondary_cpu(struct cpuinfo_x86 *c)
arch/x86/xen/enlighten_pv.c
+1
View File
@@ -276,6 +276,7 @@ static void __init xen_init_capabilities(void)
setup_clear_cpu_cap(X86_FEATURE_ACC);
setup_clear_cpu_cap(X86_FEATURE_X2APIC);
setup_clear_cpu_cap(X86_FEATURE_SME);
setup_clear_cpu_cap(X86_FEATURE_LKGS);
/*
* Xen PV would need some work to support PCID: CR3 handling as well