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iio: frequency: ad9523: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Updated help text to 'may' require buffers to be in their own cacheline.

Fixes: cd1678f963 ("iio: frequency: New driver for AD9523 SPI Low Jitter Clock Generator")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-66-jic23@kernel.org
This commit is contained in:
Jonathan Cameron
2022-05-08 18:56:45 +01:00
parent b9ac08b328
commit 8ff2eb625c
1 changed files with 3 additions and 3 deletions
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drivers/iio/frequency/ad9523.c
+3 -3
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@@ -287,13 +287,13 @@ struct ad9523_state {
struct mutex lock;
/*
* DMA (thus cache coherency maintenance) requires the
* transfer buffers to live in their own cache lines.
* DMA (thus cache coherency maintenance) may require that
* transfer buffers live in their own cache lines.
*/
union {
__be32 d32;
u8 d8[4];
} data[2] ____cacheline_aligned;
} data[2] __aligned(IIO_DMA_MINALIGN);
};
static int ad9523_read(struct iio_dev *indio_dev, unsigned int addr)