crypto: qat - fix unintentional re-enabling of error interrupts
[ Upstream commit f0622894c5 ]
The logic that detects pending VF2PF interrupts unintentionally clears
the section of the error mask register(s) not related to VF2PF.
This might cause interrupts unrelated to VF2PF, reported through
errsou3 and errsou5, to be reported again after the execution
of the function disable_pending_vf2pf_interrupts() in dh895xcc
and GEN2 devices.
Fix by updating only section of errmsk3 and errmsk5 related to VF2PF.
Signed-off-by: Hareshx Sankar Raj <hareshx.sankar.raj@intel.com>
Reviewed-by: Damian Muszynski <damian.muszynski@intel.com>
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
bba47fe3b0
commit
8f2dabd2ee
@@ -100,7 +100,9 @@ static u32 adf_gen2_disable_pending_vf2pf_interrupts(void __iomem *pmisc_addr)
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errmsk3 |= ADF_GEN2_ERR_MSK_VF2PF(ADF_GEN2_VF_MSK);
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3);
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errmsk3 &= ADF_GEN2_ERR_MSK_VF2PF(sources | disabled);
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/* Update only section of errmsk3 related to VF2PF */
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errmsk3 &= ~ADF_GEN2_ERR_MSK_VF2PF(ADF_GEN2_VF_MSK);
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errmsk3 |= ADF_GEN2_ERR_MSK_VF2PF(sources | disabled);
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3);
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/* Return the sources of the (new) interrupt(s) */
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@@ -193,8 +193,12 @@ static u32 disable_pending_vf2pf_interrupts(void __iomem *pmisc_addr)
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3);
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, errmsk5);
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errmsk3 &= ADF_DH895XCC_ERR_MSK_VF2PF_L(sources | disabled);
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errmsk5 &= ADF_DH895XCC_ERR_MSK_VF2PF_U(sources | disabled);
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/* Update only section of errmsk3 and errmsk5 related to VF2PF */
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errmsk3 &= ~ADF_DH895XCC_ERR_MSK_VF2PF_L(ADF_DH895XCC_VF_MSK);
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errmsk5 &= ~ADF_DH895XCC_ERR_MSK_VF2PF_U(ADF_DH895XCC_VF_MSK);
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errmsk3 |= ADF_DH895XCC_ERR_MSK_VF2PF_L(sources | disabled);
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errmsk5 |= ADF_DH895XCC_ERR_MSK_VF2PF_U(sources | disabled);
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3);
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ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, errmsk5);
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