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drm/i915: pass dev_priv explicitly to PIPE_FRMCOUNT_G4X

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Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_FRMCOUNT_G4X register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/747124e5eebdb58b06d70a0aae0af4dd7e6b7d86.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2024-06-04 18:25:47 +03:00
parent 446db74bd3
commit 8edbb0ee17
4 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/i915/display/intel_vblank.c
+1 -1
View File
@@ -126,7 +126,7 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
if (!vblank->max_vblank_count)
return 0;
return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(pipe));
return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(dev_priv, pipe));
}
static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
drivers/gpu/drm/i915/gvt/display.c
+1 -1
View File
@@ -647,7 +647,7 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
}
if (pipe_is_enabled(vgpu, pipe)) {
vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(dev_priv, pipe))++;
intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
}
}
drivers/gpu/drm/i915/i915_reg.h
+1 -1
View File
@@ -2176,7 +2176,7 @@
/* GM45+ just has to be different */
#define _PIPEA_FRMCOUNT_G4X 0x70040
#define _PIPEA_FLIPCOUNT_G4X 0x70044
#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
/* CHV pipe B blender */
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+4 -4
View File
@@ -142,10 +142,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B));
MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C));
MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP));
MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A));
MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B));
MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C));
MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP));
MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_A));
MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_B));
MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_C));
MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, _PIPE_EDP));
MMIO_D(CURCNTR(dev_priv, PIPE_A));
MMIO_D(CURCNTR(dev_priv, PIPE_B));
MMIO_D(CURCNTR(dev_priv, PIPE_C));